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`
` CROSSROADS EXHIBIT 2308
`Oracle Corp., et al v. Crossroads Systems, Inc.
` IPR2014-01207 and IPR2014-1209
`
`CROSSROADS EXHIBIT
`Oracle Corp. v. Crossroads Systems, Inc.
`IPR2015-0(cid:1005)(cid:1004)(cid:1010)(cid:1010)
`
`2308
`
`

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`
`errazano Software Development
`
`Confldcntlnl Document
`
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`1. Introduction
`
`This document gives an overview of the methods, processes, and requirements involved in the software
`development effort for the Verrazano Bridge. it is meant as an overview intended to provide the basic
`gutdelmes for development, and as such is subject to change as the implementation evolves.
`
`2. Overview
`
`2.1 Product Hardware Description
`The target hardware is an embedded system centered around the Intel i960RP processor. Incorporated on
`the i960 bus are program memory, flash memory, a serial UART. and a l0baseT Ethernet controller. The
`primary PCI bus from the i96ORP will have an HP Tachyon Fibre Channel controller, using the Interphase
`TPI PCI interface, and 2MB DRAM for data buffering. This DRAM will interface to the PCI bus via a
`custom interface designed in house. The secondary PCI bus will have the Symbios S3C875 PCI SCSI
`controller.
`
`
`
`
`Specific details of the hardware architecture and desi 3» can be found in the Verrazano Requirements
`Document, and in
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`2.2 Prototype Description
`To accelerate software development and to allow for software development to be overlapped with hardware
`development, a PC based prototype platform will be used. Functionally, the PC will be used for the PCI
`bus and system memory. The host processor will not be used except for limited debugging purposes. The
`processor used will be the Intel Cyclone board with the i96OJX Squall module. This will have 2MB of
`DRAM for program memory. The PLX 9060 PCI bridge on the Cyclone will allow for "'
`‘acing the 960
`processor to the FC and SCSI devices over the PCI bus. The Fibre Channel interface w.
`he lnterphase
`Tachyon based PCI adapter. The SCSI interface will be the Symbios SYM53C875 PCI a...._.-ter. Serial
`communication, flash memory, and other basic functionality is provided by the Cyclone board.
`This provides an architecturally sirnilar platform using essentially identical core components for
`development. Porting to the Verrazano hardware platform will require changes limited to the PCI bridge,
`memory and device mapping, and serial and other peripheral interfaces. The core driver and bridge code
`will remain unchanged.
`‘
`
`2.3 Design Philosophy
`0
`‘C’ Code base
`
`0 Modular design
`0
`Pass-though, event driven architecture
`0
`Use Existing 05. Drivers. Protocol Stacks as possible
`Design for performance. future portability, maintainability
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`3. Core Software Modules
`
`3. 1 Boat Code
`
`At system boot. code will, be required to initialize the hard» are, perform basic system testing. and load the
`mntime code. The expectation is that this will consist in large part of modules available from Intel
`(mon960) and the nintirne OS (currently Vxworks). Portions of this code will be modified and extended to
`support hardware specific characteristics which are TBD.
`
`Requirements:
`0
`Initialize hardware
`
`-
`-
`0
`
`Run boot diagnostics
`Set Processor, PCI address mapping
`Initialize and start Vxworks. core software
`
`3.2 Diagnostics
`In addition to the power on self test code executed at boot time. further diagnostics will be required for
`manufacturing test, field diagnosis. and returned unit test. These tests should be more extensive than the
`POST, and should include tests for all major subsystems of the Verrazano board. Diagnostics should be
`accessible from the serial console. TELNET via Ethernet, and SNMP via Ethernet. Future extensions
`should include accessibility via SCSI and Fibre Channel via FC«IP.
`
`Requirements:
`One base test suite is desired. covering:
`Manufacturing Test
`Field Test
`Retum Unit Test
`Processor test
`
`Memory test
`PCI test
`
`‘
`Buffer memory test
`Tachyon test - internal loopbaclt. electrical (GLM) wrap, external loopback
`Symbios test - internal loopback, external loopback
`Ethernet adapter test — internal loopback external loopback
`
`3.3 Kernel
`
`Currently Vxworks from Wind River Systems is the targeted runtime 08. Future ports may be targeted for
`Ix Works.
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`3.4 FC Driver
`
`The Fibre Channel driver will be based on the current ICS FC DDK. Modifications may be made to the
`initialization and FC—4 layers. The interfaces to this code will be defined in section 4.2 of this document.
`
`The FC driver provides the following functionality:
`0 Manage logins and Iogouts
`- Manage FC-4 exchanges
`0 Activation of new exchange for each FCP command
`0 Manage FCP comma.nd(exchange) through all phases for that command
`-
`Provide means for FC-4 to do process login for an FCP attached device
`0
`Receive all FC-4 data commands
`- Manage exchanges
`- Activation and Deactivation of exchanges
`-
`assigmnent of X_lD
`I Manage sequences
`-
`Initiation and termination of sequences
`0
`SEQ_lD assignment
`0 Managing sequence initiative
`0 Manage EE credit
`-
`All FC-2 functionality
`
`3.5 SCSI Driver
`
`The SCSI driver will consist of two parts. The SCSI state machines will be implemented in the Syrnbios
`SCRIPTS language, which runs on the 875 internal processor. This code will interface with a higher layer
`interface running on the i960 processor. The interfaces to this code will be defined in section 4.3 of this
`document.
`
`The SCSI dnver provides the following functionality:
`0
`Provide SCSI initiator support with a single SCSI ID
`0 Manage Commands and Messages to targets
`0 Manage DMA to/from buffer memory
`Provide SCSI target support
`0
`Respond to multiple target IDs
`0
`Process Commands and Messages
`0 Manage DMA to/from buffer memory
`0 Manage all SCSI bus phases and transitions
`0 Manage Synchronous, wide. and fast negotiation
`
`0
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`3.6 Bridge Code
`The Bridge code provides for the conversion and transport of data and commands between FCP and SCSI
`devices. This code should be event driven. of a pass-though design and use a store and forward method of
`data transport. Major functionality is defined below. Additional operational characteristics are outlined in
`the Verrazano Requirements Document.
`
`Requirements:
`o
`Process incoming CDBS from FC4 and SCSI layers
`Manage command and data transfer between FCP and SCSI drivers
`Manage data buffers and internal command structures
`0 Manage FC4 interface
`-
`Translate protocols from FCP to SCSL2
`0
`Translate address information between FC and SCSI devices
`
`0 0
`
`3.6.1 Architectural Overview
`
`Figure 3.ldiagrams the core processes and program flow within the bridge. Three areas of functionality are
`dragrammed. for FCP and SCSI processes. These are:
`
`0
`-
`0
`
`Event handling ’
`Bndge processing
`Request handling
`
`Event handlers process incoming requests from the PCP or SCSI interfaces and route these requests to the
`appropriate bridge module. The bridge modules handle the creation and management of buffer queues,
`address translation, and protocol translation. The request handlers initiate transfers on the PCP or SCSI
`interface as required by the other modules. Further description of these modules and their cc-nonents is
`provided in the following sections.
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`SCSI RECEIVE EVENT
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`SCSI sums.
`FCP_STATUS.
`FCP_DATA M
`Data In
`
`
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`
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`FCP RECEIVE EVENT
`
`.'
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`FCP SEND REQUEST
`
`
`SCSI SEND REQUEST
`
`
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`Figure 3.1- Core processes and now
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`Figure 3.1 illustrates control flow for management commands. Management commands are those ,
`commands that are processed by the bridge directly. and not passed through to the alternate interface. This
`capability is to be provided to support diagnostics, configuration. and in—band management through the FCP
`and SCSI interfaces. Similar interfaces to the Management Command Service will be provided for out of
`band management. via the Ethernet and serial interfaces.
`
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`Figure 3.2 - Management Commands Control Flow
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`Certain other cases exist to the normal flow of execution. Chief among these is the case wiiere an
`FCP__CMND Write is received. In order to reduce inactive time on the SCSI bus. data is prc-fetched. This
`is exhibited in Figure 3.3. The bridge module snoops the command, andfifnecessary, allocates buffers and
`requests data from the PCP device before generating the SCSI command. Subsequent data transfers and
`status phases for this command proceed normally.
`
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`Figure 3.3 - FCP Write with pre-fetch
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`3.6.2 Buffer Management
`
`System memory is available both in the 960 local memory space or in PCI memory space. Hardware
`performance dictates that highest performance is available when a device requiring memory ‘reads from
`nearest RAM‘. Accordingly, DMA read lists for the Tachyon will be located in PC! buffer memory, and
`Tachyon write lists in program memory. Interrupt structures and Bridge command suuctures will reside in
`program memory. Although these lists will be read by the Tachyon and Symbios part, it is likely that more
`read operations will be performed by the 960.on the CD13 elements. Data buffering will be in the PC!
`buffer memory.
`
`Primary Data elements:
`
`Data buffers
`
`- Allocated sequentially
`0 2K each
`
`- In 2MB PCI Buffer memory
`- Memory is shared with Tachyon DMA lists, so less than 1024 buffers available
`
`Bridge command elements
`- Allocated in program memory
`0 Number allocated limits the number of outstanding IO requests
`0 512 Allocated
`
`0 Max 480 targets (Wide SCSI targets times LUNS)
`- Average queue depth per target very near 1
`- About 96 bytes per, total allocation 49,152 Bytes
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`3.6.3 Protocol Translation
`
`Protocol translation is perfonned by the core bridge code. This involves the translation of a CD8
`(Command Descriptor Block) being convened between SCSX and FCP. Generally, the structure of the CDB
`IS the same in both cases. Changes to the CDB may have to be made to the LUN field when LUN
`addressing is required. The structure of the FCP_CMND and CDB is shown in Table 3.land Table 3.2.
`
`Table 3.1 - FCP__CNMI) Information Unit
`
`
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`Table 3.2 - SCSI Command Descriptor Block
`
`
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`3.6.4 Address Translation
`
`By default, the bridge will address in ‘Direct Addressing Mode’ with the mapping shown inTable 3.3 and
`Table 3.4. Configuration will allow for FC AL_PA to be changed, however, the LUN value will map
`directly to the SCSI LUN. Configuration will also allow for specific SCSI target addresses to be disabled.
`This reduces the range of available addresses, but allows for attaching other devices to the SCSI bus.
`
`Table 3.3- Default Direct Address Map, FCP—>SCSI (Narrow)
`
`SCSI Address
`SCSI Tare! 0, LUN 0
`SCSI Tare! 1. LUN 0
`SCSI Taret 2, LUN 0
`
`
`
`
`errazano AL_PA
`FC Address
`
`LUN 0
`
`LUN l
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`LUN 2
`
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`SCSI T et 0. LUN!
`SCSI Tare: I. LUN 1
`SCSI Tarct 2, LUN 1
`
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`SCSI Taret 7 Unavailable (Bride Initiator ID
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`Optionally, Ordered Addressing niode can be enabled. This mode will perform discovery on each side of
`the bridge. and use the resulting data to build an address map between the busses. This results in an ordered
`list of addresses with no apparent gaps between devices. Although this provides automatic configuration,
`no allowance is given for hot plugging devices or any dynamic change of addressing. Example tables are
`shown in Table 3.5 and Table 3.6.
`
`Table 3.5 - Ordered Address Map, FC->SCSI
`
`
`
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`discovered BUS=SCS1 TARGETJ-UN
`
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`Table 3.6 - Ordered Address Map, SCSI->FC
`
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`SCSI Address
`I" discovered FC AL_PA, LUN 0
`Taret 0, LUN 0
`2 ' discovered FC AL_PA, LUN O
`Taret 1, LUN 0
`3 ' discovered FC AL_PA, LUN 0
`Taret 2, LUN O
`
`
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`Tar et N, LUN N
`' discovered FC AL__PA. LUN O
`
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`
`A maximum of 480 translation elements are required for each direction. This is the maximum number of
`logical units that can be addressed. This is determined by using the maximum number of usable SCSI
`targets times the number ofLUNS. Wide SCSI allows 16 SCSI lDs, one of which must be used as the
`bridge initiator ID. Each target can address 32 LU‘Ns.
`
`Each FC->SCSl entry is 7 words. Each SCSI->FC element is 8 words. Thus, the total required memory for
`address tables is 7200 bytes. These tables will reside in local 960 memory.
`
`3. 7 Ethernet Driver
`
`WindRiver currently has plans to supply the Epilogue driver for the AMD LANCE Ethernet chip.
`lt is expected that this can be modified to support the PC-NET chip in LANCE compatibility mode. Further
`investigation is ongoing.
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`3.8 Configuration
`Verrazano will require configuration for various reasons. The prototype device will allow
`configuration though the serial interface. Ethernet via TELNET will be implemented in the first release.
`Subsequent releases will support SNMP and potentially HTTP, FC and SCSI interfaces.
`
`3.8.1 Configurable Optlons
`A number of configurable parameters are required. They are listed below, and grouped into major
`categories.
`
`3.8.1.1 FCP Options
`0
`Use/Set Hard Address (A.L__PA)
`0
`Participate if Hard Address unavailable
`0
`Override World Wide Address (IEEE)
`
`3.8.1.2 SCSI Options
`0
`Set ID for SCSI Initiator
`
`0
`a
`-
`0
`0
`
`Use multiple SCSI response IDs
`Set IDs for SCSI Target response
`Set general SCSI parameters (fast/disconnect/sync negotiation/etc.)
`Set SCSI Narrowfwide
`Use CDB LUN field
`
`3.8.1.3 Bridge Option:
`0
`Use Direct Address Method
`
`0
`
`0
`
`0
`I
`0
`
`Specify/Enter Address Map
`-
`- Use default Address Map
`Use Ordered Address Method
`
`Perform FCP Discovery
`-
`Perform SCSI Discovery
`0
`Use Target Addressing (LUN 0 Only)
`-
`FCP Target Addressing
`0
`SCSI Target Addressing
`Set Management Command method (LUN 0, LUN FF. Group Code, Disable)
`Select FCP LUN format
`Set Buffer Memory parameters
`0 Data Buffer Size
`0
`Set Tachyon list parameters
`0
`Set Symbios list parameters
`
`3.8.1 .4 Mlsoollanoous
`0 Override Ethernet IEEE address
`0
`Link I-‘C/Ethernet IEEE addresses
`
`0
`0
`
`Set default serial parameters
`Disable diagnostics
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`3.8.2 Serial Console
`
`The Serial Console will provide for:
`- Menu based configuration
`- Statistics repons
`0 EEPROM Download
`
`0 Debugging Vxworlcs Interface
`
`3.8.3 Telnet
`
`Access to the same options and control given through the serial interface will be provided through
`Ethernet based TELNET. (future FC-IP)
`
`3.8.4 FTP
`
`Firmware download will be provided through Ethernet FTP.
`
`3.8.5 SNMP
`
`MIB based configuration and statistics via SNMP (Ethernet, future FC-IP)
`
`3.8.6 HTTP
`
`Configuration, management available via HTTP in future release.
`
`&9Ahnqxnwm
`
`3.9.1 SNMP
`MIB-ll definition TBD
`
`3.9.2 HTTP
`
`TBD. in future release
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`4. Software Interfaces
`
`4.1 Common Structures
`
`There is a general one to one correlation between SCSI and PCP commands in the bridge. Cases
`where this is not so include management commands as well as commands with invalid addressing and
`potentially other errors. Thus, in order to simplify allocation and increase performance, it is desirable to
`combine PCP and SCSI command structures into one element.
`
`Bridge Command Structure: (24 words)
`QUEUE
`qlink;
`FCP_CMND
`FCP_Cornmand
`SCSl_CDB
`SCSl_Command
`WORD
`FCP__t'lags
`WORD
`SCSl__flags
`WORD
`FCP___burst_length
`WORD
`FCP_relative_ofi‘set
`WORD
`FCP_total_data
`WORD
`SCSI_total__data
`WORD
`correlation__id
`FQXID
`fqxid
`QUEUE
`data_q_ptr
`WORD
`data_length
`
`Queue pointer info
`FCP Command Infonnation Unit
`SCSI Command descriptor Block
`Flags for I-‘CP state information
`Flags to indicate phase information
`Burst size for FCP transfers
`FCP data relative offset
`Data size expected for FCP
`Data size expected for SCSI
`Correlation ID for FC4
`D_ID, S_ID. OX_ID, RX__lD
`Pointer to data buffer queue entries
`number of allocated data blocks
`
`FCP->SCSl Address Translation Structure: (1 words)
`FCP_LUN
`FCP__LUN__Value;
`SCSLADDR
`SCSI__Valuc;
`
`LUN contents
`SCSI BUS:TARGET:LUN
`
`SCSI->FCP Address Translation Structure: (8 words)
`FCP_AL_PA
`N_PORT_ID
`FCP_LUN
`FCP_LUN_Value
`SCSl_ADDR
`SCSI_Value
`
`FC Address
`LUN Value
`SCSI BUS:TARGE'l':I.UN
`
`4 words
`8 words
`4 words
`l word
`l word
`1 word
`1 word
`l word
`l word
`l word
`4 words
`4 words
`1 word
`
`6 words
`l word
`
`1 word
`6 words
`1 word
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`'-‘.2
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`4.2 FCP.$Bridge Interface
`The FC interface is essentially that of the FC DDK, with some extensions. Primary elements are
`shown below.
`
`fc4_send__req()
`fc4_process_login()
`fc4_process__logout0
`
`Send an FC—4 request.
`Do process login for FC»4's that require process login.
`Do process log out for FC-4'5 that require process log out.
`
`fc4__register()
`
`fc4_remove()
`
`fc4__tx_callback
`fc4__rx_callback
`fc4___freeBufs
`fc4_REQ structure {
`
`Register an PC-4 type to the F02 layer. Registers the callback routines for the
`given FC-4. Enables this FC-4 to start receiving unsolicited data for this I-‘C-4
`type.
`Remove an I-‘C-4 type that was previously registered to the FC-2 layer with the
`fc4_register() function. Removes the information registered with fc4_register()
`and disables the ability to receive unsolicited data for this FC-4 type.
`Provides status of fc-1 send request.
`Provide status and transfer PCP command received to bridge
`Free receive buffer elements
`
`fc4_type
`profile
`s_id
`d_id
`total_sizc
`fcp_cmd
`fcp_status
`data___info
`fc4__context
`
`.3
`
`Extensions:
`FCP_EventHandler
`
`ISR, DMA service routine
`
`4.3 SCSI->Bridge Interface
`The interface between the SCSI driver module and Bridge code will be generally consistent with that
`specified by the SCSI-3 SIP specification (ANSI drafi X3Tl0 Project 856D R10).
`
`All functions will be passed a pointer to the current Bridge Command Structure.
`
`Primary functions are as follows:
`SCSI_EventHandler
`SCSl_Command__In
`SCSl_Command_Out
`SCSI_Data_ln
`SCSl_Data_Out
`SCSl_Status_ln
`SCSl_Status_Out
`SCSl_Message_ln
`SCSl_Message_Out
`
`ISR, DMA service
`Initiate SCSI command to target device
`Process target command from initiator
`Process DMA Data In to buffer memory
`Process DMA Data Out from buffer memory
`Process SCSI Status message (Initiator Role)
`Process SCSI Status message (Target Role)
`Process other message (Initiator Role)
`Process other message (Target Role)
`
`Confidential Document
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`lnfinity Cornmstor, LLC
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`4.4 Protocol Stacks
`The initial release ofVex1-azano will use off the shelf protocol stacks. Some modification may be
`necessary depending on code availabllity. Desired elements are:
`
`TCP/IP
`SNMP
`TELNET
`FTP
`
`HTTP (future)
`
`COOOO
`
`Vendors providing stacks are currently being researched and include:
`-
`US Software
`EBS lnc.
`Pacific Softworks
`Epilogue
`XLNT
`
`Accelerated Technology
`
`This code may have large up-from and royalty requiremens. A large body of public domain software is also
`available. Switching to Infinity generated code is a possible future cost reduction.
`
`Confidential Document
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