ORACLE EXHIBIT 1002
`
`ORACLE EXHIBIT 1002
`
`PART 3
`
`PART 3
`
`
`
`
`
`ORACLE EXHIBIT 1002
`
`PART 3
`
`PART 3
`
`
`
`
`
`'“K)9DW3788
`
`PCUUS90/0471]
`
`-80-
`
`To commence the transfer of the next segment of the
`block of data to be transferred,
`the master drives
`Ds0* low 739 and, after a predetermined period of
`time, drives DSO* high 741.
`'-In response to the
`transition of DSO* from high to low,
`respectivelyv739
`and 741, the slave latches the data being broadcast by
`the master over data lines D00 through D31, 743.
`The
`master places the next
`segment of
`the data to be
`transferred on data lines D00 through D31, 745,
`_
`awaits receipt of a DTACK* signal
`in the form of a
`high to low transition, 747.
`after
`The slave then drives DTACK* low, 749, and,
`a predetermined period of time, drives DTACK* high,
`751.. The data latched by the slave, 743,
`is written
`to the device selected to store the data and the
`device address is incremented 753.
`The slave waits
`for another transition of DSO* from high to low 737.
`The transfer of data will continue in the above-
`described manner until all of
`the data has been
`transferred from the master to the slave.
`After all.
`of
`the data has been transferred,
`the master will
`release the address lines, address modifier
`lines,
`data lines,
`IACK* line, LWORD*
`line and DSO*
`line,
`755.
`’The master will
`then wait for receipt of a
`DTACK* high to low transition 757.
`The slave will
`drive DTACK*
`low,
`759 and, after
`a predetermined
`period of time, drive DTACK* high 761.
`In response to
`the receipt of the DTAcK* high to low transition, the
`master will drive As* high 763 and then release the
`As* line 765.
`
`Fig.
`is
`a
`flowchart
`8, parts
`A
`through C.
`illustrating the operations involved in accomplishing
`the fast
`transfer protocol BLOCK READ cycle.
`To
`initiate-a BLOCK READ cycle, the master broadcasts the
`memory address of the data to be transferred and the
`address modifier across the DTB bus 801.
`The master
`
`sussnturs sues .
`
`Oracle Ex. 1002, pg. 1201
`
`
`
`WO 91/03788
`
`PCT/US90/0471 1
`
`_81_
`
`drives the LWORD* signal low and the IACK* signal high
`801.
`
`As noted previously, a special address modifier
`indicates to the slave module that the fast transfer
`
`'protocol will be used to accomplish the BLOCK READ.
`The slave modules connected to the DTB receive the
`
`address and the address modifier broadcast by the
`
`master across the bus and receive LWORD* low and IACK*
`
`high 803. Shortly after broadcasting the address and
`address modifier 801, the master drives the AS* signal
`low 805.
`607.
`
`The slave modules receive the As* low signal
`
`Each slave individually determines whether it
`
`will participate in the data transfer by determining
`whether the broadcasted address is valid for the slave
`If the address is not valid,
`the
`
`in question 809.
`data transfer does not involve that particular slave
`
`the data transfer
`and it ignores the remainder of
`4
`cycle.
`The master drives WRITE* high to indicate that the
`
`transfer cycle about to occur is a READ operation 811.
`The slave receives the WRITE* high signal 813 and,
`knowing that the data transfer operation is a READ
`operation, places the first segment of the data to be
`transferred on data lines D00 through D31 819.
`The
`master will wait until both DTACK* and BERR* are high
`
`818, which indicates that the previous slave is no
`longer driving the DTB.
`The raster then drives DSO* low 821 and, after a
`The »
`drives DSO* high 823.
`
`predete mined interval,
`master then awaits a high to low transition on the
`As
`shown in Fig.
`
`the
`8B,
`line 824.
`DTACK* signal
`slave then drives the DTACK* signal low 825 and, after
`a predetermined period of
`time, drives the DTACK*
`signal high 827.
`
`In response to the transition of DTACK* from high
`to low, respectively 825 and 827,
`the master latches"
`the data being transmitted by the slave over data
`
`sussmune sum
`
`Oracle Ex. 1002, pg. 1202
`
`
`
`W091/03788
`
`PCI'IUS90/0471]
`
`-82-
`
`The data latched by the
`lines n'oo through D31, 331.
`master, 831,
`is written to a device, which has been
`selected to store, the data the device address
`is
`incremented 833.
`A
`
`The slave places the next segment of the data to be
`
`transferred on data lines D00 through D31, 829, and
`then waits for another transition of DSO* from high to
`low 837.
`'
`V
`
`To commence the transfer of the next segment of the
`block of data to be transferred,
`the master drives
`DSO*
`low 839 and, after a predetermined period of
`time, drives DSO* high 841. The master then waits for
`
`the DTACK* line to transition from high to low, 843.
`_The ‘slave drives nmczv law, 845, and, after a
`predetermined period of time, drives DTACK* high, 847.
`In response to the transition of DTACK* from high to
`low, respectively 839 and 841,
`the master latches the
`
`data being transmitted by the slave over data lines
`D00 through D31, 845. The data latched by the master,
`845,
`is written to the device selected to store the
`data,
`851
`in Fig.
`8C,
`and the device address
`is
`
`incremented. The slave places the next segment of the
`data to be transferred on data lines D00 through D31,
`849.
`,
`The transfer of data will continue in the above-
`described manner until all
`of
`the data
`to be
`
`transferred from the slave to the master has been
`
`written into the device selected to store the data.
`
`After all of
`
`the data to be transferred has been
`the master will
`
`written into the storage device,
`lines,
`release the address lines, address modifier
`data lines,
`the Izicrv line,
`the LWORD line and nso*
`line 852.
`The master will then wait for receipt of a
`DTACK* high to low transition 853.
`The_slave will
`drive DTACK* low 855 and, after a predetermined period
`.of time, drive DTACK* high 857.
`In response to the
`
`SUHSTITUTE SHEET
`
`Oracle Ex. 1002, pg. 1203
`
`
`
`W0 91/03788
`
`PC!‘IUS90/047] 1
`
`-33-
`
`receipt of
`
`the DTACK* high to low transition,
`
`the
`
`master will drive AS* high 859 and release the AS*
`line 861.
`
`implement
`transfer protocol,
`a
`fast
`the
`To
`conventional 64 mA tri—state driver is substituted for
`
`the 48 mA open collector driver conventionally used in
`
`VME slave modules to drive DTACK*.
`
`Similarly,
`
`the
`
`conventional VMEbus data drivers are replaced with 64
`The latter
`
`.mA tri-state drivers in SD-type packages.
`
`modification reduces the ground lead inductance of the
`reduces
`actual driver package
`itself
`and,
`thus,
`“ground bounce" effects which contribute to
`between data,
`
`DSO* and DTACK*,
`
`In addition,
`
`skew
`
`signal
`
`return inductance along the bus backplane is reduced
`
`by using a connector system having a greater number of
`
`ground pins so as to minimize signal return and mated-
`
`pair pin inductance. One such connector system is the
`connector,
`
`Model No. 420-8015-
`
`“High Density Plus“
`
`000, manufactured by Teradyne Corporation.
`I
`
`Oracle Ex. 1002, pg. 1204
`
`
`
`W0 91/03788
`
`PCH7US9&flM71t-
`
`The parity FIFOs 240, 260 and 270 (on the network
`controllers
`and
`and
`(on
`110),
`544
`554
`storage
`
`processors 114) are each implemented as an ASIC. All
`
`the parity FIFOs are identical, and are configured on
`
`power-up or-during normal operation for the particular
`
`function desired.
`
`The parity FIFO is designed to
`
`allow speed matching between buses of different speed,
`
`and to perform the parity generation and correction
`for the parallel SCSI drives.
`
`The FIFO comprises two bidirectional data ports,
`Port A and Port 3, with 36 x 64 bits of RAM buffer
`between them.
`Port A is 8 bits wide and Port B is 32
`
`bits wide.
`
`The RAM buffer is divided into two parts,
`each 36 x 32 hits,
`
`designated RAM X and RAM Y.
`
`The
`
`two ports
`
`the buffer
`Vaccess different halves of
`alternating to the other half when available. when
`
`the chip is configured as a parallel parity chip (e.g.
`
`one of the-FIFOs 544 on SP 1143), all accesses on Port
`
`3 are monitored and parity is accumulated in RAM X
`and RAM Y alternately.
`
`The chip also has a CPU interface, which may be 8
`or 16 bits wide.
`
`In 16 bit mode the Port A pins are‘
`
`used as the most significant data bits of the CPU
`
`interface and are only actually used when reading or
`
`writing to the Fife Data Register inside the chip.
`
`A REQ, ACK handshake is used for data transfer on
`both Ports A and. B.
`The chip may be configured as
`either a master or a slave on Port A in the sense
`
`that,
`
`in master node the Port A ACK / RDY output
`
`signifies that the chip is ready to transfer data on
`
`Port A, and the Port A REQ input specifies that the
`
`slave is responding.
`
`In slave node, however, the Port
`
`A REQ input specifies that the master requires a data
`
`$_llB_S_T!TllTE SHEET
`
`Oracle Ex. 1002, pg. 1205
`
`
`
`\V()9l/03788
`
`PCT/US90/04711
`
`-35-
`
`transfer, and the chip responds with Port A ACK / RDY
`
`The chip is a master on Port
`when data is available.
`B since it raises Port B REQ and waits for Port B ACK
`
`to indicate completion of the data transfer.
`
`EI£NAL_D£§QBIEIIQNfi
`
`Port A 0-7, P
`
`Port'A is the 8 bit data port. Port A P, if used,
`is the odd parity bit for this port.
`
`A Req,
`
`A Ack/Rdy
`
`These two signals are used in the data transfer
`mode to control the handshake of data on Port A.
`
`uP Data 0-7, uP Data P, uPAdd 0-2,
`
`CS
`
`These signals are used by a microprocessor
`
`to
`
`address the programmable registers within the chip.
`
`The odd parity signal uP Data P is only checked when
`data is written to the Fifo Data or Checksum Registers
`and microprocessor parity is enabled.
`
`Clk
`
`The clock input
`
`is used to generate some of the
`
`is expected to be in the 10-20 Mhz
`
`chip timing. It
`range.
`
`Read En, Write En
`
`During microprocessor accesses, while CS is true,
`these
`the
`direction of
`the
`
`signals
`
`determine
`
`microprocessor accesses. During data transfers in the
`
`these signals are data 'strobes used in
`WD mode
`conjunction with Port A Ack.
`'
`
`SUBSTITIITE SHEET
`
`Oracle Ex. 1002, pg. 1206
`
`
`
`W0 9]/03788
`
`PC!‘IU590/0471 I
`
`-35-
`
`Port B 60-07, 10-17, 20-27, 30-37,
`Port B is a 32 bit data port.
`Port B OP is the parity of
`
`0P—3P
`
`There is one odd
`
`parity bit for each byte.
`bits 00-O7, PortB 1P is the parity of hits 10-17, Port-
`
`B 2P is the parity of hits 20-27, and Port B 3P is the
`
`parity of bits 30-37.
`
`B Select, B Reg, E Ack, Parity Sync, B Output Enable
`These signals are used in the data transfer mode to
`control the handshake of data on Port B. Port B Reg
`
`and Port B Ack are both gated with Port 3 select.
`
`The Port B Ack signal is used to strobe the data on
`the Port B data lines.
`The parity sync signal is
`
`used to indicate to a chip configured as the parity
`
`chip to indicate that-the last words of data involved
`in the parity accumulation are on Part B.
`The Port E
`data lines will only be driven by the Fifo chip if all
`conditions are met:
`
`of the following
`a.
`the data
`
`transfer is from Port A to Port B;
`
`b.
`
`c.
`
`d.
`
`Reset
`
`the Port
`
`the Port
`
`B select signal is true;
`
`B output enable signal is true; and
`
`the chip
`is not configured as the parity chip
`the Parity
`or it is in parity correct mode and
`.sync signal is true.
`
`This signal resets all the registers within the
`
`chip and causes all bidirectional pins to be in a high
`impedance state;
`
`DE§§BlRIIQN_Q£_QEEEAIIQE
`
`a
`Normally the chip acts as
`’ ngrma1_Lm§;g;ign.
`A FIFO is simulated by using two
`‘simple FIFO chip.
`RAM buffers
`in a
`
`It
`
`is
`
`simple ping-pong mode.
`
`that data is burst into
`intended, but not mandatory,
`or out of the FIFO on Part B. This is done by holding
`
`low and pulsing the Port B Abk
`Port B Sel signal
`signal. When transferring data from Port B to Port A,
`
`mum saw a
`
`Oracle Ex. 1002, pg. 1207
`
`
`
`W0 91/03788
`
`PCT/US90/047 1 1
`
`-37-
`
`data is first written into RAM X and when this is
`
`full,
`
`the data paths will he switched such that Port
`
`B may start writing to RAM Y. Meanwhile the chip will
`begin emptying RAM X to Port A.
`When RAM Yuis full
`
`and RAM X empty the data paths will he switched again
`such that Port B may reload RAM X and
`Port A may
`
`empty RAM Y.
`
`.
`
`£Q;t_A_§l5ge_Mgdg.
`
`This is the default mode and
`
`In this mode the
`the chip is reset to this condition.
`chip waits for a master
`such as one of
`the SCSI
`
`adapter chips 542 to raise Port A Request for data
`transfer.
`
`If data is available the Fifo chip will
`respond with Port A Ack/Rdy.
`.2Q££_A_H2_MQi£-
`The chip may be configured to run
`in the WD or Western Digital mode.
`In this mode the
`chip must be configured as a slave on Port A.
`It
`
`differs from the default slave node in that the chip
`with Read Enable
`Write Enable
`responds
`or
`as
`
`appropriate together with Port A Ack/Rdy. This mode
`is intended to allow the chip to be interfaced to the
`
`Western Digital 33C93A SCSI chip or the NCR 53C90 SCSI
`chip.
`
`2grt_A_fla§ter_Mgde. When the chip is configured as
`
`a master, it will raise Port A Ack/Rdy when it is
`ready for data transfer.
`This signal is expected to
`
`be tied to the Request input of a DNA controller which
`
`will respond with Port A Reg when data is available.
`
`In order to allow the DMA controller to burst,
`
`the
`
`Port A Ack/Rdy signal will only be negated after every
`8 or 16 bytes transferred.
`
`In parallel write
`
`mode, the chip is configured to be the parity chip for
`
`a parallel transfer from Port 3 to Port A.-
`mode,
`when Port B select and Port B Request are
`asserted, data is
`written into RAM X or RAM Y each
`
`In this
`
`time the Port B Ack signal is received. For the first
`
`_8_ll_B_STlTllTE SHEET
`
`R
`
`Oracle Ex. 1002, pg. 1208
`
`
`
`W0 91/03788
`
`PCI7US90NM7ll
`
`-33-
`
`128 bytes data is simply copied into the
`block of
`selected RAM. The next 128 bytes driven on Port B will
`be exclusive-0Red with the first 128 bytes.
`This
`
`procedure will be repeated for all drives such that
`The Parity
`the parity is accumulated in this chip.
`
`Sync signal should be asserted to the parallel chip
`
`together with the last block of
`
`128 bytes.
`
`This
`
`enables the chip to switch access to the other RAM and
`start accumulating a new 128 bytes of parity.
`E9rI_E_2aral1sl_Bsad_M2ds_:_§hs£h_Dara. This mode
`
`is set if all drives are being read and parity is to
`be checked.
`
`In this case the Parity Correct bit in
`the Data Transfer Configuration Register is not set.
`
`The parity chip will first read 128 bytes on Port A as
`in a normal read mode and then raise Port 8 Request.
`While
`it has
`this
`
`signal .asserted the chip will
`
`monitor the Port 8 Ask signals and exclusive—or the
`data on Port B with the data in its selected RAM. The
`
`Parity Sync should again be asserted with the last
`
`In this mode the chip will not
`block of 123 bytes.
`drive the Port B data lines but will check the output
`
`of its exclusive-or logic for zero.
`set at
`this time a parallel parity error will be
`
`If any hits are
`
`flagged.
`
`R9r1_E_2arallel_3sad_MQda_;_Q9rr§2t_Data-
`
`This
`
`mode is set by setting the Parity Correct hit in the
`
`In this case
`Data Transfer Configuration Register.
`the chip will work exactly as in the check mode except
`
`that when Port B Output Enable, Port B select and
`
`‘Parity Sync are true the data is driven onto the Port
`B data
`lines and a parallel parity check for zero is
`
`not performed.
`
`In the normal mode it is expected that
`A Eyte_§wap.
`Port B bits 00-07 are the first byte, bits 10-17 the
`
`second byte, bits 20-27 the third byte, and bits 30-37
`
`the last byte of each word. The order of these bytes
`
`gussmurasnm
`
`Oracle Ex. 1002, pg. 1209
`
`
`
`W0 91/D3788
`
`PC!‘/US90/0471 1
`
`-89-
`
`may be changed by writing to the byte swap bits in the
`configuration register such that the byte address bits
`are inverted.
`The way the bytes are written and read
`
`also depend on whether the CPU interface is configured
`as 16 or 3 bits.
`The following table shows the byte
`alignments. for the different possibilities for data
`transfer using the Port A Request
`/ Acknowledge
`handshake:
`CPU
`I/F
`
`Invert
`Addr 1
`
`Invert
`Addr 0
`
`Part B
`00-07
`
`Port B
`10-17
`
`Part B
`20-27
`
`Port B
`30-37
`
`3
`
`False
`
`False
`
`False
`
`True
`
`True
`
`False
`
`Tme
`
`True
`
`False
`
`False
`
`False
`
`True
`
`True
`
`False
`
`True
`
`True
`
`Port A
`byte 0
`
`Port A
`byte 1
`
`Port A -
`byte 2
`
`Port A
`byte 3
`
`Port A
`byte 0
`
`uProc
`byte 0
`
`Port A
`byte 1
`
`uProc
`byte 1
`
`Port A
`byte 1
`
`Port A
`byte 0
`
`Port A
`byte 3
`
`Port A
`byte 2
`
`uProc
`byte 0
`
`Port A
`byte 0
`
`uProc
`bytel
`
`Port A
`byte 1
`
`Port A
`byte 2
`
`Port A
`byte 3
`
`Port A
`byte 0
`
`Port A
`byte 1
`
`Port A
`byte 1
`
`uProc
`byte 1
`
`Port A
`byte 0
`
`uProc
`byte 0
`
`Port A
`byte 1
`
`Port A
`byte 2
`
`Port A
`byte 1
`
`Port A
`byte 0
`
`uProc
`byte 1
`
`Port A
`byte 1
`
`uProc
`byte 0
`
`Port A
`byte 0
`
`When the Fifo is accessed by reading or writing the
`Fifo Data Register through the microprocessor port in
`8 bit mode,
`the bytes are in the same order as the
`
`table above but the uProc data port is used instead of
`
`In 16 bit mode the table above applies.
`Port A.
` . If the data transfer is not
`
`a nultiple
`
`of
`
`32 words,
`
`or
`
`128
`
`bytes ,
`
`the
`
`microprocessor must manipulate the internal registers
`Port
`of the chip to ensure all data is transferred.
`A Ack and Port B Req are normally not asserted until
`
`SUBSTITUTE SHEET
`
`Oracle Ex. 1002, pg. 1210
`
`
`
`W0 9]/03788
`
`PCTIUS90/0471 I
`
`_gg_
`
`all 32 words of the selected RAM are available. These
`signals may be forced by writing to the appropriate
`RAM status bits of the Data Transfer status Register.
`
`When an odd length transfer has taken place the
`wait
`both ports
`are
`microprocessor must
`until
`
`It
`quiescent before manipulating any registers.
`should then reset both of the Enable Data Transfer
`
`bits for Port, A and Port B in the Data Transfer
`
`Control Register.
`
`It must then determine by reading
`
`their Address Registers and the RAM Access Control
`Register whether RAM X or RAM Y holds the odd length
`data.
`It should then set the corresponding Address
`
`Register to a value of 20 hexadecimal, forcing the RAM
`full hit and setting the address to the first word.
`
`Finally the microprocessor should set the Enable Data‘
`Transfer bits to allow the chip to complete the
`transfer.
`
`At this point the Fifo chip will think that there
`
`are now a full 128 bytes of data in the RAM and will
`
`transfer 128 bytes if allowed to do so. The fact that
`
`some of
`
`these
`
`128 bytes are not valid must be
`
`‘recognized externally to the FIFO chip.
`
`BL
`f
`
`IT
`'
`
`'
`
`‘
`
`V
`
`r
`
`W
`
`Register Address 0.
`
`This register is cleared by
`
`the reset signal.
`Set if data transfers are to
`Bit
`0
`E2_M9d§-
`use
`the Western Digital .‘WD33C93A
`protocol, otherwise
`the Adaptec
`6250
`protocol will he used.
`
`if this chip is to
`Set
`Parity Chip.
`accumulate Port B parities.
`
`if the parity
` . set
`chip is to correct parallel parity on
`Port B.
`
`$l.'BsTlT“TE 3”‘
`
`Oracle Ex. 1002, pg. 1211
`
`
`
`WO 91/03788
`
`PCT/US90/04711 -
`
`-91-
`
`the
` . If set.
`microprocessor data bits are combined
`with the Port A data bits to effectively
`produce a 16 bit Port. All accesses by
`the microprocessor as well as all data
`transferred using the Port A Request and
`Acknowledge handshake will
`transfer 16
`bits.
`
`to
` - ’ Set
`invert the least significant bit of Port
`A byte address.
`
`to
`Set
`Invert 29;; 3 byte address 1.
`invert the most significant bit of Port
`A byte address.
`*
`
` - Set to enable the
`carry out of the 16 bit checksum adder to
`carry back into the least significant bit
`of the adder.
`
`to this bit will
`Béigt. Writing a 1
`reset
`the other
`registers. This bit
`resets itself after a maximum of 2 clock
`cycles and will
`therefore normally be
`read as a 0. No other register should be
`written for a minimum of 4 clock cycles
`after writing to this bit.
`
`r
`
`'
`
`R
`
`Register Address 1.
`
`This register is cleared by
`
`the reset signal or by writing to the reset bit.
`Bit
`0 . Set to
`enable the Port A Req/Ack handshake.
`
`Bit
`
`Bit
`
`1
`
`2
`
` .v Set to
`enable the Port B Req/Ack handshake.
`
`If set, data transfer,
`£gzt_A_tg_£g:t_a.
`is from Port A to Part B.
`If reset, data
`transfer is from Port 3 to Port A.
`In
`order
`to avoid any glitches
`on
`the
`request
`lines,
`the state of
`this bit
`should not be altered at the same time as
`the enable data transfer bits 0 or
`1
`above.
`
`suasntufn sum
`
`Oracle Ex. 1002, pg. 1212
`
`
`
`WO 91/037118
`
`'
`
`‘
`
`PCWUS90/04711 -
`
`-92-
`
` . Set if parity
`is to be checked on the microprocessor
`interface.
`It will only be checked when
`writing to the Fifo Data Register or
`reading from the Fifo Data or Checksum
`Registers,
`or
`during
`a
`Port
`A
`Request/Acknowledge transfer in 16 bit
`mode.
`The chip will, however, always
`re-generate parity ensuring that correct
`parity is written to the RAM or read on
`the microprocessor interface.
`
` . Set if parity is
`to be checked on Port A.
`It is checked
`when accessing the Fifo Data Register in
`16 bit mode,
`or
`during
`a Port
`A
`Request/Acknowledge transfer.
`The chip
`will, however, always re—generate parity
`ensuring that correct parity is written
`to the
`RAM or
`read on.
`the Port A
`interface.
`
`Port B
` . Set if
`If it is
`data has valid byte parities.
`generated
`not
`set, _byte parity is
`internally to the chip when writing to
`the RAMs.
`Byte parity is not checked
`when writing from Port B, but always
`checked when reading to Port B.
`
`Set to enable writing
`§hggk§um_£na§1g.
`to the 16 bit checksum register.
`This
`register accumulates a 16 hit checksum
`for all RAM accesses, including accesses
`to the Pifo Data Register, as well as all
`writes to the checksum register.
`This
`bit must be reset before reading from the
`Checksum Register.
`
`if Port A is to
` . set
`operate in the master node on Port A
`during the data transfer.
`
`km_ua
`Register Address 2.
`This register is cleared hy
`the reset signal or by writing to the reset bit.
`
`Bit
`
`O
`
`Y. Set if any bits
`r
`i
`are true in the RAM X, RAM Y, or Port A
`byte address registers.
`
`sussmure SHEET
`
`Oracle Ex. 1002, pg. 1213
`
`
`
`W0 91/03788
`
`PCl'/US90/0471 1
`
`-93-
`
`if the
` . set
`uProc Parity Enable bit
`is set and a
`parity
`error
`is
`detected
`on
`the
`microprocessor interface during any RAM
`access or write to-the Checksum Register
`in 16 bit mode.
`
`Set if the Port A
`is set and a parity
`Parity Enable bit
`error is detected on the Port A interface
`during any RAM access or write to the
`Checksum Register.
`
`Set if
`.
`39;; B garallgl Rarity Ergo:
`the‘ parity
`the chip is configured as
`chip, is not in parity correct mode, and
`a non zero result is detected when the
`Parity Sync signal is true.
`It is also
`set whenever data is read out onto Port
`B and the data being read back through
`the
`bidirectional
`buffer
`does
`not
`compare.
`
` . Set
`whenever the data being read out of the
`RAMS on the Port B side has bad parity.
`
`BanLA22§§£_Q2ntrQl_&&$huu;_lBeadLflritei
`
`Register Address 3. This register is cleared by
`the reset signal or-by writing to the reset hit.
`The
`
`Enable Data Transfer bits in the Data Transfer Control
`Register must be reset before attempting to write to
`
`this register, else the write will be ignored.
`Bit
`0 . This bit is the
`‘
`least significant byte address bit.
`It
`is read directly bypassing any inversion
`done by
`the invert bit
`in the Data
`Transfer Configuration Register.
`
`29;; 5 byte address L. This bit is the
`most significant byte address bit.
`It is
`read directly bypassing any inversion
`done by the invert bit
`in the Data
`Transfer Configuration Register.
`
`Pgr; A :9 33M 2.
`accessing RAM Y,
`accessing RAM X .
`
`if Port A is
`Set
`and reset
`if it
`is
`
`SUBSTITUTE SHEET
`
`Oracle Ex. 1002, pg. 1214
`
`
`
`WO 91103788
`
`_
`
`PCT/US90/04711 '
`
`-94-
`
`if Rort s is
` .‘ Set
`accessing RAM Y,
`and reset
`if
`it is
`accessing RAM X .
`
`If the chip is configured to
`Lgng_fln;s:.
`transfer data on Port A as a master, and
`this bit
`is reset,
`the chip will only
`negate Port A Ack/Rdy after every 8
`bytes, or 4 words in 16 bit mode, have
`been transferred.
`If this bit is set,
`Port A Ack/Rdy will be negated every 16
`bytes, or 8 words in 16 bit mode.
`'
`
`Bits 5-7 ngt_nsg§.
`
`am .|]
`.!
`E
`Bnlxam.
`This register is cleared by
`‘Register Address 4.
`the reset signal or by writing to the reset bit.
`The
`Enable Data Transfer bits in the Data Transfer Control
`
`[3
`
`Register must be reset before attempting to write to
`
`this register, else the write will be ignored.
`Bits O-4
`RAM X word address
`Bit
`5
`RAM X full
`Bits 6-7
`Not Used
`
`
`
`This register is cleared by
`Register Address 5.
`the reset signal or by writing to the reset bit.
`The
`Enable Data Transfer bits in the Data Transfer Control
`
`Register must_be reset before attempting to write to
`
`this register, else the write will be ignored.
`Bits 0-4
`RAM Y word address
`Bit
`5
`RAM Y full
`
`Bits 6-7
`
`Not Used
`
`&mJfia_
`
`Register Address 6.
`
`The Enable Data Transfer bits
`
`in the Data Transfer Control Register must be reset
`
`before attempting to write to this register, else the
`write will be ignored.
`The port A to Port B bit in
`
`SUBSTITUTE SHEET
`
`Oracle Ex. 1002, pg. 1215
`
`
`
`wo 9_1 l03788
`
`PCTIUS90l04711
`
`-95-
`
`the Data Transfer Control register must also be set
`If it is not,
`the RAM
`will be
`
`before writing this register.
`controls will be incremented but no data
`written to the RAM.
`
`For consistency,
`
`the Port A to
`
`PortE should be reset prior to reading this register.
`Bits 0-7 are Fifo Data.
`The microprocessor may
`
`-access the FIFO by reading or writing this register.
`The RAM control registers are updated as if the access
`
`was using Port A.
`bit CPU Interface the most significant byte will use
`the Port A 0-7 data lines, and each Port A access will
`
`If the chip is configured with a 16
`
`increment the Port A byte address by 2.
`
` mnm.
`
`Register Address 7.
`
`This register is cleared by
`
`the reset signal or by writing to the reset bit.
`Bits
`The
`0-7 are Checksum Data.
`chip will
`accumulate a 16 hit checksum for all Port A accesses.
`
`If the chip is configured with a 16 bit CPU interface,
`
`the most significant byte is read on the Port A 0-7
`If data is written directly
`to this
`
`data lines.
`
`register it is added to the current contents rather
`than overwriting them.
`It is important to note that
`the Checksum Enable bit in the Data.Transfer Control
`
`Register must be set to write this register and reset
`to read it.
`
`EEQQRAQMING [[‘_l-IE FIEQ QHIZ
`
`In general the fifo chip is programmed by writing
`to the data
`transfer
`configuration and
`control
`
`registers to enable a data transfer, and by reading
`the data transfer status register at the end of the
`
`transfer to check the completion status. Usually the
`
`take place with both the
`data transfer itself will
`Port A and the Port B handshakes enabled, and in this
`
`case the data transfer itself should be done without
`
`SUBSTITLITESHEET
`
`Oracle Ex. 1002, pg. 1216
`
`
`
`wo 9‘!/03788
`
`PCT/US90/0471 1. _
`
`-96-
`
`In
`interaction.
`any other microprocessor.
`applications, however,
`the Port A handshake may not be
`it will
`be
`the
`
`enabled ,
`
`and
`
`BONE
`
`necessary
`
`for
`
`microprocessor to fill or empty the fifo by repeatedly
`
`writing or reading the Fifo Data Register.
`
`Since the fifo chip has no knowledgeof any byte
`
`counts,
`
`there is no way of
`
`telling when any data
`
`transfer is complete by reading any register within
`this chip itself.
`Determination of whether the data
`
`transfer has been completed must therefore be done by
`some other circuitry outside this chip.
`
`The following C language routines illustrate how
`
`the parity FIFO chip may be programmed. The routines
`
`assume that both Port A and the microprocessor port
`
`are connected to the system microprocessor, and return
`
`a
`
`size code of
`
`16 bits, but
`
`that
`
`the hardware
`
`addresses the Fifo chip as long 32 bit registers.
`
`struct FlFO__regs {
`unsigned char config,a1,a2,a3 ;
`unsigned char controI,b1,b2,b3;
`unsigned char status,c1,c2,c3;
`unsigned char ram access_corrtrol,d1,d2,d3;
`unsigned char ram:X addr,e1.e2.e3;
`unsigned char ram_Y:addr,f1,f2,f3;
`unsigned long data;
`L}1nsigned Int checksum.h1;
`
`#define FIFO1 ((struct FIFO__regs*) F|F0_BASE;_ADDRESS)
`
`#deflne FlF0__RESET 0x80
`#define FIFO 16 srrs 0x08
`#define Flsojczmnv WRAP 0x40
`#deflne FlF0_PORT K_ENABLE 0x01
`#define FlFO_PORT:B_ENABLE 0x02
`#deflne FlFO_PORT_ENABLES oxoa
`#define FlF0_PORT A TO B 0x04 .
`#define FIFo_cHEcT<s‘uM"ENAsLE 0x40
`#define FlFO_DATA_lN_R/KM 0x01
`#dei_ine FlFO_FORCE_FIAM_FULL 0x20
`
`#define PORT A_TO PORT B(fifo) ((fifo-> control) & 0x04)
`#define POR‘l’:A_BYTE_ADfiRESS(fifo)' ((fifo—>ram_access_contro|) &
`0x03)
`'
`«
`#dsfine PORT A_TO__RAM Y(fifo)
`#define PORT:B_T0_RAM_'_Y(fifo)
`
`0x04)
`((fifo->ram aocess_contra|) &
`((fifo-> rarr'f_access__oontrol) & 0x08)
`
`suasinura sum
`
`Oracle Ex. 1002, pg. 1217
`
`
`
`W0 91/03788
`
`PCTIUS90/0471 I
`
`-97-
`
`l***t*1*****tttttt**i*****fl'ktt*tttitt*ttt*iit*tt***fl*i'*******
`The following routine Initiates a File data transfer using two
`values passed to it.
`
`config__data
`
`This is the data to be written to the configuration register.
`
`controI_data This is the data to be written to the Data Transfer Control
`Register.
`If the data transfer is to take place
`automatically using both the Port Aand Port 3
`handshakes. both data transfer enables bits should be
`set in this parameter.
`I'f*i'fi**iIt&'kfi*‘k*tt*'IR*‘I*f'kCI‘I*2tflQ*fl*tltfifiittttfiifititttiifif
`
`FIFO initiate data transfer(config data, control_data)
`unsigTied char oonTig_data. control_data;
`{
`
`.
`FIFO1->oonfig = oontig data | FlFO_FlESEl';
`Configuration value & Reset 7/
`FIFO1->control = control data 8. (~FlFO_PORT_ENABLES):
`everything but enaBles */
`FlFO1->control = control_data;
`enables */
`
`/* Set
`
`/* Set
`
`-
`
`/* Set data transfer
`
`} l
`
`tt**i~l*i't‘fit*t***Ifl*ti'*t*i*tI‘t'ktfl'*if*ifi1*l'tkttiitiiflflifititfl
`The following routine forces the transfer of any odd bytes that
`have been left in the Frfo at the end of a data transfer.
`It first disables both ports, then forces the Ram Full bits, and then
`re-enables the appropriate Port.
`‘
`'ki*i'I'k**i§*#fi'IfQflf*f**Ii
`K*t*t* /
`
`FlFO_fcrce_cdd__length__transfer0
`{
`*
`
`.
`A
`FlFO1->control &= --FlF0_PORT_ENABLES; /* Disable Parts A & B
`
`if (PORT A TO POBT_B(F|FO1)) {
`i1'(POn'r" A TO_FlAM_Y(FIF01)) {
`FTF51->rarn_Y_addr = FlFO_FORCE_FlAM_FULL: /*
`
`Set RAM Y full -/
`
`} e
`
`lse FIFO1->ram_X_addr = FlFO_FORCE_RAM_FULL:
`RAM X full */
`FlFO1->control l= FIFO_POFlT_B_ENABLE;
`Re-Enable Port B */
`
`/* _Set
`
`/*
`
`} e
`
`lse {
`
`{
`if (POFlT_B T0_FtAM Y(Fll-'01))
`FIFGI->ram_7_addr = F|FO_FORCE_RAM__FULL;
`
`Set RAM Y full */
`
`/*
`
`} e
`
`lse FlFO1->ram_X_addr = FlFO_FOFlCE_RAM_FULL: /* Set
`RAM X full */
`
`EZSBSTITHTE SHEET
`
`Oracle Ex. 1002, pg. 1218
`
`
`
`W0 91/03788
`
`PCT/U590/04711
`
`-98-
`
`' FlFO1->control |= FlFO__PORT_A'__ENABLE;
`Re-Enable Port A */
`}
`
`/*
`
`} I
`
`ititttiiiiititiiiiiiiiiftiiiiittfiiiifl*Ifi**ii*iti**tii*iiii*
`The following routine returns how many odd bytes have been
`left in the Fifo at the end of a data transfer.
`iittikiiit**itiiiifittitti*t**t**!I**It*i*t*it**tfi*flIt**fli**/
`
`iitt FlF0_count_odd_bytes0
`int number odd_bytes;
`number_o<Td_bytes=O;
`if (FIFO1->status & FIFO DATA IN RAM)
`if (PoRT_A_To_PZ'JRT_B'(FIFo1)) {
`number odd bytes =
`(PORT_A_BYTE_ADDRES§(FlF61» ;
`if (POFlT_A_T0_FiAM Y(FlFO1))
`number__odd__Bytes + = (FlF01—>ram_Y_addr) *
`
`4 ;
`
`else number_odd_bytes + = (FIFO1->ram_X_addr) * 4 ;
`
`else {
`
`}
`
`if (PORT_B TO_FiAM v(r=n=o1))
`num'ber odd_Bytes = (FIFO1->ram,_Y_addr) * 4 ;
`else number_o3d_bytes = (FIFO1->ram_X_addr) * 4;
`I
`
`return (number_odd_bytes);
`
`} !
`
`*fifi**it****t******ii*iittiiiitiiiiiiiiltiiiiittttfiittfliifitf
`The following routine tests the microprocessor interiace of the
`It first writes and reads the first 6 registers.
`It then writes 1s. Os, and
`chip.
`an address pattern to the RAM, reading the data back and checking it.
`
`The test returns a bit significant error code where each bit
`represents the address of the registers that failed.
`
`Bit 0 = oonfig register tailed
`Bili = control register tailed
`Bit 2 = status register failed
`Bit 3 = ram access control register failed
`Bit 4 = ram X address register failed
`Bit 5 = ran1 Y address register failed
`Bit 6 = data register failed
`Bit 7 = checksum register failed
`ItiiI*iii*t*tit*IIttiiIt**t*i*t*ti*Qflii**ti*itit**I***fi**fiil
`
`#deiine RAM_DEPTH s4
`
`/* number of long words in Fife Flam’ *1
`
`reg_expected_data[6] = {Ox7F. D_xFF. 0x00, OX1 F. 0x3F. 0x3F };
`
`8lJll_S_TlT|liE SHEET
`
`Oracle Ex. 1002, pg. 1219
`
`
`
`W0 91/03788
`
`'
`
`PC!‘IUS90/0471 1
`
`-99-
`
`:{:har FlFO_uprocessor_interface_testo
`unsigned long test_data;
`char *register_addr;
`int I;
`char j,error;
`FIFO1->config = FiFO_RESEi';
`error=O;
`register_addr = (char *) FIFO1;
`i=1:
`
`/* first test registers 0 thru 5 */
`
`tor G=0; i<6; i++) {
`/* write test data */
`*register_addr = OxFF;
`it (‘register addr i= reg_expected__data[I]) error. | = J;
`*register_aHdr = 0:
`/* write us to register */
`if (*register_addr) error [= j;
`’
`/* write test data again */
`*register_addr = 0xFF;
`i1‘(*register_addri= reg_expected_datafi]) error |= 1;
`FIFO1->oonfig = FIFO RESEF;
`/* reset the chip */
`if (*reglster_addr) error'| = J; /' register should be 0 */
`register_addr+ +;
`/* go to next register */
`j < < =1;
`
`/" new test Ram data & checksum registers
`test is throughout Ram & then test Os */
`
`tor (test_data = -1; test_data l= 1; test_data+ +)
`& Os */
`
`{
`
`/* test for is
`
`FIFO1->oontig = FiFO.RESET | FIFO 16_BlTS;
`FIF01->oontrol = FIFO‘ POFiT_A_TO_§;
`for (i=0;i<RAM_DEPTH?i+ +)
`
`/* write data to RAM
`
`*/
`
`FiFO1->data = test_data;
`FiF01->oomrol = 0;
`for G=0;i<FtAM_DEPTH;i+ +)
`It (FIFO1->data != test_data) error |= j;
`
`check data */
`if (FIFO1->checksum) error |= 0x80;
`should = O */
`.
`}
`
`‘
`/* read &
`
`/* checksum
`
`/* new test Ram data with address pattern
`uses a different pattern for eve
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