ORACLE EXHIBIT 1002
`
`ORACLE EXHIBIT 1002
`
`PART 2
`
`PART 2
`
`
`
`
`
`ORACLE EXHIBIT 1002
`
`PART 2
`
`PART 2
`
`
`
`
`
`uP Data 0-7, uP Data P, uPAdd 0-2,
`
`CS
`
`These
`
`signals are used by a microprocessor
`
`to
`
`address
`
`the programmable repisters within the 'chip.
`
`The odd parity signal uP Data P is only checked when
`data is written to the Fifo Data or Checksum Registers
`
`and microprocessor parity is enabled.
`
`élk
`
`The clock input
`
`is nsed to generate some of
`
`the
`
`chip timing. It
`
`is expected to be in the 10-20 Mmz
`
`range.
`
`Read En, Write En
`
`During microprocessor accesses, while cs is true,
`
`these
`
`signals
`
`determine
`
`the direction of
`
`the
`
`microprocessor accesses. During data transfiers in the
`WD made.
`these
`signals
`are data
`strohes
`used
`in
`conjunction with Port A Ack.
`
`Port 3 00-07, 10-17, 20-21, 30-37,
`
`0P—3P
`
`Port 8 is a 32 bit data port.
`
`There is one odd
`
`parity bit for each byte.
`
`Port B OP is the parity of
`
`bits 00-07, PortB 1P is the parity of bits 10-17, Port
`
`3 29 is the parity of bits 20-27, and Port 3 39 is the
`
`parity of bits 30-37.
`
`Attorney Docket No.:AUSP7209.‘
`WP1/WSW/AUSP/7209.001
`,
`
`8/24/89-7
`
`Oracle Ex. 1002, pg. 601
`
`
`
`-115-
`
`B select, B Reg, B Ack, Parity sync, B Output Enable
`
`These signals are used in the data transfer mode
`
`to control the handshake of data on Port B. Port B Reg
`
`and Port 3 Ack are both gated with Part B select.
`
`‘The Port 8 Ask signal is used to strobe the data on the
`
`Port B data lines.
`
`The parity sync signal is used to
`
`indicate to a chip configured as the parity chip to
`
`indicate that
`
`the last words of data involved in the
`
`parity accumulation are on Port B.
`
`The sort B data
`
`lines will only be driven by the Fife chip if all of
`
`the following conditions are met:
`
`"the data transfer is from Port A to Port B;
`
`the Port 8 select signal is true;
`
`the Port B output enable signal is true; and
`
`the chip is not configured as the parity chip
`or
`it
`is in parity correct mode
`and ‘the
`Parity Sync signal is true.
`
`Reset
`
`This signal resets all
`
`the registers within the
`
`chip‘and causes all bidirectional pins to be in a high
`
`impedance state.
`
`0
`
`fiQgmaL_Q2§ratigg.. Normally the chip acts as a
`
`simple FIFO chip.
`A FIFO is simulated by using two RAM
`buffers in a simple ping—pong mode.
`It is intended,
`
`but not mandatory.
`
`that data is burst
`
`into or out of
`
`Attorney Docket No.:AUSP7209
`WP1/WSW/AUSP/7209.001
`
`8/24/89-7
`
`Oracle Ex. 1002, pg. 602
`
`
`
`-116-
`
`the FIFO on Port 3. This is done by holding Port 8 sel
`
`signal
`
`low and pulsing the Port B Ack signal. When
`
`transferring data from Port 3 to Port A, data is first
`
`written into RAM X and when this is full,
`
`the data.
`
`paths will be
`
`switched such ‘that Port
`
`8 may start
`
`writing to RAM Y.
`
`_Meanwhi1e
`
`the chip willl begin
`
`emptying RAM X to Port A.
`
`When RAM Y is full and RAM
`
`h empty the data paths will be switched again such that
`
`Port 8 may reload RAM X and Port A may empty RAM Y.
`
`2g;;_A_§;ggg_flgdg.
`
`This is the default mode and
`
`the chip is reset to this condition.
`
`In this mode the
`
`chip waits for a master such as one of the SCSI adapter
`
`chips $42 to raise Port A Request for data transfer.
`
`If data is available the Fifo chip will respond with
`
`Port A Ack/Rdy.
`
`gar; A WD Mode.
`
`The chip may be configured to
`
`run in the WD or Western Digital mode.
`
`In this mode
`
`the chip must be configured as a slave on Port A.
`
`It
`
`differs from the default slave mode in that
`
`the chip
`
`responds with Read Enable or Write Enable’ as
`
`appropriate together with Port A Ack/Rdy. This mode is
`
`intended to allow the chip to be interfaced to the
`
`Western Digital 33C93A SCSI chip or the NCR 53C90 SCSI
`
`chip.
`
`gag; A Master uggg.
`
`when the chip is configured
`
`as a master, it will-raise Port A Ack/Rdy when it is
`
`Attorney Docket No.:AUSP7209
`WP1/WSW/AUSP/7209.001
`:
`
`'
`
`8/24/89-7
`
`Oracle Ex. 1002, pg. 603
`
`
`
`-117-
`
`ready for data transfer. This signal is expected to be
`
`tied to the Request
`
`input of
`
`a DMA controller which
`
`will
`
`respond with Port A Req when data is available.
`
`In order to allow the DMA controller to burst,
`
`the Port
`
`A Ack/Rdy signal will only be negated after every 8 or
`
`16 bytes transferred.
`
`2ggt_j_g§;g;;g;_jgi;g_flggg.
`
`In parallel write
`
`node,
`
`the chip is configured to be the parity chip for
`
`a parallel
`
`transfer from Port 8 to Port A.
`
`In this
`
`mode, when Port
`
`B Select
`
`and Port
`
`8 Request are
`
`asserted, data is written into RAM X or RAM"! each
`
`time the Port 3 Ack signal is received.
`
`For the first
`
`block. of
`
`128 bytes data is
`
`simply copied into the
`
`selected RAM. The next 128 bytes driven on Port 8 will
`
`be exclusive-ORed with the first
`
`128 bytes.
`
`This
`
`procedure will be repeated for all drives such that the
`parity is accumulated in this chip.
`The Parity sync
`signal should be asserted to the parallel chip together
`
`with'the last block of 128 bytes.
`
`This enables the
`
`chip to switch‘ access
`
`to the other
`
`RAM and start
`
`accumulating a new 128 bytes of parity.
`
`rt B P
`
`a
`
`e
`
`o
`
`- C
`
`ck Da
`
`.
`
`This
`
`mode is set if all drives are being read and parity is
`
`to be cheched.
`
`In this case the Parity Correct bit in
`
`the Data Transfer Configuration Register
`
`is not set.
`
`The parity chip will first read 128 bytes on Port A as
`
`Attorney Docket No.:AUSP7209
`HP1/WSW/AUSP/7209.001
`
`8/24/89-7
`
`Oracle Ex. 1002, pg. 604
`
`
`
`C
`
`-118-
`
`in a-normal read mode and then raise Port B Request.
`
`While it has this signal asserted the chip will monitor
`
`the Port 8 Ack signals and exclusive-or the data on
`
`Port 8 with the data in its selected RAM.
`
`The Parity
`
`sync should again be asserted with the last block of
`
`128 bytes.
`
`In this mode the chip will not drive the
`
`Port 8 data lines but will check the output of
`
`its
`
`exclusive-or logic for zero.
`
`If any bits are set at
`
`this time a parallel parity error will be flagged.
`
`29;: g gaggllgl Egg; mode - ggrregt Qata.
`This”
`mode is set by setting the farity Correct bit in the
`
`Data Transfer Configuration Register.
`
`In this case the
`
`chip will work exactly as in the check mode except that
`
`when Port
`
`13 Output Enable, Port 8 Select and Parity
`
`Sync are true the data is driven onto the Part 3 data
`
`lines and a parallel parity check for zero is not
`
`‘performed.‘
`
`In the normal. mode it is expected
`§x§g__§xan.
`that‘Port B bits 00-07 are the first byte; bits 10-17
`
`the second byte, bits 20-27 the third byte, and bits
`
`30-37 the last byte of each word.
`
`The order of these
`
`bytes may be changed by writing to the byte swap bits
`
`in the
`
`configuration register
`
`such
`
`that
`
`the byte
`
`address bits are inverted.
`
`The _way
`
`the bytes are
`
`written and
`
`read also depend on whether
`
`the
`
`CPU
`
`interface is configured as 16 or 8 bits.
`
`The following
`
`Attorney Docket No.:AUSP7209
`WP1/WSW/AUSP/7209.001
`
`8/24/89-7
`
`Oracle Ex. 1002, pg. 605
`
`
`
`-119-
`
`table shows _the byte alignments
`
`for
`
`the different
`
`possibilities
`
`for data
`
`transfer using the Port
`
`A
`
`Request / Acknowledge handshake:
`
`CPU
`
`Invert
`
`Invert
`
`Port B '
`
`Port 3
`
`byte 1
`
`byte 1
`
`byte 0
`
`byte 0
`
`’ uProc
`byte 1
`
`Port A
`byte 1
`
`uProc
`byte 0
`
`Port A
`byte 0
`
`when the Fifo is accessed by reading or writing
`
`the Fifo Data Register through the microprocessor port
`
`in 8 bit mode,
`
`the bytes are in the same order as the
`
`‘table above but the uProc data port is used instead of
`
`Port A.
`
`In 16 bit mode the table above applies.
`
`d
`
`h Tran er .
`
`If the data transfer
`
`is
`
`not
`
`a multiple
`
`of
`
`32 uords, or
`
`128 bytes.
`
`the
`
`microprocessor bust manipulate the internal registers
`
`of the chip to ensure all data is transferred. Port A
`
`Ack and Port 8 Reg are normally not asserted until all
`
`Attorney Docket No.:AUSP7209
`«W21/WSW/AUSP/7209.001
`
`8/24/89-7
`
`Oracle Ex. 1002, pg. 606
`
`
`
`-120-
`
`32 words of
`
`the selected RAM are available.
`
`These
`
`signals may be forced by writing to the appropriate RAM
`
`status bits of the Data Transfer Status Register.
`
`when an odd length transfer has taken place the
`
`microprocessor must wait until both ports are quiescent
`
`before manipulating any registers.
`
`It
`
`should then
`
`reset both of the Enable Data Transfer bits for Port A
`
`and Port B.in the Data Transfer Control Register.
`
`It
`
`must then determine by reading their Address Registers
`
`and the RAM Access Control Register whether RAM X or
`
`RAM Y holds the odd length data.
`
`It should then set
`
`the corresponding Address Register
`
`to a value of
`
`20
`
`hexadecimal,
`
`forcing the RAM full hit and setting the
`
`address to the first word. Finally the microprocessor
`
`should set the Enable Data Transfer bits to allow the
`
`chip to complete the transfer.
`
`-
`
`At this point the Fifo chip will think that there
`
`are now a full 128 bytes of data in the ham and will
`
`transfer 128 bytes if allowed to do so.
`
`The fact that
`
`some of
`
`these
`
`128 bytes
`
`are not valid must
`
`be
`
`recognized externally to the FIFO chip.
`
`Attorney Docket No.:AUSP7209
`WP1/WSW/AUSP/7209.001
`
`8/24/89-7
`
`Oracle Ex. 1002, pg. 607
`
`
`
`E
`
`E
`
`R R
`
`egister Address 0.
`
`This register is cleared by
`
`the reset signal.
`
`Bit
`
`0
`
`Set if data transfers are to
`flQ_MQQg.
`use
`the Western Digital WD33C93A
`protocol, otherwise
`the Adaptec
`6250
`protocol will be used.
`
`if this chip is to
`Set
`ggrity ghip.
`accumulate Port B parities.
`
`C ‘rec
`Parit
`parity chip is
`parity on Port B.
`
`the
`if
`Set
`.
`to correct ' parallel
`
`If" set,
`.
`i
`i
`16
`ace
`the microprocessor data bits
`are
`combined with the Port A data bits to
`effectively produce a 16 bit Port. All
`accesses by the microprocessor as well
`as all data transferred using the Port A
`Request and Acknowledge handshake will
`transfer 16 bits.
`
`A b
`r
`v
`least
`the
`invert
`Port A byte address.
`
`to
`Set
`.
`e addres
`significant bit of
`
`to
`Set
`.
`Invert Port A byte address
`invert the most significant bit of Port
`A byte address.
`
`' - Set to enable the
`carry out of
`the 16 bit checksum adder
`to carry back into the least significant
`bit of the adder.
`
`to this bit will
`geset. Writing a 1
`reset
`the other
`registers. This bit
`resets
`itself after
`a maximum of
`2
`clock cycles and will therefore normally
`be
`read as
`a 0.
`No other
`register
`should be written for
`a minimum of
`4
`clock cycles after writing to this bit.
`
`Attorney Docket No.:AUSP7209
`WP1/WSW/AUSP/7209.001
`'
`
`.
`
`8/24/89—7
`
`Oracle Ex. 1002, pg. 608
`
`
`
` fl
`
`Register Address 1.
`
`This register is cleared by
`
`the reset signal or by writing to the reset bit.
`
`Bit
`
`Bit
`
`Bit
`
`'
`
`0 . Set to
`enable the Port A Req/Ack handshake.
`
`1
`
`2
`
`Set to
`B.
`n
`r n
`Da
`b
`enable the Port 8 Reg/Ack handshake.
`
`data
`set,
`If
`g.
`to gort
`g
`gort
`If
`transfer is from Port A to Port B.
`reset, data transfer is from Port B to
`Port A.
`In order to avoid any glitches
`on the request lines,
`the state of this
`bit should not be altered at-the same
`
`time as the enable data transfer bits 0
`or 1 above.
`
`Bit
`
`3
`
`uPrQgg§§gr Parity Enable. Set if parity
`is to be checked on the microprocessor
`interface.
`It will only be checked when
`writing to the Fifo Data Register or
`reading from the Fifo Data or Cbecksum
`Registers,
`or during a Port
`A
`Request/Acknowledge,
`transfer in 16 bit
`mode.
`The chip will, however, always
`re-generate parity ensuring that
`correct parity is written to the RAM or
`read on the microprocessor interface.
`
`Set if parity is
`.
`En
`A Pa
`to be checked on Port A.
`It is checked
`when accessing the Fifo Data Register in
`16 bit, node,
`or during
`a Port
`.A-
`Request/Acknowledge transfer.
`The chip
`will, however, always re—generate parity
`ensuring that correct parity is written
`to the
`RAM or‘ read on
`the Port A
`interface.
`
`Port B
`Set if
`29;; B Earity Enable.
`If it is
`data has valid byte parities.
`generated
`not
`set,
`byte parity is
`internally to the chip when writing to
`the RAMs.
`Byte parity is not checked
`when writing from Port 3, but always
`checked when reading to Port B.
`
`Attorney Docket No.:AUsP7209
`WP1/WSW/AUSP/7209.001
`
`B/24/89-7
`
`Oracle Ex. 1002, pg. 609
`
`
`
`-123-
`
`to enable writing
`Set
`gnggK5um_§nahLe.
`to the 16 bit checkaum register.
`This
`register accumulates a 16 bit checksum
`for all
`RAM accesses,
`including
`accesses to the Fifo Data Register, as
`well
`as all writes
`to the
`checksum
`register. This bit must be reset before
`reading from the Checksum Register.
`
`if Port A is to
`Set
`r.
`M
`r
`operate in the master mode on Port A
`during the data transfer.
`-
`
`Data
`
`r n fer
`
`a us Re '
`
`r Re
`
`Onl
`
`Register Address 2.
`
`This register is cleared by
`
`the reset signal or by writing to the reset bit.
`Bit
`O
`
`set if any bits
`' Data in RAM 3 or RAM Y.
`are true in the RAM X, RAM_Y, or Port A
`byte address registers.
`
`if the
`Set
`E or.
`P
`P rt
`Pr
`is set and a
`uProc Parity Enable bit
`parity error.
`is detected on
`the
`microprocessor interface during any RAM
`access or write to the Checksum Register
`in 16 bit mode.
`V
`
`Set if the Port A
`ggrt g garitg Errgg.
`Parity Enable bit
`is set and a parity
`error
`is detected on
`the Port
`A
`interface during any RAM access or write
`to the Checksum Register.
`
`set if
`.
`'
`ri
`1
`P
`the parity
`the chip is configured as
`chip,
`is not in parity correct mode, and
`a non zero result is detected when the
`Parity Sync signal is true.
`It is also
`set whenever data is read out onto Port
`B and the data being read back through
`the bidirectional buffer
`does
`not
`compare.
`'
`
`Set
`0—§ garity Egggg.
`B Bytes
`20;;
`whenever the data being read out of the
`RAMs on the Port 3 side has had parity.
`
`Attorney Docket No.:AUSP7209
`WP1/WSW/AUSP/7209.001
`
`8/24/89-7
`
`Oracle Ex. 1002, pg. 610
`
`
`
` mm
`
`Register Address 3.
`
`This register is cleared by
`
`the reset signal or by writing to the reset bit.
`
`The
`
`Enable Data Transfer bits in the Data Transfer Control
`
`Register must be reset before attempting to write to
`
`this register, else the write will be ignored.
`
`Bit
`
`0 - This bit is the
`least significant byte address bit.
`It
`is read directly bypassing any inversion
`done by the 'invert bit
`in the Data
`Transfer Configuration Register.
`
` - This bit is the
`most significant byte address bit.
`It
`is read directly bypassing any inversion
`done
`by the invert bit
`in the Data
`Transfer Configuration-Register.
`
`Port A to RAM Y.
`accessing RAM Y,
`accessing RAM X .
`
`to RAM Y.
`Pggg B
`accessing RAM Y,
`accessing RAM X .
`
`if Port A is
`Set
`and reset
`if it
`is
`
`if Port B
`Set
`and reset
`if it
`
`is
`is
`
`If the chip is-configured
`Long Burst.
`to transfer data on Port A as a master,
`amd this bit
`is reset,
`the chip will
`only negate Port A Ack/Edy after every 8_
`bytes, or 4 words in 16 bit mode, have-
`been transferred.
`If this bit is set,
`Port A Ack/Rdy will be negated every 16
`bytes, or 8 words in 16 bit mode.
`
`HQ; Used.
`
`MM
`
`Register Address 4.
`
`This register is cleared by
`
`the reset signal or by writing to the reset bit.
`
`The
`
`Enable Data Transfer bits in the Data Transfer Control
`
`Attorney Docket No. :AUSP7209‘
`WP!/WSW/AUSP/7209.001
`
`'
`
`8/24/89-‘I
`
`Oracle Ex. 1002, pg. 611
`
`
`
`-125-
`
`Register must be reset before attempting to write to
`
`this register, else the write will be ignored.
`
`Bits 0-4
`
`RAM X word address
`
`Bit
`
`5
`
`,
`
`RAM X full
`
`Bits 6-7
`
`Not Used
`
`r
`
`R
`
`'
`
`' e
`
`Register Address 5.
`
`This register is cleared by
`
`The
`the reset signal or by writing to the reset bit.
`Enable Data Transfer bits in the Data Transfer Control
`
`Register must be reset before attempting to write to
`
`this register, else the write will be ignored.‘
`
`Bits 0-4
`
`RAM Y word address
`
`Bit
`
`5
`
`Bits 6-7
`
`RAM i full
`
`Not Used
`
`ata
`
`e iste '
`
`e d W ite
`
`Register Address 6.
`
`The Enable Data Transfer bits
`
`in tfie Data Transfer Control Register must be reset
`
`before attempting to write to this register, else the
`
`write will be ignored.
`
`The Port A to Port 8 bit in the
`
`Data Transfer Control register must also be set before
`
`writing this register.
`
`If it is not,
`
`the RAM controls
`
`will be incremented but no data will be written to the
`
`RAM.
`
`For consistency,
`
`the Port A to PortB should be
`
`reset prior to reading this register.
`
`Attorney Docket No.:AUSP7209
`WP1/WSW/AUSP/7209.001
`
`8/24/89-7
`
`Oracle Ex. 1002, pg. 612
`
`
`
`-126-
`
`Bits 0-7 are Fifo Data.
`
`The microprocessor may
`
`access the FIFO by reading or writing this register.
`
`The RAM control registers are updated as if the access
`
`was using Port A.
`
`If the chip is configured with a 16
`
`bit CPU Interface the most significant byte will use
`
`the. Port A 0-7 data lines, and each Port A access will
`
`increment the Port A byte address by 2.
`
`ggrt A Chgckgurn Register (R§;';§1(flz;i§§1
`
`Register Address 7.
`
`This register is cleared by
`
`the reset signal or by writing to the reset bit.
`
`Bits
`
`0-7
`
`are Checksum Data.
`
`The
`
`chip will
`
`accumulate a 16 bit checksum for all Port A accesses.
`
`If the chip is configured with a 16 bit CPU interface,
`
`the most significant byte is read on the Port A 0-7
`
`data lines.
`
`If data is written directly
`
`to this
`
`register it is added to the current contents rather
`than overwriting them. ‘It is important
`to _note that
`the Checksum Enable hit
`in the Data Transfer Control
`
`Register must be set to write this register and reset
`to read it.
`
`M
`
`O HIP
`
`In general
`
`the fifo chip is programmed by writing I
`
`to the data
`
`transfer
`
`configuration and
`
`control
`
`registers to enable a data transfer,
`
`and by reading
`
`Attorney Docket No. :AUSP7209
`WP1/WSW/AUSP/1209.001
`
`8/24/89-7
`
`Oracle Ex. 1002, pg. 613
`
`
`
`-127-
`
`the data transfer status register at the end of
`
`the
`
`transfer to check the completion status. Usually the
`
`data transfer itself will take place with both the Port
`
`A and the Port B handshakes enabled, and in this case
`
`the data transfer itself should be done without any
`
`other microprocessor
`
`interaction.
`
`In
`
`some
`
`applications, however,
`
`the Port A handshake may not be
`
`enabled,
`
`and
`
`it will
`
`be necessary
`
`for
`
`the
`
`microprocessor to fill or empty the fifo by repeatedly
`
`writing or reading the Fifo Data Register.
`-
`Since the fifo chip has no hnowledge of any byte
`
`counts,
`
`there is no way
`
`of’
`
`telling when any data
`
`transfer is complete by reading any register within
`
`this chip itself.
`
`Determination of whether the data
`
`transfer has been completed must therefore be done by
`
`some other circuitry outside this chip.
`
`The following C language routines illustrate how
`
`the parity FIFO chip may be programmed.
`
`The routines
`
`assume that both Port A and the microprocessor port are
`
`connected to the system microprocessor, and return a
`
`size code of 16 bits,’but that the hardware addresses
`
`the Fifo chip as long 32 bit registers.
`
`Attorney Docket No. :AUSP7209
`WPI/WSW/AUSP/7209.001
`
`'
`
`3/24/89-7
`
`Oracle Ex. 1002, pg. 614
`
`
`
`-128-
`
`struct FIFO_regs {
`char
`unsigned
`config,al,a2,a3 ;
`char
`unsigned
`control,b1,b2.b3;
`char
`sra:us,cl,c2,c3;
`unsigned
`char
`unsigned
`tam_access_pontro1,dl_d2,d3;
`char
`unsigned
`ram_X_addr,el;e2,e3;
`char
`unsigned
`ram_Y_addr,f1,t2,f3;
`data;
`long
`unsigned
`unsigned
`int checksun,h1;
`I;
`
`#define
`
`FIE01-((struct
`
`FIFO_regs*) FIFO_BASE_ADDRESS)
`
`fidefine
`adefine
`fidefine
`fidetine
`fidefine
`fldefine
`fidefine
`gdefine
`fidefine
`#define
`
`1-'1so_nzss-r 0x80
`FIFO_l6_BI‘1‘S 0x08
`FIFO_CA.RRY_WRAP oxao
`FIFO_POB‘l'__A__ENABLE 0x01
`FIFO_POR'l‘_B_ENABLE 0x02
`I-‘IFO_POR'l'_ENABLES 0x03
`FIFO_POR'l‘_A_'l'O_B 0x04
`FIFO_pHECKSUM_ENABLE Oxbo
`FIFO__DA'1'A_IN_RAH 0x01
`sn=o_roncE_pZm4_1=u1.L 0x20
`
`) a oxoa)
`((fifo-—) control
`poa'r_A_-ro_pon-r_3('t1:o)
`PORT_A_BYTE_ADDRESS(fife) ([tifo->ram_access_contro1) &
`
`adefine
`gdefine
`0x03)
`fldefine
`-0x06)
`#define PORT_B_TO_BAH_Y(fiEo)
`0x08)
`
`pon'r__A__'ro'_nAM_Y ( t i to)
`
`((fito—>ramLpccess_contro1 ) &
`
`((fifo-> ramLpccess_pontrol
`
`) &
`
`/ttfiflfikkfltttfifitfifitfikfifittflkfififlfltfiflfiktflEt:fi:R*#*##§ktt2***t§**
`The following routine initiates a Fifo data transfer using
`two values passed to it.
`'
`
`config_data
`
`This is the data to be written to the
`configuration register.
`
`contro1_data
`
`This is the data to be written to the Data
`Transfer Control Register.
`If the data'transter
`is to take place automatically using both the
`Port Aand Port B handshakes, both data transfer
`enables bits should he set in this parameter.
`=:::est::::::testttes::2:::s:::::::::=::=:::=::::=:=::::=:=/
`
`FIFO_initiate_data_transfer(con!ig_data, contro1_data)
`unsigned char config_data, control_data;
`(
`
`FIF0l—>config = config_data 5 Fl!’-'O__RESE'l.‘;
`Configuration value-G Reset */
`
`/= Set
`
`Attorney Docket No.:AUSP7209
`WP!/WSW/AUSP/7209.001
`
`8/24/89-7
`
`Oracle Ex. 1002, pg. 615
`
`
`
`-129-
`
`FIFOI->controI - contro1_data G ('FIFO_POR1;fiNABLES);
`everything but enables */
`'
`FIFOI->control = contro1_fiata ;
`/* Set data transfer
`enables */
`
`/* Set
`
`I /
`
`titfikfitttfifiktkfltkfitflfikflflflttkfitkttkktttkkttttfifitfikkfihtttttfik
`The following routine forces the transfer of any odd bytes
`that have been left in the Fifo at the end of a data transfer.
`It first disables both ports,
`then forces the Ram Full bits, end'
`then re-enables the appropriate Port.
`eeaareeweacenaneeaaeteeazteeeeecagen:a¢eeee:::e*ee2**:«*a*:/
`
`EIFO_force_odd_1ength_transfer()
`[
`
`.
`FIFO!->contro1 &= 'FIFO_?ORT_ENABLES; /* Disable Parts A E B */
`if (PORT_A_IO_POET_8(FIF0l))
`(
`{
`i E
`(POR'1‘__A_'l‘O__RAM_Y (FIFO 1) )
`PIFO1—>ram_Y_addr = r1ro_Eonct_nAM_§6LL;‘/* Set nan Y
`
`full */
`
`)
`else z='I1=o1—>ram_x_addr = FIFO_FDRCE_R.A.M_FULL ;
`_
`X full */
`FIEOI->concro1 as FIFo_PoRT_p_ENABLE ;
`Port 8 */
`
`/* Set RAM
`
`/= Re~Enah1e
`
`/* Set
`
`/= Set RAM
`
`}e
`
`-
`lse (
`(
`if (POR'l'__B__'1‘O_RAM_Y(FIE'01))
`FIF01—>ram_Y_addr = FIFO_£ORCE_EAH_FULL
`RAH Y full *I
`
`} e
`
`lse FIF01—>ram_x__4ddr = FIE-‘O_FORCE_EAM_FULL
`X full */
`
`EIFO1-)contro1 }= FIFO_PORT_A_ENABLE ;
`Port A */
`}
`
`)
`
`..
`
`/* Re—Enab1e
`
`/flEl##tttfitktatttttttkfitfitttfikfikflfifitkttfittflfifififitttfitfifitittfit
`The following routine returns how many odd bytes have been
`left in the Fifo at the end of a data transfer.
`tttflkttttiattttktttttttktttttktttattkkttkttttkfittfitfigtttt#:/
`
`int FIEO_count_odd_bytes()
`{
`
`int number_odd_bytes;
`number_odd_bytes=0;
`it (FIFOl->status & nro DA‘l'A_1N mm)
`if (ponr_A_ro_poar_§(ErEoz)7
`(
`number_odd_bytes = (PORT_A_fiYTE_ADORESS(FIFO!))
`i t (PORT_A__'1‘O__RAH_Y ( F1 to 1 ) )
`number_oqd_bytes += (PIFOL-)ram_Y_addt) = 4 ;
`
`(
`
`;
`
`Attorney Docket No.:AUSP7209
`UPI/WSW/AUSPl7209.00l
`
`8/2h/89-7
`
`Oracle Ex. 1002, pg. 616
`
`
`
`-110-
`
`else number_odd_bytes +- (FIFOI->ran_X_addr) * 4 ;
`
`lse (
`it (PoRT_B_To_pAM_Y(FIFo1))
`number_odd_bytes - (FIFO!->ran;Y_eddr) * 4
`else number_odd_bytes = (FIFOI->ram_X_addr) * 4
`
`)e
`
`)
`
`eturn (number_odd_bytes);
`
`) r
`
`) /
`
`‘£‘.'9:.".".‘.'t:tktttttfififittfittafififitfififl=‘."£::‘.’:i‘*tt3‘.'%‘:‘:z"-‘:*tt‘:'£.".‘:'k$‘:'£':kt’£‘:**9:t3‘zt
`The following routine tests the microprocessor interface of
`the chip.
`It first writes and reads the first 6 registers.
`It
`then writes Is, Os, and an address pattern to the RAM, reading the
`data back and checking it.
`
`The test returns a bit significant error code vhere each
`bit represents the address of the registers that failed.
`
`= config register tailed
`air
`= control register failed
`Bit
`= status register failed
`Bit
`— ram access control register failed.
`Bit
`ram X address register failed
`Bit
`= ran Y address register failed
`Bit
`= data register failed
`air
`Bit 7 = checksum register failed
`at:itsttstttssittttttttttgtttkasttttttatttettsettttatséttts]
`
`adefine RAM_DEPTH 6h -
`
`l* number of long words in Fife Ram ‘I
`
`reg_expecred_nnra[6] = { 0x7F, OxFF, 0x00, 0x1F, 0x3F, OXJF ];
`
`char FIFO_nprocessor_interEace_test()
`I
`
`unsigned long test_data;
`char *register_addr;
`int i;
`-
`char j,error;
`FIFO1->con£ig = FIFO_RESET;
`error=D;
`register_addr =(char *) FIFOI;
`i=1;
`
`/* first test registers 0 thru 5 */
`
`/* reset the chip =/
`
`for
`
`[
`i++)
`i<6;
`(i-0;
`/* write test data */
`*register_addr = 0xFF;
`if (=register_addr != reg_expected_data[i]) error := j;
`*registcr_pddr - 0;-
`/= write Os to register */
`if (=register_addr) error £= j;
`
`Attorney Docket No.:AUSP7209
`HP!/WSW/AUSP/7209.001
`
`8/24/89-7
`
`Oracle Ex. 1002, pg. 617
`
`
`
`-131-
`
`/* write test data again */
`*register_addr - 0xFF;
`it (flregister_addr 1- reg_expecced_data[i]) error 1- j;
`FIFO!->config = FIFO_RESET;
`/* reset the chip */
`it (*regisrer;gddr) error := j; /* register should be 0 ‘I
`register_addr++;
`'/* go to next register */
`j <<-1;
`
`/* nou test Ram data & checksum registers
`test ls throughout Ram & then test Os */
`
`H
`
`'
`
`a
`
`test_data I= 1;
`
`test_data++)
`
`for (test_data = -1;
`for Is & Os */
`rm-‘o_1s_a1-rs ;
`FIFOI-)conf:'Lg — FII-‘O__RESET :
`FIFO!->contro).
`=- FIFO_PORT__A___'l'0__B;
`for (i=O;i<RAH_DEPTH;f++)
`FIFOI-)data = test_data;
`FIF01->contro1 - 0;
`for (i-=0;i<RAH_DEP'1‘H;i++)
`it (FIFO1->data l= tesr_data) error := j;
`_
`5 check data */
`'
`if (FIFO1~>checksum) error {= 0x80;
`should = 0 */
`)
`
`/* write data to RAH */
`
`/* read
`'
`
`* checksum
`
`/* new test Ram data with address pattern
`uses a different pattern for_every byte */
`
`/* address pattern start */
`test_data=0x00Ol0203;
`l-'IFO_16_BITS 1 FIFO_CARRY_W'R.AP;
`:
`FIFO!->canfig = FIFO_RESE'1‘
`FIFO!->contro1 = FIFO_P0RT_A_TQ_B } FIEO_CHECKSUM_ENABLE;
`for (i=O;i(RAM_DEPTH;i++)
`{
`FIFO1->data = test_data;
`test_data += 0x04640604;
`
`/* write address pattern */
`
`I t
`
`1* address pattern start */
`est_data=OxOOOl02D3;
`FIFO!->cnntro1 = FIEO_§HECKSUM_ENABLE;
`for (i=0;i<RAK_DEPTH;i++)
`[
`if (FIFO1->status != FIFO_DATA_IN_flAM)
`error £= 0x04;
`/* should be date in ten */
`if (FIFO!-)data != rest_dara) error := j;
`/* read &
`check address pattern */
`test_data +- 0x04040404;
`
`.
`
`.
`)
`if (FIFO1-)checksum != 0x0102) error {= 0x80;
`checksum of address pattern */
`-
`FIFO1—>conEig = FIFO_RESET I FIFO_l6_BITS ;
`wrap.*/
`FIF01->checksum = 0xFEFE;
`
`/* test
`
`/= inhibit carry
`
`/* writing adds to checksum */
`
`Attorney Docket No.:AusP7209
`W91/Usw/AUSP/7209.001
`
`8/2b/89-7
`
`Oracle Ex. 1002, pg. 618
`
`
`
`-132-
`
`if (FIFOI-)checksum) error :=0x80;
`if (FIFOI->scacus) error i- 03:01:;
`return (error);
`J
`
`/* checksum should be 0 */
`/“ Status Should be 0 */
`
`Attorney Docket No. :AUSP7209
`WP1/WSW/AUSP/7209.001
`
`-
`
`8/24/89.-7
`
`Oracle Ex. 1002, pg. 619
`
`
`
`CLAIMS
`
`095447/2
`
`_
`
`1.
`
`Network server apparatus for use with a data
`
`network and a mass storage dewice, comprising:
`
`an interface processor unit coupleable to said
`
`network and to said mass storage device;
`
`a host processor unit capable of running remote
`
`procedures defined by a client node on said network;
`
`means
`
`in said interface processor unit
`
`for
`
`satisfying requests from said network to store data
`
`from said network on said mass storage device;
`
`means-
`
`in said interface processor unit
`
`for
`
`satisfying requests from said network to retrieve data
`
`from said mass storage device to said network; and
`
`means
`
`in said interface processor unit
`
`for
`
`transmitting predefined categories of messages
`
`from
`
`said network to said host processor unit for processing
`
`in said host processor unit, said transmitted messages
`
`including all
`
`requests by a network client
`
`to run
`
`client-defined procedures
`
`on
`
`said network server
`
`apparatus.
`
`2.
`Apparatus according to claim 1, wherein said
`interface processor unit comprises:
`i
`a network control unit coupleable to said network;
`
`a data control unit
`storage device;.p
`«
`a buffer memory;
`
`coupleable to "said massj
`
`Attorney Docket llo.: I AUSP720fi|CFIGBR/HSU
`usu/ausp/T209.claims
`
`Oracle Ex. 1002, pg. 620
`
`
`
`095447/2
`
`means
`
`in
`
`said
`
`network
`
`control‘ unit
`
`for
`
`transmitting to said data control unit requests from
`
`said network to store specified storage data from said
`
`network on said mass storage device;
`
`means
`
`in‘
`
`said
`
`network
`
`control
`
`unit
`
`for
`
`transmitting said specified storage data from said
`
`network to said buffer memory and from said buffer
`
`memory to said data control unit;
`
`means
`
`in
`
`said
`
`network
`
`control
`
`unit
`
`for
`
`transmitting to said data control unit requests from
`
`said network to retrieve specified retrieval data from
`
`said mass storage device to said network;
`
`means
`
`in
`
`said
`
`network
`
`control
`
`unit
`
`for
`
`transmitting said specified retrieval data from said
`
`data control unit to said buffer memory and from said
`
`buffer memory to said network; and
`
`means
`
`in
`
`said
`
`network
`
`control
`
`unit
`
`for
`
`transmitting said. predefined categories of messages
`
`from said network to said host processing unit for
`
`processing by said host processing unit.
`
`3.
`
`Apparatus according to claim 2, wherein said
`
`data control unit comprises:
`
`a storage processor unit coupleable to said mass
`
`storage device;
`
`.a file processor unit;
`
`means on said file processor unit; for translating
`
`said file system level storage requests from said
`
`Attorney nocket No.: Au$P7209McF/GER/usu
`usu/ausp/T209.claims
`
`-134-
`
`Oracle Ex. 1002, pg. 621
`
`
`
`095447/3
`
`network into requests
`
`to store data at
`
`specified
`
`physical storage locations in said mass storage device;.
`
`means on said file processor unit for instructing
`
`said storage processor unit
`
`to write data from said
`
`buffer memory into said specified physical storage
`
`locations in said mass storage device;
`
`means on said file processor unit for translating
`
`file system level retrieval requests from said network
`
`into requests to retrieve data_from specified physical
`
`retrieval locations in said mass storage device;
`
`means on said file processor unit for instructing
`
`said storage processor unit to retrieve data from said
`specified physical
`retrieval
`locations in said mass
`
`storage device to said buffer memory if said data from
`
`said specified physical
`
`locations is not already in
`
`said buffer memory; and
`
`means
`
`in
`
`said .storage
`
`processor unit
`
`for
`
`transmitting data between said buffer memory and said
`
`mass storage device.
`
`4,
`
`-Network server apparatus for use with a data
`
`network and a mass storage device, comprising:
`
`a network control unit coupleable to said network;
`
`a data »control unit
`
`coupleable to said mass
`
`storage device;
`
`a buffer memory;
`
`means for transmitting from said network control
`
`unit
`
`to said data control unit
`
`requests from said
`
`Attomey (Jacket 010.: AUSPTZDVNCFI/USU
`Hsulausp/7209.claims
`
`-135-
`
`Oracle Ex. 1002, pg. 622
`
`
`
`095447/2
`
`network to. store specified storage data from said
`
`network on said mass storage device;
`
`means for transmitting said specified storage data
`
`by DMA from said network control unit
`
`to said buffer
`
`memory and by DMA from said buffer memory to said data
`
`control unit;
`
`means for transmitting from said network control
`
`unit
`
`to said data control unit
`
`requests fro said
`
`network to retrieve specified retrieval data from said
`
`mass storage device to said network; and
`
`means
`
`for transmitting said specified retrieval
`
`data by DMA from said data control unit to said buffer
`
`memory and by DMA from said buffer uemory to said
`
`network control unit.
`
`5.
`
`Apparatus according to claim 1,
`
`for use
`
`further with a buffer memory, and wherein said requests
`
`from said network to store and retrieve data include
`
`file system level
`
`storage
`
`and retrieval
`
`requests
`
`respectively, and wherein said interface processor unit
`
`comprises:
`
`a storage processor unit coupleable to said mass
`
`storage device;
`
`a file processor unit;
`
`means on said file processor unit for translating
`
`said file system level storage requests into requests
`
`to store data at specified physical storage locations
`
`in said mass storage device;
`
`-136-
`
`Auorney Docket llo.: AUSPTZOOHCF/GBR/USU
`USU/ausp/7Z09.claims
`
`Oracle Ex. 1002, pg. 623
`
`
`
`095447/4
`
`means on said file processor unit for instructing
`
`said storage processor unit
`
`to write data from said.
`
`buffer memory into said specified physical storage
`
`locations in said mass storage device;
`
`means on said file processor unit for translating
`
`said file system level retrievablerequests into requests
`
`to retrieve data from specified physical
`
`retrievable
`
`locations in said mass storage ‘device;
`
`means on said file processor unit for instructing
`
`said storage processor unit to retrieve data from said
`
`specified physical
`
`retrievabflelocations in said mass
`
`storage device to said buffer memory if said data from
`
`said specified physical
`
`locations is not already in
`
`said buffer memory; and
`
`means
`
`in
`
`said
`
`storage
`
`processor
`
`unit
`
`for
`
`transmitting data between said buffer memory and said
`
`mass storage device .
`
`Oracle Ex. 1002, pg. 624
`
`
`
`095447/.2> '
`Networksezver apparatus for use with a data
`
`I
`
`_6.
`
`network, comprising:
`
`a network controller coupleable to said network t0
`
`receive incoming information packets over said network,
`
`said incoming information packets \ including certain
`
`packets which contain part or all of a request to said
`server apparatus, said request being in either a first
`
`or a second class of requests to said server apparatus;
`
`a first additional processor;
`
`an interchange bus different from said network
`
`coupled between said network controller and said first
`
`additional processor;
`
`means in said network controller for detecting and
`
`satisfying requests in said first class of
`
`requests
`
`contained in said certain incoming information packets,
`
`said network controller lacking means in said network
`
`controller for satisfying requests in said second class
`of requests;
`.
`.
`‘
`
`means in said network controller for detecting and
`
`assembling. into assembled requests,
`
`requests in said
`
`second class of
`
`requests contained in said certain
`
`incoming inf
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