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`
` CROSSROADS EXHIBIT 2319
`Oracle Corp., et al v. Crossroads Systems, Inc.
` IPR2014-01207 and IPR2014-1209
`
`CROSSROADS EXHIBIT
`Oracle Corp. v. Crossroads Systems, Inc.
`IPR2015-0(cid:1005)(cid:1004)(cid:1010)(cid:1008)
`
`2319
`
`

`
` Updated:W
`Crossroads Confidential Material
`
`1.
`
`INTRODUCTION ............................................................................................................
`
`...........
`
`2. OVERVIEW .....
`
`
`
`.......................................4
`
`2.1 mnw.............................................................................................. ..4
`2.2
`PROTOTYPE DESCRIPTION ....................................................................................
`2.3
`DESIGN PHILOSOPHY...................................................................................................................... ..4
`
`
`3. CORE SOFTWARE MODULES....................................................................................................5
`
`BOOT CODE.................................................................................................................................... ..5
`3.1
`DIAGNOSTICS ................................................................................................................................. ..5
`3.2
`KERNEL.......................................................................................................................................... ..5
`3;
`FC DRIVER .......................................................................
`3.4
`SCSI DRIVER ................................................................................................................................. .. 6
`3.5
`BRIDGE CODE ................................................................................................................................ ..7
`3:6
`3.6.1 ArMMaud . ...................................................................... .. 7
`3. 6.2
`Buffer Management ........................................................................................................... .. 11
`3. 6. 3
`Protocol'TransIation........................................................................................................... .. 12
`3.6.4
`Address Translation............................................................................................................ .. 13
`3.6.5
`Program Structure............................................... ..
`3 .7
`ETHERNET DRIVER....................................................................................................................... .. 15
`3.8 C .......................................................................................................................... .. 15
`3.3.1 I ......................................................................................... .. [5
`3.8.2
`Serial Console .................................................................................................................. ..
`L6
`3. 83
`Telnet .................................................................................................................................. .. I6
`3.8.4
`FTP ..................................................................................................................................... .. M
`3.8.5
`SNMP................................................ .. _..........._..._...._.......__.....,“..m...........
`................... .. 16
`3. 8. 6
`HTTP .................................................................................................................................. .. 16
` Em‘ ............................................................................................................................. . . 16
`3 .9
`
`3.2.1
`SNMP
`............................................................................................... .. hi
`3.9.2
`HTTP ...................................................................................................... .. “
`
`4. DIAGNOSTIC TEST SOFTWARE ..................
`
`DIAGNOSTIC TI~;s1S.._..__._...__.._.._.............................................................................................. .. 17
`4.1
`Initial boot........................................................................................................................... .. I 7
`4.1.1
`[ED visual test.................................................................................................................... .. 1 7
`4.1.2
`Elas.h—Memor5v—.Read—test .................................................................................................. .. 17
`4.1.3
`Instruction Memory - Read/write test...................... .. M#_**_w*
`4.1.4
`Serial Controller - read/write test....................................................................................... .. I8
`4.1.5
`4.1.6 e test ................................................................................. ..18
`4.1.7 PCIMemm ...................................................................... .. 1-8
`4.1.8
`Tachyon .............................................................................................................................. ..18
`4.1.9
`Symliios 6'73 SCSI Controller............................................................................................. ..18
`
`Figure 3.1- Core processes and flow .............................. ............__.........._,,.....,............................................ .. 8
`Figure 3.2 - Management Commands Control Flow..................................................................................... .. 9
`Figure 3.3 - FC pre-fetch ........................................................................................................ .. 10
`
`r
`
`Table 3.1 - FCP_CNMD Infomiation Unit .................................................................
`TaEle 3.2 - SCSI Command Descriptor Block ............................................................................................ .. 12
`Table3. ..................................................................13
`Table 3.4 - Default Direct Address Map - SCSI->F_CP CNanrnm)...............
`............................................. ..1—3
`Table 3.5 - Ordered Address Map, FC->SCSI ............................................................................................ .. 14
`T2rbTe—6.1 960RP‘InterTupt’Map ................................................................... ..Error! Bookmark not defined.
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`Tafile 7.1 System Memory Map .....................................................................Error! Bookmark not defined.
`Table LLBCI Mammy Map ........................................................................ Bmmm
`
`C°“fid°“ti31 D°°“m°"t
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`3 Qm
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`
`
`
`
` - 7. . '. ’ =“i=_‘:‘i:~":‘G~“‘-'--S
`methods, processes, and requirements involved in the software development effort. It is meant to provide
`the basic guidelines for development, and as such is subject to change as the implementation evolves.
`
`2.0¥er\riew
`
`2.1 Product Hardware Description
`
`The target hardware is an embedded system centered around the Intel i960RP processor. Incorporated on
`the i960 bus are program memory, flash memory, and a serial UART. The secondary PCI bus from the
`i9‘60R? wilfhave an HP Tachyon , and
`,
`.
`us;
`In
`tau. u-:.-
`'
`.,
`' .-
`
`
`in house. The secondary PCI bus will also have the Symbios 53C875 PCI SCSI controller. The 960RP
`primary PCI bus will have an AMD l0BaseT Ethernet controller.
`
`Document, and in the Verrazano Strategic Specificatin.
`
`
`
`2.2 Prototype Description
`To accelerate software development and to allow for software development to be overlapped with
`
`
`the PCI bus and system memory. The host processor will not be used except for limited debugging
`purposes. The processor used will be the Intel Cyclone board with the i960JX processor module. This will
`l‘C‘I'o'oc~.' -’o"""
`‘ioi"no;‘uI‘ vo'vv.ovvo
`
`'
`.,_'
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`Ira‘:-.u‘u‘«,‘
`will be the Interphase Tachyon based PCI adapter. The SCSI interface will be the Symbios SYM53C875
`PCI adapter. Serial communication, flash memory, and other basic fimctionafity IS provfdecfhy the
`
`
`
`. T
`
`his provides an architecturally similar platform using essentially identical core components for
`development. Porting to the Verrazano hardware platform will require changes limited to the PCI bridge,
`memory and device mapping, and serial and other peripheral
`.1]
`.
`1
`I
`
`
`
`2.3 Design Philosophy
`‘C’ Code base
`
`Modular design
`
`Use Existing OS, Drivers, Protocol Stacks as possible
`Design for performance, future portability, maintainability
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`
`3. CoreS
`
`3. 1 Boot Code
`
`At system boot, code will be required to initialize the hardware,_perform basicsyste
`runtime code. The expectation is that this will consist in large part of modules available from Intel
` code will‘be modified and extended to support
`hardware specific characteristics which are TBD.
`
` s:
`1
`1
`. 1.
`.
`I
`Run Power On Self Test
`
`Set Processor, PCI address mapping
`Initialize and start VxWorks, core software
`
`3.2 Diagn_o_ati¢:s
`
`In addition to the power on self ‘
` ZIII
`hould inclue acibli
`scsi and Fibre Channel via FC-IP.
`
`0 Manufacturing Test
`0
`Field Test
`-
`I
`Return UnifTest
`Erocessor test
`
`0
`
`'
`
`0 Memory test
`0
`PCI test
`
`Buffer memory test
`0
`0 MTmw, external loop back
`0
`Symbios test - internal loop back, extemal_loop_back
`0
`Ethernet adapter test - internal loop back, external loop back
`
`3.3 Kernel
`
` d runtime OS. Future ports may be targeted for
`IxWorks.
`
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`3.4 FC Driver
`
`The Fibre Charmel driver will be based on the current ICS FC-2 SDK.Modifi
`initialization and FC-4 layers. The interfaces to this code will be defined in section Error! Reference
` .
`
`The FC driver provides the following functionality:
`0 Manage logms and logouts
`0
`.
`.
`
`.
`
`O
`
`0 Manage FCP command(exchange) through all phases for that command
`0
`Provide means for FC-4 to do process login for an FCP attached device
`0
`Receive all‘FC-4 data commands
` u
`0 Activation and Deactivation of exchanges
`0
`assignment of X_ID
`I Manage sequences
`I
`
`SEQ_1D assignment
`0
`0 Managing sequence initiative
`0 Manage EE credit
`
`Initial support will be arbitrated loops only. Later versions will support fabrics including_F andfilnpxmsj
`
`3.5 SCS1Dr1'VeT
`
`The SCSI driver will consist of two parts. The SCSI state machines will be implemented in the Symbios
`
`
`SCRIP
`I-
`-'
`---- --
`-"Z
`-‘--
`-- ‘
`- ""ii"' u" ’"I
`I‘
`'
`"
`interface runngon the i960 processor. The interfaces to this code and other architecturalch
`will’be defined in section Error! Reference source not found. of this document.
`
`The SCSI driver provides the
`0
`Provide SCSI initiator support with a single SCSI ID
`0 Manage Commands and Messages to targets
`0 r memory
`w
`Respond to multiple target IDs
`Process Commands and Messages
`Manage‘D‘M7\ to/‘from buffer memory
`
`.&
`
`.
`
`0
`
`Manage Synchronous, wide, and fast negotiation
`
`0 0
`
`fiT
`EXES QNLX
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`3.6 Bridge Code
`
`The Bridge code provides for the conversion andm and—SCSI
`devices. This code should be event driven, of a pass-through design and use a store and forward method of
` onal1w is defmed‘below. Additional operational characteristics are outlined in
`the .
`
`Requirements:
`
`0 layers
`
`Manage data buffers and internal command structures
`Manage FC4 interface
`
`
`
`3.6.1 Architectural Overview
`
`
`
` ..r;..--....:'
`I""
`‘2‘iii"
`
`are diagrammed, for FCP and SCSI processes. ese are:
`
`
`
`. Three areas offuncfionality
`
`0
`
`0
`
`Evenfhandling
`Bndgerpweesnng
`Request handling
`
`
`address translatin, and protocol tralation. The request handlers initiate tranfers on the FCP or_SCS]
`mterface as required by the other modules. Further description of these modules and their components is
`
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`SCSI In
`
`SCSI RECEIVE EVENT
`
`
`
` FCP RECEIVE EVENT
`
` FCP_RSP,
`
`SCSI smus.
`
`FEP_DATA In
`Date In
`SCSI Command,
`
`
`SCSI Command.
`Data Out
`
`
`
`
`FCP SEND REQUEST
`
`Figure 3.1- Core processes and flow
`
`(Describe FCP Command bridge, scsi command bridge as those processing for SCSI initiators and FC
`inieiaters.)
`I
`
`.
`
`(Add examples, with steps 1-N defined where each arrow in flow above is step described.)
`
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`Figure 3.1 illustrates control flow for management commands. Management commands are those
`
`commands that are processedhy the bridge directly, and not passed through to the altemate interface. This
`
`-;:.= ' i
`=
`:= =
`: :'= : -U“ I
`':i_ui
`'
`,
`I
`I ;II- ', -no
`- a_‘''‘‘
`I oughfhe
`FCP and SCSI interfaces in future releases. Similar interfaces to
`be provided for out of band management, via the Ethernet and serial interfaces.
`
`FCP RECEIVE EVENT
`
`SCSI RECEIVE EVENT
`
`
`
`Manauennnt
`Command
`Request
`
`Bridge
`
`FCP
`Command
`ET-fige
`
`Management Command
`Service
`
`SCSI
`Command
`
`I
`I
`Management
`Command
`Response
`
`lliaflll
`
`
`
`FCP SEND REQUEST
`
`Figure 3.2 - Management Commands Control Flow
`
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`
`where an
`Certain other cases exist to the nonnal flow
`FCP_CMND Write is received. In order to reduce inactive time on the SCSI bus, data is pre-fetched. This
`is exhibited in Figure 33. The bridge module snoops the command, and, if necessary,
`locates buffers and
`
`
`
`status pases fo thi ond proceed nrmally.
`
`Incoming
`FCP_CMD Writ:
`
`via IM
`SCSI
`
`(FCP_XF|R_RDY)
`Dltl h Bum:
`
` Pralatah om
`FCP_DATA FCF SEND REQUEST
`
`
`
`
`
`
`SCSI SEND REQUEST
`
`
`Figure 33 - FC’I"Write with pre-fetch
`
`(Optimize io vs throughput? Discuss - can sub_miI
`and like devices)
`
`for tapes
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`3.6.2 Buffer Management
`
`
`
`System memory is available both in the 960 local memory space or in PCI memory
`space. Hardware
`-..
`..
`-... .;
`u
`u
`r.
`.v.
`.o
`.u
`¢lI|I'
`
`' emory ‘reads from
`nearest RAM’. Accordingly, DMA read lists for the Tachyon
`'
` memory, and
`Tachyon write lists in program memory. Interrupt structures and Bridge command structures will reside in
`program memory. Although these lists w
`i1l'be read'by the Tachyon and Symbios part, it is likely that more
`—!
`.
`n_;,,
`._,; n:.....;
`-—-=..~
`'
`noon‘ .
`an
`.
`.5
`'.!e
`, -
`.
`
`buffer memory.
`
` flmwnm
`
`Data buffers
`
`0 Allocated sequentially
`0 2K eaeh
`
`- In 4MB PCI Buffenmemory
`0 Memory may be shared with Tachyon DMA lists, so less than 2048 buffers available
`0 Empirical testing to determine benefits of DMA lists in PCI vs. CPU memory
`
`Bridge command elements
`
`0 AIlocated“m program memory
`
`0 512 Allocated
`
`0 Max 480 targets (Wide SCSI targets times LUNS)
`0 Average queue depth per target greater than 1, TBD
`0 fi,U2 Bytes
`
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`3.6.3 Protocol Translation
`
`Protocol translation is performed by the core bridge code. This involves the translation of a CDB
`(CommandW converted‘between SCSI and'FCP. Generally, the structure of the
`
`
`CDBi_S -ll‘lIOI .-
`1.3!‘
`|
`-
`..-...- .
`.-
`|-
`addressing is required. The structure f th CP C ad
`s swn in Table 3.land Table 3.2.
`
`I
`
` —
`
`
`
`Lo ical Unit Number
`ontrol’FieId
`SCSLC --.--...e : B ‘ H ' i
`
`i
`
`
`
`
`
`
`
`
`
`CYRUS
`
`1‘E>-‘+37
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`
`3JL4 Addnsslfimshfien
`
`By default, the bridge will address in ‘Direct Addressing Mode’ with thema
`Table 3.4. Configuration will allow for FC AL_PA to be changed, however, the LUN value will map
`allow for specific SCSI target addresses to be disabled.
`SCSI bus.
`
`This reduces the range of available
`
`
`
`
`Talile 3.3- Default Direct Address Map, FCP->SCSI CVarrow)
`
`
`’ FC Address Verrazano AL PA
`SCSI Address
`I SCSI Tareto, LUNO
`I
`SCSI"l'aret 1, EUN'0
`%
` l
`| UN 8
`I
`
`
`
`
`
`
`
`n éésnarenunavanabxe Bnammatorm
`
`
`
`
`
`AL PALLUN6
`
`
`
`SCSITaret2,LUNO
`AL PA 2,L1m0
`‘
`
`
`
`S681‘-;-1,LUN1
`scsr 2,LUNl
`
`AL PA7,LUNO
`ALPA8,LUT+f)
`
`>
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`
` e can be enabled. This mode wfll perform discovery on the SCSI side
`
`
`ordered list of addresses with no pparen ps been devices. Although this provides automatic
`configuration, no allowance is given for hot plugging devices or any dynamic change of addressing.
`.
`not found..
`
`Table 1.5 - $$
`
`AL
`
`LU_'N 0
`LUN 1
`LUN 2
`
`SCSI Address
`1“
`2"‘ discovered SCSI BUS:TARGET:LUN
`3”‘ discovered SCSI BUS:TARGET:LUN
`
`
`
`
`An
`
`
`
`
`.
`'. ' ' n-
`numberof
`logical umts at cn adrssed. This is dete
`' ed by usingjhe $
`targets times the number of LUNS. Wide SCSI allows 16 SCSI IDs, one of which must be used as the
` can address 8 LUNS.
`
`Each FC->SCSI entry is 7 words. Each SCSI->FC element is 8 words. Thus, the total required memory
`for address tables IS 720?) bytes. These tables will reside in local 960 memory.
`
`3.6.5 Program Structure
`
`Three primary elements are defined for core bridge functionality. These are the SCSI driver, the FC driver,
` %®.
`
`BRIDGE
`
`SCSID1=i¥er
`
`FC2Bfl'ver
`
`(SCSILIB.O)
`
`(FC2LIB.O)
`
` $mMm
`TPI/Tachyon
`875 SCSI Controller
`
`Bridge intemals
`..............--
`
`—
`
`C
`
`S 1 6 Ll’
`
`In the future, FC2 may be bridged to other Arch. like ATM, ESCON, LAN, etc. In order to facilitate the
`
`-
`V
`v up:
`-
`Ikl II‘ mr
`
`- .
`o 2 components:
`
`0
`
`FC2 interface handler
`FC2 to SCSI conversion
`
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`:
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`.1”
`.1
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`,
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`'
`
`e same source ie
`
`.C.
`
`Code that does the SCSI conversion is #IFDEFed with #IFDEF SCSI.
`
`3.7 Ethernetbriver
`
`
`
`
`
`Windkiverciirrently.
`.
`___
`__
`-_
`,
`..
`..
`This can be modified to support the PC-NE chip in LANCE compatibility mode, or more likely,
`to
`supporfDMA master operations.
`
`3.8 Czrnflyura tion
`
`Verrazano will require configuration for various reasons. The prototype device will allow
`_
`
`''
`interface’
`'
`' a
`subsequent release. Subsequent releases will further support SNlV[P and
`interfaces.
`
`categories.
`
`3.8.1.1 FCP Options
`
`
`
`. _pg
`0
`Participate if Hard Address unavailable
`0
`Override World Wide Address (IEEE)
`
`3.8. 1.2 SCSI Options
`0
`Set ID for SCSI Initiator
`
`Use multiple SCSI response IDs
`0
`0 onse
`|.. "_ ,._.._.-
`O
`’1'I‘.
`
`Set SCSI Narrow/Wide
`0
`0 Use CDB LUN field
`
`3.5.1.3 Bridge Qptinns
`0
`Use Duec
`
`Specify/Enter Address Map
`0
`Use default Address Map
`0
`o
`
`-
`0
`Perform SCSI Discovery
`0 Use Target Addressing (LUN 0 Only)
`I
`FCP Target Addressing
`
`AT TURNEYS '
`E¥ES ONLY
`
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`Crossroads C_QnfidentiaLMaterial
`
`SCSI Target Addressing
`0
`I , EUITFF, Group Code, Disable)
`o
`SelecLECP LIJN format
`
`Set Buffer Memory parameters
`0 Data Buffer Size
`
`SefTachyon list parameters
`0
`0
`
`3.8.1 .4 Miscellaneous
`
`0 Override Ethernet IEEE address
`0
`
`&%
`0 Disable diagnostics
`
`&8£
`
`0 Menu based configuration
`0 Statistics reports
`I omload
`
` hEfiaw
`
`3.8.3 Telnet
`
`'
`
`Access to the same options and control given through the serial interface will be provided through
` .
`
`3.8.4 FTP
`
`Firmware download will be provided through Ethernet FTP.
`
`RHBbmmdmmfignmkmnmLfimkm3xhi¢Efl&MnnwgfimaeFC4P)
`
`378.6 HTTP
`
`C ia HTTP'in future release.
`
`3.9 Management
`
`3.9.1 SNMP
`
`MIB-II compliant private MIB defined in Crossroads CP4l00 SNl\I£P document.
`
`3.9.2 HTTP
`
`TBD, in future release
`
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`
`
`!.:-:5 --
`' =:-..-:::= ‘ .:.
`i‘‘vi‘‘iliIII‘_|l|
`’. .
`updates may allow diagnostics through SNMP, SCSI, or FCP interfaszes.
`'
`activity, and will leave the bridge in a power on condition. A configuration option will be provided to
`enable ordisable diafilostics other than at power reset,
`to help to prevent inadvertent data corruption.
`
`0 Manufacturing Test
`0
`Field Test
`0
`Return Test
`
`'FELN‘ET interface. Future
`
`4. 1 Diagnostic Tests
`
`Processor/Program memory
`Data paths
`Tachyon
`845
`
`Buffer memory
`Peripheral components
`
`
`
` !.-.r:.r.:
`‘
`'-‘:.-.:..i u‘-: v;
`bridging faults, and stuck-open faults.
`RAM pattern test - In addition to data path tests, pattern sensitive faults are tested. Patterns include
` , 55. .. and aa. . .. These patterns mvolvmg switching the most bits in a word and tend
`nun :
`.
`.
`'
`.
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`I
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`IO
`IO
`III
`I
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`faults that may not be covered by er ps.
`
`3 e) stuck-at faults,
`
`'
`
`4.14 lnjtialboot
`
`0 Wfi@ wEeH
`0
`Processor reads initial memory image (see RP User’s Manual, Ch. ll).mm
`NMI vector, and Control Table loads.
`
`4.1.2 LED visual test
`
`I
`
`A sweeping pattern is generated on the LEDs to bevisua11
`later stages of the bringup test to indicate the current stage of the test. Should a failure occur
` , the LEDS will indicate the last test being performed in which
`a failure is detected.
`
`4.1.3 Flash MemoryTRead1est
`
`0 data and verify against pre-computed checksum.
`
`V
`
`4.1.4 Instruction Memory - Read/write test
`
`Walking 1 word write/verify on address bits
`W‘alking 0 word write/verify on address bits
`Walking 1 word
`Walking 0 word write/verify on data bits
`Incrementing word count (address) write/verify on data bus
`‘
`/
`f
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`F\TTDRNEYS'
`EYES ONLY
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`o Quad-word write/verify
`0
`1-byte alignment Quad—word wn'te/verify
`.
`.
`.
`.
`O
`3-byte alignment Quad-word write/verify
`
`4.4.5SeI=ialGentreHeF«read%w|='rtetest
`
`H
`.1.
`i
`“
`The controller is put into ' -
`
`contoller and verified
`
`H,
`
`.
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`I
`
`0
`
`0
`
`I
`
`A PC or dumb terminal is connected to the serial port. A terminal session is started and a test
`n
`“In:
`I-I
`I‘
`‘I:
`I
`IIIVI
`I
`I0
`
`
`The 960 is programmed to echo inputchara
`emulator
`
`1. Verify operationo through serial port
`
`4.1.6 Ethernet Controller - readlwrite test
`
`4.1.7 PC1 Memory Read7Write Test
`
`Waflcing 1 word write/verify on address bits
` .
`Walkjng_1 word
`Walking 0 word write/verify on data bits
`Incrementing word count (address) write/verify for entire memory (4 M)
`hrcrenrerrtnrgword coum"(address) writes with YOU ms delay before venTy (verifies refresh
`circuitry)
`Incrementing byte count (address) write/verify (verifies byte accessing)
`Incrementing word count (address) for every multiple 1K-l word location (verify end of dram
`r vefify that surrounding words remain unchanged.
`
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`row accesses work). This should also verify that surrounding words remain unchanged.
`Incrementing word count (address) for every multiple 1K-3 word location (verify end of dram
` dmg words remain unchanged.
`lncrementingbvte I
`I
`.u-
`5
`-
`-n n Ig“-
`e
`:e..-::
`‘-- --:= -:--
`
`row accesses work). This should also verify that surrounding bytes remain unchanged.
`Incrementing byte count (address) for every multiple 4K-2 byte location (verify end of dram
`row
`unchanged.
`‘
`-
`'
`Incrementing byte count a
`'
`row accesses work). This should also verify that surrounding bytes remain unchanged.
`
`
`
`0
`0
`
`0
`
`0
`
`0
`
`0
`
`4.1.8 Tachyon
`
`0
`
`Register Test
`
`4.1.9 Symbios 875 SCSI Controller
`0
`Register tests
`eo—set1‘~tcst
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`o
`
`dalapathjest
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`Confidential Document
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