1 of 32
`
` CROSSROADS EXHIBIT 2317
`Oracle Corp., et al v. Crossroads Systems, Inc.
` IPR2014-01207 and IPR2014-1209
`
`CROSSROADS EXHIBIT
`Oracle Corp. v. Crossroads Systems, Inc.
`IPR2015-0(cid:1005)(cid:1004)(cid:1010)(cid:1008)
`
`2317
`
`

`
`_Verrazano Hardware Architecture
`
`Revision 2_1
`
`The infonnafipn contained in this document has been carefully Chcckcd and is believed to be entirely
`reliable. However. no responsibility is assumed for inaccuracies. Furthermore, Crossroads Systems. Inc...
`reserves medgmtochmgembdwmmrmdmwmfifimmfimmdm;m3¢
`des_ign without notice. Crossroads Systems, Inc... neither assumes any liability
`arising out of the application or use of any product, sofiware or circuit described herein, nor does it convey
`any HCCXISC
`I
`In
`3]: I»
`9
`1 II
`_
`o
`can
`, mu:
`, an IV. r. u 1 in
`.un--
`u
`.
` tc¢ No pan of this document may be reproduced or
`mined in any form
`or by any means, electronic, mechanical, for any purpose, without the express written permission of
`Crossroads Systems, Inc..
`
`
`
`© 1997 Crossroads Systems, Inc.. K11 riglits reserved.
`
`Crossroads Systems is a trademark ofcrossroads Sfirems, lm:.., i1rt!re‘USA .
`
`Copyright © 1997
`Crossroads Systems, I-nc..
`Building 1, MS 225
`6101 West Courtyard Drive
`Arttsfin, Teaeas 18730
`
`Fax:
`
`(512) 349-0300
`(54-2-) 349-0304
`
`info@crossroads.com
`
`http://www.crossroads.com
`
`Printfil in
`
`(iH'?BRNE¥S '
`EYES ONLY
`
`CRDS 1639.3
`
`Confidential Document
`
`2
`
`Crossroads Systems. "10-
`
`2or32
`
`CRDS-T 04689
`
`2 of 32
`
`

`
`Verrazano Hardware Architecture
`
`Revision 2.1
`
`
`
`
`The information contained herein is confidential in nature and is to be used only with written permission
`from Crossroads Systems, Inc.
`
`
`
`
`
`
`This document is only valid on the date printed. Please see the document author for information about the
`latest revision.
`
`
`
`
`ATTORNEYS '
`EYES ONLY
`
`GRUB 15391
`
`Confidential Document
`
`3 C
`
`éorsz
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`CRDS-T 04690
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`3 of 32
`
`

`
`Verrazano Hardware Architecture
`
`Revision 1_0
`
`Crossroads Systems Confidential Material
`
`mmooucnon ...................................................................................................................6
`
`Related Documents ......................................................................................................... ..6
`
`L 1
`
`.1
`
`2. H ...........................................................................................................6
`
`............................................. __5
`2.1 .m. . .................................
`2.2
`Component Comparison Notes........................................................................................ ..7
`2. 2. 1
`Processor.................................................................................................................. .. 8
`2.2.2 og ................................................... ._ 3
`2.2.3
`Ethemet Port............................................................................................................. .. 8
`2.2.4
`Fibre C?7anneFPort.................................................................................................... ..9
`2.2.5 . ........................................................... .. 10
`2.2.6
`SCSI Port.................................................................................................................. 13
`2.2. 7
`Generarcomponents.............................................................................................. .. 111
`2.2.8 P ......................................................... ,_ 15
`
`Enclosure ................................................................................................................... ..17
`2.3
`Features.................................................................................................................. .. 1-7
`2.3.1
`2.3.2 mmma ..................................................... .. 17
`2.3.3
`Color Scheme ......................................................................................................... .. 17
`2.3.4
`. Finish ...................................................................................................................... .. 1*?
`2.3% mmmf ................................................. .. 18
`2.3. 6
`Molded Front Bezel................................................................................................. .. 18
`2.4
`System I70 Panel ........................................................................................................... .. ‘r8
`2.4.1 P@d£m .................................................. .. 19
`2.4.2
`Labels ..................................................................................................................... .. 19
`2.5
`Mechan:cal'Features .......................................................................
`............................ .. +9
`2.5.1
`Air flow assLu1Jptioas_.......................... ....................................................... .. 19
`2.5.2
`Electromagnetic Shielding ............................................................................... 19
`2.5.3
`Desk Top................................................................................................................... 19
`2.5.41 %mMw .................................. .. 19
`2.6
`Enclosure Components .................................................................................................. .. 19
`2.6.1
`' Fan ...................................................................................................................... .. 26
`2.62
`Power Su,x.mI;:..............................................
`..................................................... 20
`2.6.3
`Printed Circuit Board............................................................................................. 20
`2.7
`Assemfily Considerations ................................................................................................29
`3.
`ENGINEERING DITA ...................................................................................................... ..29
`
`
`
`
`
`Standards ....................................................................................................................... ..29
`3.1
`3.2" Ha¢w ................................. ..21
`
`Nonvolatile storage ....................................................................................... .. 21
`3. 2. 1
`Interrupts......................................................................................................... 24
`3. 2. 2
`$2.3
`LczcaLbus................................................
`........................................................22
`3.24
`Ethernet PCI Bus ........................................................................................... 22
`3.3
`Memory Map ..........................................................................................................22
`4 .....................................................................................25
`
`QBURP ..............................................................................................................................25
`4.1
`472 P ......................................................25
`4.3
`Supervisory Space Registers.................................................................................26
`4.3.1
`Infiiamlemory Image (W11) .............................................................................. 26
`423.2
`other Supenzisoqr Space Registers ......
`...................................................... 27
`4.4
`‘fimers .............................................................................................................................27
`4.5
`lntegmtm?erip
`g-rTtmNE715—-
`-2-7
`E3455 QNLX
`
`CRDS 16395
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`Verrazano Hardware Architecture
`
`Revision 1.0
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`Crossroads Systems Confidential Material
`
`ATU Registers .................................................................................................... .. 28
`4. 5.1
`
`Memory Conimller ................. ..
`4.5.2
`fnfarnrpfcontreller.................................................................................................. .. 36
`4.5.3
`Ert#Gh‘6S‘fl6S .................................................................................................
`................31)
`
`5.
`
`51
`
`5.3
`53.“!
`5.3.2
`
`5.3.3
`53.4
`
`mmmmmnmmm .......................................................................................................um
`VxVanxsIHagnnsficsThsk ............................................................................................ "31
`Common Diagnostics Utilities ........................................................................................ ..31
`P3119771 Gmerator................................................................................................... .. 31
`Pattern . ............
`.............................................................................. ..31
`
`Register Walking bit tester...................................................................................... .. 32
`CZTGEDown ..; ............................................................32
`
`QJ'T_DB.NE¥S '
`EYES ONLY
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`Confidential Document
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`Page 5 oF32
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`

`
`Verrazano Hardware Architecture
`
`Revision 1.0
`
`Crossroads Systems Confidential Material
`
`'
`
`Llntroduciion
`
` dwm architecture of the CrossPoint 4100 (code named Verrazano).
`
`1. 1 Related Documents
`
`—
`-
`n
`In
`no
`n.a
`no
`Information necessary to use the product is presenterfin the CrossPoint Il'0U‘Reference Manual, the
`
`
`Reasoning behind design decisi d ein design detaik deerned prorietary are described in the
`Strategic Specification, the softcopy of which is available in
`“ kmt_$«.dx".
`The Statement of Requirements is available at “\\lnfinity\Source\Vermzano\doc\req\requirernents.doc“, and
`describes the functionality goals of the product.
`
`
`
`
`
`
`
`\
`.-.a
`Hun |
`
`devices. The harwarsbsystm coriscd of an embedded 80960 RISC controller, a programmable
`SCSI controller, a Fibre Channel controller, an Ethemct‘(8U2?3) controller, and a serial port. VTt"6tE other
`n
`....rno.o n
`u on
`
`---- “A
`‘ H
`'
`'
`|-
`-_4-- Vcrrmnoisoptirnized
`
`to support data flow bee Fibe Channel and SCSI controllers, and support out ofband connections
`via the Ethernet or serial ports. The 817930 controller has its own program execution memory space to
`
`
`2.1 Architecture
`
`The main controller of the system is an i960RP processor running VxWorlcs and handles the necessary
`protocol conversions to transfer data between the Fibre Channel and SCSI connections.
`
`The Verrazano architecture is surnrnarized in Figure 1. Vermzano hardware platform architecture.
`
`Q1-TDRNEYS'
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`Confidential Document
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`
`Verrazano Hardware Architecture
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`Revisaon 1.0
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`Crossroads Systems Confidential Material
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`Fibre Channel
`
`SCSI Bus
`
`“”“‘ E
`
`40 MHZ
`
`Ta°hV°"
`
`I
`.
`D . E
`Transceivers
`
`Bfifih‘
`
`TF1
`
`S-‘FMS-3C87'5
`
`®
`80 MHZ
`
`960 Local Bus
`
`FLASH
`
`‘ ‘
`
`Serial
`Cfitroner
`
`MHz
`
`
`
`RS-232E
`
`TOBaseT
`
` Figura—1.
`
`2.2 Component Comparison Notes
`This section describes in more detail the components used in the system.
`
`ATTORNEYS '
`EYES ONLY
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`Verrazano Hardware Architecture
`
`Revision 1_0
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`Crossroads Systems Confidential Material
`
`ZJLJ Processor
`
`The central controller in the system is an 80960RP processor. It contains an integrated JF core, a PCI-PCI
`bndge, and a local 960 bus. It is packaged in a 352-pin Ball Grid Array which requires a special process to
` mwud
`
`The 80960RP controls all the functions (modules) in the Verrazano product The 80960RP controls the
`0pcra['iO_fl I
`In
`I
`uhhll
`e I
`.
`I I
`:
`u
`can ~
`- u.
`u
`. u
`u u
`
`the operation of the Ethernet port through its primary PCI bus. The 80960RP controls the operation of the
`serial port through its local bus.
`'
`
`2.2.2 Serial Port
`
`The industry standard l655O UART is used. This component converts serial to parallel conversion on
`characters.
`
`
`
`
`
`
`Usin a 7.3728 MHz
`stal. the followrn baud rates are - ssrblc
`
`lfifll
`IMEEHHIIIEHEHIIIEMEEMEIIIflflflhfllliflflifiilll
`
`IIIIIIIIIIIIIIIIIIEDIIIIIIIEZIIIIIEIIIIIIIIIZIIIII
`IEIIIIIIIIIIIIIIIMEIIIIIIIRIIIIIMMHIIIIIIIIIIII
`N
`N
`01
`llfllllliiiIIHIIIIIIMMIIIIIIIIEZIIIIIEEIZIIIIIIEIIIII
`
`i E
`IEZJIIIIIIIIIIIIIIIIIIIIIIIIIIEEIIIIIIEHQEIIIIIIIIIIIII
`
`
`
`
`IEIIIIIIIIIHEIIIIlflmflllllllIIIIIII Izvfiw
`IEEIIII
`
`
`
`E t
`
`2.2.2.1 Transmr‘t‘terl‘Rec€ivEr
`
`'
`II
`' -K
`I
`-'0
`A gencral‘RS-232‘Seri
`
`implementation with the RJ-1 1, only 2 drive
`
`2.2.2.2 Serial Controllers
`
`
`.
`,
`
` JII . . '
`
`
`rs and 2 receivers are needed.
`
`R-S-232 line,
`The serial
`Z_372_8_MH; crystal, 245 hi-directional transceiver, address decode logic. address latch (shared with
`FLASH)
`
`21212.3 SeI=ialConnector(RJ-11)
`The serial connector used is a shielded filtered RJ-ll connector.
`
`‘
`
`
`
`2.2.3.1 Controller
`
`The Ethernet controller provides a bus master interface and supervises the Ethernet port.
` W%.
`
`2.2.3.1.‘! Ethernet Controller Interface Design
`
` ...._ 9 - '-.r.u .
`
`
`0
`'
`
`l. The software relocation strategy for the AM79C970A is used to setup the base address. This means
`
`
`
`the address on the bus followtng the first access to address 0x378 sets up the . . . .— . I . no
`
`
`
`2. y odceses are allowed.
`91
`V-5 _
`3. All DMA transfers must start on a wortfboundary.
`EYES ONLY
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`Verrazano Hardware Architecture
`
`Revision 1.0
`
`Crossroads Systems Confidential Material
`
`2. 2.3. 1. 1.2 Hardware Structure
`
`The Ethernet controller chip uses the 960R? Primary PCI bus to communicate to the processor.
`
`2.2.3.2 ma
`
`2.2.3.3 Connector (RJ~4‘5)
`The Ethernet connector is a pin through hole lU-43 slfielded connector.
`
`2.2.4 Fibre Channel Port
`
`The functionality of this port is based on Tachyon/TF1 capaliilites.
`
`2.2.4.1 Tachyon Controller
`The Tachyon controller chip provides all Fibre channel protocol support. Tachyon interrupts are mapped
`through the TI’! chip (see that section for details). Tachyon must be configuredTor a maximum write
` %.
`
`See the lip TACHYON specification for details on this component.
`
`2.2.4.2 rm chip
`This is an ASIC manufactured by lnterphase that is designed to interface Tachyon to a PCI bus. lt consists -
`of several FII-‘Os to buffer operations between the bosses. The Tachyon bus can run at ¢OMHz.
`It provides
` .
`0
`0 wait state as PCI master
`0
`5 volt part
`0
`programmzb1e‘PCl‘bm'st
`0 om serial EEPROM. It is optional. A central non—volatile element in Verrazano will
`store all appropriate unique information.
`Provides byte swap
`
`0
`
`TPI optionally requires 93C46 serial EEPROM to store contents of serial EEPROM. 64 bytes of extra
`information can be stored. mmlfid ‘FBI
`u:gisn:rsshould_he examined to determine if EEPROM can be omitted. See data list on p. 38 of Rev. B TPI
`spec.
`'
`
`
` -||.oun
`
`
`The following PC!
`_
`: K
`«-
`list, there is no need or a serial EEPOM 0 support. I
`'
`VendorID
`Devrcell)
`
`CIOOOOOOIIO
`
`E.. E11.“ 1“.
`Class code
`
`1..
`
`Header type
`B-EST
`
`Subsystem vendor ID
`Subsystem n)
`
`
`
`
`
`
`
`ATTORNEYS’
`
`EYES om.v
`
`Tach onINT
`
`CRD5 151.99
`
`Confiilentiarnocument
`
`9of32
`
`A CRDS-T 04696
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`9 of 32
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`

`
`Verrazano Hardware Architecture
`
`Revismn to
`
`Crossroads Systems Confidential Material
`
`'I?SLbu.<_ti.reeourrpari1y ermr.
`PCI bus errors
`
`Design Requirements
`,
`.
`PflHH$HEB41fixFH4anufiLQ
`Programming: configure both DMA channels to use byte swapping, as per errata 2 for TPI.
`
`2.2.4.3 Fibreclhannellldedla
`
`The connector is GLM based. See the GLM specification for details. This allows flexibility on choosing
`which media is needed. The supooncd GLM types are:
`0 Comm
`O
`ShortWaveQp_tic_al
`-
`Long Wave Optical
`
`2.2.5 Memory
`
`2.2.5.1 RP Memory controller
`The RP memory dcsigi consists of 4Mbyte of DRAM. Parity is not implemented.
`
`'Dae_RP 3.2-hi13_6-bit DRAM that is Extended Data Out (EDO)/fast page.
`Drives row-address strobes (320), column access strobes (7:0), and write enables (1:0). DRAM refresh
`provided as CKS”be1'ore RIS. Only 4"M‘byte ifliscd orrdre design.
`
`2.2.5.2 PC! memory controller
`
` consists of 4M'byte of DRAM plus parity.
`
`It IS implemented as custom logic with a PLD.
` It also supports 1-0-0-0-... write accesses (unless doing non-word
`write access).
`. The DRAM is EDO/fast page mode, lMx16. . The extended data out implementation
`requires one bank of memory to achieve
`& which includes two chips for actual data and one chip for parity.
`
`.
`
`The design is imp1ementcd"fi1 an MXETTFLEX l0K p:I!t‘('l0Kl0-3‘).
` e of design. The Altera tools allow for better control over tinting than discrete
`pans.
`
` fim is also used (l6v8-5) which runs from a 66Mhz clock. This device is used to give
`better control over the CAS signals to the drarn. Faster CAS signals basically give faster data access times.
`
`2.2.52.1 System Description
`
`A representative diagram of the PCI memory controller is shown below.
`
`3
`
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`

`
` mre
`
`Revision 1.0
`
` dS Systems Confidenfim/laterial
`
`
`
`J‘
`
`=
`
`g
`
`«_
`
`E
`1.
`
`DRAM PNVTY
`
`'
`
`on/w DATAIJLOI
`
`.
`
`. -
`
`r-cu Aopi. 01
`
`2c1.An;21..421
`
`we:-mom 21
`
`Pct-wrs1..e1
`
`PC! aE(3..n1
`vc: PAR
`pen PERR
`
`S
`
`J‘
`
`*5-J’
`
`‘6
`
`8J‘
`
`,4? §
`‘.5
`
`‘
`
`_
`
`E
`
`E
`
`:
`
` CR-B51-6491?
`
`2. 2. 5. 2. 2. 1 Gamer DOES support
`Gamer implements a subset of the l7CITunct1ons that are allowed These are themcuo
` m&M¢
`- memory read and write cycles including read multiple, cache write and invalidate, and read line
`ATTORNEYS ’
`(although their function is eqmvalcnt to the read and write cycles)
`E-Y-ESBNLY
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`Confidential Document
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`
`Meuamo
`
`Revision Lg
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`C
`
`is‘ Cfil|.ml.'
`
`.! rum
`!
`‘H
`.l” I
`nonw wg zero byte access)
`linear address sequencing (pci addr bits 0 and l are assumed to be 00)
`generates parity during data read cycles
`
`address bursting (1 1K word row ad)3~0»0-... burst access
`support for up to 4 M of drain (l0 address lines and 4 CAS lines)
`Deemlesbit
`
`OOIOOIOO
`
`2. 2. 5. 2. 2.2 Gamer does NOTsupport
`
`Garner implements a subset of the PCI functions that are allowed. These are the fiinctions that garner does
`NOT support:
`configuration cycles (a target abort will be generated)
`interrupt acknowledge cycles (a target abort will be generated)
`dual address cycles (a
` ted)
`lock function
`
`parity checking on address cycles
`liflfififfif
`
`full address decode (only PCI data bit 31 is used)
`nonlinear address sequencing (ie. PCI add: bits 0 and 1 not being equal to 00)
`I.
`I0
`I!!! II
`I
`V
`II
`Inn :5
`vyu
`--— vi-
`Pcenalcsé
`
`
`.
`
`,
`
`Reads-are 3-9=9=6...
`Writes are l-0-0—0...
`
`Non-word writes require an extra 5 wait states. Tlfis is due to having a single parity dram. The parity bits
`..-:.--
`---e.
`.5 ..-e -n- I
`-
`
`2.2.5.2.4 Device package
`
` -M8
`Note: This device type and package is available in the FLEXIOKIO, l0K20, IOIGO devices..
`
`2.2.52.5
` vmed 33 Mhz clock signal from the clock distribution network.
`Thulesign makes use of the fact that both the inverted and non-inverted elk signals are available to internal
`
` I. I‘ K
` In
`
`
`
`registersonthechrp. “- no In
`.
`..
`.
`_.y.
`..
`.
`..
`..
`original clock signal) available to internal registers. This allows some signals to be generated lSns earlier
`than normal. Running registers off both edges of the clock emulates 66Mhz operation for some signals.
`
`We chose to use the inverted clock (rather that the true form) because I/O registers on the chip have only
`the clock supplied available to them (ie. not both the inverted and true). Sinee most of the critical signals
`a
`..
`__ .
`- ' .._
`.I
`0
`.
`I
`II
`II
`I
`2 .
`at
`
`regiters still have the option ofusing either version ofthe cock.
`
`
`
`'
`
`2.2.5.2.6 CAS pal
`A faster PAL is used to implement the CKS signals to the UWXM. The pal uses a 66‘M1:iz clock to
` from the PCI Memory Controller chip.
`
`fiT
`EYES CINLX
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`
`Verrazano Hardware Architecture
`
`Revision 1_0
`
`2.2.5.2.] Denice Initialization
`
`Crossroads Systems Confidentia! Material
`
`The FLEX IOK devices are SRAM based, so they must be configured (loaded with a program) at power-on.
`
`
`
`to work with.
`
`2.2.5.3 SRAM
`
`NoSRINlwill'beus‘e‘dort‘tiD'3dcsigu.
`
`2.2.5.4 FLASH
`
`The AMD 29F0l6. It is a 2Mbyte part (1 byte wide). The AMD programming algorithm must be used
`when programming .
`
`2.2.6 SCSI Port
`
`Note: The Fast-20, P connector imply SCSI-3 Parallel Interface standard is being used. The SPI, Annex
`H,dcf1ncSa
`'
`0'0
`In.
`I
`II
`II
`re
`or;
`en we
`I:
`.u.
`.u
`u
`r
`
`hit wide l cable/port defined in SCSI-3. The optional Q cable adds another 32 bits of data. This
`is not implemented because the 53C87S does not support this mode. A shielded connector is used:bascd on
`the external connection
`p. Ll of_SP_I, rev Isa. Cable retention is with two 2-56 screws. Shield is DC connected to enclosure. The
`standard (SPI, rev 153., p. 8) recommends having two shielded connectors. with internal connections.
`
`The tmysical interface and differential drivers will be contained on a daughter card. This card is the SCSI
`Interface Board (SIB). The differential version is the primary SCSI bus interface. A single ended SIB will
`Ll
`‘III
`vs
`eunu-
`differential, twisted pair cable should be used for a maximum length of5m. Also, it should be shielded
`since used external. Terminator power source needs protection circuits, as per SP1, p. 23. The PCB will
`
`
`PCB. Note that power requirements of SCSI-3 for TERMPWR is greater than SCSI-. for, atlet
`‘one SCSI-3 device must supply power. Verrazano will supply the power as it may be the only SCSI-3
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`additional termination requirements are needed. Consider if Verrazano terminator: can be wired to support
`termination requirements of cable conversion as per Annex C. p. 66, SP1 rev 153.
`
`Skew and propagation delay: for SCSI wiring is defined in Annex E of SPI. Vcrrazano wiring must follow
`these guidelines. SCAM protocol support is to be determined.
`
`2.2.5.1 Controller
`
`The design is constrained to use Syrnbios Logic 53C875 SCSI controllers.
`
`2._2_.i2 SYM53C875
`
`Refer to the Syrnbios SYM53C875 for details.
`
`ATTORNEYS '
`EYES UNL7
`CRDS 16404’
` Iii
`external drivers aren e circuitry is cotained n the SCSI In rface oard (SIB). which
`allows the Verrazano product to be configured with a differennal or single-ended‘interface by populating
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`
`
`Confidentiafbocument
`
`Page T3 ot‘32
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`13 of32
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`CRDS-T 04700
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`13 of 32
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`
`Verrazano Hardware Architecture
`
`RBVlSl0n Lo
`
`Crossroads Systems Confidential Material
`
`The differential version contains tcnninating resistors and drivers, plus the connectors. The Single-ended
`version contains only connectors.
`
`2.2.5.4 Temtinatinn
`
`An Active termination required on all l6 data lines for SCSI-3.
`
`
`c uisuil
`nruunn
`A .
`.-:-.a.... ]—14..:ee29'
`.
`.7
`—
`.
`
`"Amplimite .050 Series Connectors...", p. l4. Pay special attention to “ CI'lON PIN" contacts, dimension
`of plated hole important. For board thiclmess of 0.062", use Contact tail lengths on ACTION PINS of
`4. .
`
`2.2.7 General Components
`
`2.7.7 .1 Clock D‘Istn‘but‘Ion
`
`Clock osciliators are used: highenost, or an clocks.
` is driven through a PLL clock buffer.
`Use an BOMIHZ clock to derive 40MHz. The 20MHz needed by Ethernet is derived from a 20 MHz crystal.
`There are three choi¢eS‘fi)T 20‘MTIz), single
`input-multiple ougpiitjnfljerg with skew matched gates, and PLL based buffers. The PLL buffets oficr
`lower skew and can be used to build multiple part buffer trees with virtually zero propagation delay. The
`single chip buffer is suitalile lbTfin‘6[I!13]3‘tO 1'0 devices.
`Eor Verrgo, 21 P14, buffer is used for the 33/66 MHz signals. It can be generated from a single 33MlIz
`source, and the phase alignment of the outpus is very good. Primary need is for the 66 MHz clock to be
`skewco
`The clock distribution trees are shown in . Skew is limited to 1 ns.
`
`.
`
`Garner-PLA
`
`
`
` Garner
`
`Ethernet 960RP
`
`
`SCSI Chip
` TF1
`
`Tachyon
`
`GLM
`
`Figure 3. Clock distribution trees.
`
`ATTORNEYS’
`EYES DNLV
`
`CRD5 $495
`
`Confidentiamocument
`
`Page 14 oF32
`
`Crossroads SysléTTP5.
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`14 of32
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`CRDS-T 04701
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`14 of 32
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`

`
`Verrazano Hardware Architecture
`
`Rewsion to
`
`Crossroads Systems Confidential Material
`
`2.2.7.2 Crystallclock Specifications
`
`2.2.7.2.1 Crystals
`
`
`1T
`
`7.3728 MHZ
`
`20-000 MR2
`
`
`
`
`
`
`
`
`limo
`
`
`
`
`
`
`
`
`
`
`
`Load Caacitznce
`
`xomo-70°C
`
`14m 0-70°C
`20-51=
`
`2.2.7.2.2 Clocks
`
`A PLL (phase lock loop) is used to generate the 2X frequencies. This saves the cost of the high frequency
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`
`
`
`
`2.2.L3Rese1QiLcuit
`
`The reset subsystem is shown in . The reset signal generation is accomplished by the 1232 supervisory
`circuit. This is an industry standard product that gencmtcs a 250 mS reset pulse on power-on, when
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`watch dg timer monitors the systems for inactivity.
`
`
`
`FlTTD‘RNEVS_'
`E3155 QNLY
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`CRDS 16406
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`Confidentiarbocumant
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`Page ‘r5 (W32
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`6msm
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`15 of32
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`CRDS-T 04702
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`

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`Verrazano Hardware Architecture
`
`Revision 1.0
`
`Crossroads Systems Confidential Material
`
`tuner
`
`500m 8 watchdog
`
`Figure 4. Reset subsystem.
`
`2.2.8 Peripheral IIO
`The peripheral [/0 provides a real time clock and debug interfaces (LEDS and LCD).
`Only word accesses are supportcd. Each device is an 83bit device, mappcd‘to the least significanrbytc of
`the word.
`
`2.2.8.1 Real time clocklcalendar
`
`.
`
`A PC industry standard real time clock is included. ffis referreifto as the “calcndax”‘thmughourthc
`
`
`This clock module contains an integral oscillator ancfbattery with a lifetime oFIO years. It contains IT4
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`and only 8 address bits are available.
`us, only the first 64 bytes of the calendar arc accessible.
`
`
`
`2.2.8.2 LCB interface
`| Wfifgchgjfiqcr
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`and command data to the display. The interface is a standard 14-pin interface, which could support
`multiple fin: displays ifiicsircd. Tlfis interface is includedTor debugging, and‘is not"intcndcd‘to be
`‘
`.
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`incac. K
`
`2.2.8.3 LED lnterfiaee
`
`
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`;
`0
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`thc board. The upper 4 bits are green, the lower 4 are orange. (This is subject to change based on
`availability oi'lCEDs). The EEDS are active low, is. write a 010 a biftiitfis OITIITC LED.
`
`¢¢fl
`2.2.8.4 Address Mapping
`The peripheral U0 is connected to the 960 bus ruing extra logic in Garner, the DRAM controller. The byte
`re - isters are ma 3. d‘to word'boundan'es. Use nornialjrlworac .
`
`
`
`
`
`0xC000 0000
`0xC000 0100
`°"C°°° °2°°
`
`
`
`
`
`
`
`”
`
`
`
`ATTORNEYS’
`EYES ONLY
`
`The production version will not support alfthcsc interfaces, but write cycles wil1‘bc accepted.
`
`CRDS 1 6407
`
`Confidential Document
`
`Page 16 of 32
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`CRDS-T 04703
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`

`
`.Verrazano Hardware Architecture
`
`Revision 1.0
`
`Crossroads Systems Confidential Material
`
`
`Rubbc: ufceru £6
` connectors and the power entry. In order to rack mount the
`
`
`
`..___...;oo_—_p
`4-IN-O
`
`Figure 5. Approximate size of enclosure. The depth is 9'. The height and
`Wrath are
`
`,
`
`necessary [or assembly.
`
`2.3.1 Features
`
`tS“‘(w), 24/." (ir),
`
`Enclosure feature highlights:
`0
`The enclosure consists of rbase, a cover,
`9" Cd)-
`The cover is painted. The cover mates with the base to form a tight “EMI" seal.
`The base IS not finis"hedbeyond matenaffinish. The front edge oftbe base is coveretfby the
`bezel,
`The bezel design is under development.
`Status LEDS are on the front to indicate operational modes, power. and fault conditions.
`
`-
`0
`
`o
`0
`
`2.12 lmplenientation Standards
`Must conform to ElA~3 10 rack mounting when configured for rack installation. Provision for rack
`
`,,mounting will be a modern shclfthat is 2U (3.5") high. It is assumed the shel}'w1'Ifbe no more that '7.”
`
`'
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`
`maroon (P-antone 209.
`Specifically:
`0 eflm
`0
`Bezel: Background matches box cover, Pantone 427C. Lettering in black. Crossroads “C” in Pantone -
`209C.
`
`2.3.4 Finish
`
`Off-white surfaces finished with medium texture.
`
`ATTORNEYS '
`EVESUNLY
`
`C905 1 6493
`
`Confidential Document
`
`Page 17 of 32
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`Crossroads Systems.
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`17 of32
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`CRDS-T 04704
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`17 of 32
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`

`
`Verrazano Hardware Architecture
`
`Re.,;s;on_1_0
`
`Crossroads Systems Confidential Material
`
` cmmm of cnclnsun:.js not painted a1T
`
`
`with an adheseck to ct to the front fee of the enclose base. It is intended t bezel is an
`interim solution until a molded front bezel can be incorpomtedinto production.
`.‘_
`
`
`
`
`' cnosuoaos
`
`I ¢
`
`Figute 6. Interim bezel design.
`
`2.3.6 Molded From Bezel
`In‘ an 01
`-III
`nun
`-
`I
`2-.'i ‘i
`iv-ivui;-Iui
`i ---'
`
`
`the use of tools. If fasteners are needed f r mounting. they will be installed from inside the enclosure.
`Figure 2 shows the components of the front panel layout. It is not intend to show the final placement of the
`beze .
`
`o
`
`Company Name and Logo
`
`Model NumberIName
`
`
`
`
`
`Figure 7. Front bezel layout. Provide for a configurable company logo and producflogo.
`The CP4100 bezel can be configured for specific customers by changing the company name and7or product
`-.
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`
`used to make the LEDs visible froin me: pl( idsW of L P sbsbly).
`If necessary, the LEDs can be moved to anywhere on the bezel wifit a slight design change. Tliis not
`
`
`
`that is they can be filled ifnot use
`labels should be considered.
`
`is no d reuireme vision for custog the
`
`2.4 5¥S1em [/0 Panel
`Metal panel thickness (base): 0.050 cold rolled steel.
`
`
`
`
`
`A1-TDRNE¥So
`EYES ONLY
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`CRDS 1640c
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`Confidential Document
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`Page 18 of 32
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`Crossroads Systems.
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`CRDS-T 04705
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`

`
`Verrazano Hardware Architecture
`
`Revision to
`
`Crossroads Systems Confidential Material
`
`2.4.1 Panel Gui-outs
`Panel cutouts should be accommodate a vertical tolerance of .040” and a horizontal tolerance of .020”.
`
`SCSI-3 connectors: AMP 786555-7 mounted on a “SIB board". The cut-cum in the enclosure :1 oversizcd
`arc on In 1 Ian‘
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`definedjn Vjtesse VSQ7 131 GLM data sheet. page 5. G
`envelope defined in general in
`e GLM
`Family specification, FCSI-301, page 5.
`R3-43711 cutout dcfincd’by Corcom
`’
` age 106-107 of Corcorn catalog.
`The power entry cut-out is defined for the Corcom PS series power entry modules. This power entry
`module shoulilhe evalualetffor alternate sources.
`
`2.4.2 Labels
`
`There are four labels on the rear. l/O panel of the enclosure.
`1. The prototype enclosure shalfbc labeled with: “This
`.4 ' l
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`
`dec mt
`teted per FCC rules prior to being offere for sale (including avrtisin.
`2. Label for power ranng. fine S126, and other mformafion required‘for U1 registrations. The labels will
`me
`3. A connector label for the serial port, Ethernet port, and the Fibre Channel.
`4. A SCSI differential or single euded1abel‘based on the SB card.
`
`
`will compl
`-
`
`
`2.5 Mechanical Features
`
`Base material: 18 gauge galvanized cold rolled steel.
`Cover material: 20 gauge galvanized cold rolled steel.
`
`2.5.1 Airflmuassumpjions
`Air intake is from through the fan opening in the rear of the enclosure to insure maximum fan life.. Air
`exhaust is through the sides of the enclosure, and since the enclosure does not take up a full rack wrdih,
` .
`
`2.5.2 Electromagnetic Shielding
`Enclosure top and bottom attach with a slip joint. A clip welded on the top insures a tight mating surface.
`
`
`chassis ground through standoffs.
`Provision for U0 filters:
`
`o
`
`
`
`The GLM connector is what we get. It make be necessary to include a gaset around the GLM
`_connector. A .250 clearance around the GLM cut-out is incorporated for this option.
`
`‘rhcscsiconfi
`' .' .r.l|-I Ill
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`-- ‘L n...
`
`flCCCSS3.fy.
`The power entry module is available in a filtered version if necessary.
`
`0
`
`2.5.3Desk'[op
`Feet are vinyl, attached with a machine screw to the enclosure.
`
`a
`
`.
`
`9'
`
`,
`
`mounting on a 19" rack.
`
`2.5.4 Rack Mtsurlfrny
`'9:
`'
`
`
`
`A s
`
`ATTORNEYS ,
`2. 6 Enclosure Components
`The must be a ground stucrthati . EVE-5 ONLY
`
`cmys rent. is
`
`Confidential Document
`
`Page 19 of 32
`
`Crossroads Systems-
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`19 of32
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`CRDS"'I' 04706
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`19 of 32
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`

`
`Verrazano Hardware Architecture
`
`Revisgon 1_o
`
`Crossroads Systems Confi