US007940809B2
`
`(12) United States Patent
`Lee
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 7,940,809 B2
`May 10, 201]
`
`DIGITAL VIDEO INTERFACE VVITH
`BI-DIRECTIONAL HALF-DUPLEX CLOCK
`CHANNEL USED AS AUXILIARY DATA
`CHANNEL
`
`Inventor: Bong-Joon Lee, Seoul (KR)
`
`Assignee: Synerchip Co. Ltd., Ilsinchu (TVJ)
`
`Notice:
`
`Subject to any disclaimer, tl1e term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 405 days.
`
`Kimet al.
`2002/0181608 Ali‘ 12/2002
`Schafer
`2004/0001447 Ali‘
`1/2004
`2004/0264482 A1'“* 12/2004 Kang etal.
`2008/0112371 A1“
`5/2008 Joshiet al.
`
`.. 375/295
`.. 370/280
`.. 370/401
`.................. .. 370/337
`
`OTHER PI IBI JCATIONS
`
`“Digital Visual Interface, DVI: Revision 10,” Apr. 2, 1999, Digital
`Display Working Group, pp. 1-76.
`“High-Definition Multimedia Interface: Specification Version 1.2a,”
`Dec. 14, 2005, pp. 1-193, HDMI Licensing. LLC.
`“High—Definiti0n Multimedia Interface: Specification Version 1.3a,”
`Nov. 10, 2006, pp. 1-276, IIDMI Licensing, I,I,C.
`“Unified Display Interface (UDI) Specification: Revision 1.0a Final,”
`Jul. 12, 2006, pp. 1-185.
`
`App]. No: 11/760,164
`
`Filed:
`
`Jun. 3, 2007
`
`Prior Publication Data
`
`US 2008/0247341 Al
`
`Oct. 9, 2008
`
`Related U.S. Application Data
`
`Provisional application No. 60/910,759, filed on Apr.
`9, 2007.
`
`Int. Cl.
`(2006.01)
`H04] 3/12
`U.S. Cl.
`..................................................... .. 370/525
`Field of Classification Search ...................... .. None
`See application file for complete search history.
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`1/2003 Hurvig et al.
`6,507,592 Bl *
`7,295,578 B1* 11/2007 Lyle et al.
`2001/0024430 A1 *
`9/2001
`
`370/503
`370/503
`
`* cited by examiner
`
`Primary Examiner — Chi H Pham
`Assistant Examiner — Fan Ng
`(74) A rrarney, Agent, or Firm — Elizabeth Kim
`
`(57)
`
`ABSTRACT
`
`A digital video interface system and method for communi-
`cating digital video data from a source device to a sink device
`is provided, where the clock channel is used to transmit data
`as well as clock signals in a bi-directional, half-duplex man-
`ner using time division multiplexing. The digital video inter-
`face system comprises one or more data channels configured
`to transmit digital video data from the source device to the
`sink device in time divisional multiplexing including a plu-
`rality of first time slots and second time slots, and a clock
`channel configured to transmit a clock signal from the source
`device to the sink device in the first time slots and configured
`to transmit additional data from the source device to the sink
`device or from the sink device to the source device in the
`second time slots.
`
`32 Claims, 4 Drawing Sheets
`
`1 1
`
`| (3+1 pairs)
`
`131
`
`Active
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`130
`129
`144 0
`121r\
`Present
`RGB IEEEIEEE
`Invention
`Clock
`120“
`
`138
`
`140
`
`142
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`

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`U.S. Patent
`
`May 10, 2011
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`
`US 7,940,809 B2
`
`1
`DIGITAL VIDEO INTERFACE WITH
`BI-DIRECTIOVAL HALF-DUPLEX CLOCK
`CHANNEL USED AS AUXILIARY DATA
`CHANNEL
`
`CROSS-R A F A RENC A TO RELATED
`APPLICATION
`
`This application claims priority under 35 L .S.C. §119(e)
`from co-pending U.S. Provisional Patent Application No.
`60/910,759, entitled “Digital Video Interface witl1 Bi-Direc-
`tional IIalf-Duplex Auxiliary Data Chamiel,” filed on Apr. 9,
`2007, which is incorporated by rcfcrcncc hcrcin in its cntircty.
`BACKGROUND OF TI IE INVENTION
`
`‘
`
`1. Field of the Invention
`The present invention relates to a digital video interface
`and, more specifically, to a digital video interface that uses the
`clock channel as an auxiliary data channel.
`2. Description of the Related Art
`Current digital video interfaces such as DVI (Digital Video
`Interface), HDMI (High-Defir1itior1 Multimedia Interface),
`and UDI (Unified Display Interface) typically use 3 or 6 RGB
`(Red, Green, and Blue vidco data) charmcls for thc main data I
`stream and 1 clock channel for a frequency reference, in order
`to transmit digital video data between a video source device
`(e.g., a digital video diskplayer) and a video sink device (eg,
`a high-definition television). Each channel (R, G, B, and
`clock) is typically comprised of a differential pair of two
`matched wires. The clock channel is used to transmit the
`frequency reference for tl1e digital video data from tl1e video
`source device to the video sink device, with the clock fre-
`qucncy bcing sct to thc Vidco data rate of the digital video
`data.
`In conventional digital video interfaces such as HDMI, tl1e
`R, G, B data channels transmit video data and control data in
`an alternating manner with time-division multiplexing. That
`is, video data is transmitted in certain time slots of the R, G,
`B data channels while control data is transmitted in other time
`slots of tl1e R, G, B data channels in an alternating manner.
`The clock signal is transmitted via the clock channel continu-
`ously rcgardlcss ofwhether the R, G, B data charmcls arc uscd
`to transmit digital video data or control data.
`However, once the RGB links become settled, the fre-
`quency information is no lo11ger needed by tl1e video sink
`side, because the receiver clock and data recovery circuit in
`the digital video interfaces can keep the link synchronized
`using the serial RGB data. Thus, conventional digital video
`interfaces use tl1e clock channel inefficiently, trar1sr11itting tl1e V
`clock signal continuously even when the frequency informa-
`tion may not bc nccdcd at the Vidco sink. This rcsults in
`inefiicient use of the clock charmel.
`Thus, there is a need for a technique for using the clock
`channel ofa digital video interface 111ore efliciently.
`
`SUMMARY OF THE INVENTION
`
`Embodiments of the present invention include a digital
`video interface system and method for communicating digital
`video data from a source device to a sink device, where the
`clock channel is used as an auxiliary data channel to transmit
`data as well as clock signals in a bi-directional, half-duplex
`manncr using time division multiplcxing. In onc cmbodi-
`ment, the digital video interface system comprises one or
`more data channels configured to transmit digital video data
`from the source device to the sink device, where the data
`
`2
`charmels are configured to operate in time divisional m11lti—
`plexing witl1 a plurality of first tir11e slots and second time
`slots, and a clock channel configured to transmit a clock
`signal from the source device to the sink device in the first
`time slots and configured to transmit additional data from the
`source device to the sink device in the second time slots. The
`clock channel may also be configured to transmit the addi-
`tional data in the opposite direction from thc sink dcvicc to thc
`source device in the second time slots.
`The digital video data are transmitted from the source
`device to the sink device via the data channels in the second
`time slots, while control data corresponding to the digital
`Vidco data arc transmitted from thc sourcc dcvicc to thc sink
`device via the data charmels ir1 tl1e first time slots. In addition,
`additional control data may be transmitted from the source
`device to the sink device via the clock channel in the first time
`slots.
`In one embodiment, the clock channel is configured to
`operate in one of a plurality of operation modes. In a fII'Sl
`mode, the clock signal is transmitted from the source device
`to the sink device via the clock channel in the first time slots.
`In a second mode, the additional data are transmitted from the
`source device to the sink device via the clock channel in the
`second time slots. Ir1 a third r11ode, the additional data are
`transmitted from the sink device to the source device via the
`clock charmel in the second time slots.
`Accordingly,
`the digital video interface system further
`comprises a source side transmitter configured to transmit the
`clock sigr1al in tlie first r11ode or tl1e additional data ir1 tl1e
`second mode to thc sink dcvicc via thc clock channcl, a sink
`side receiver configured to receive the clock signal in the first
`mode or the additional data in the second mode from the
`source device via the clock chamiel, a sink side transmitter
`configured to transmit tl1e additional data in tlie third mode to
`thc sourcc dcvicc via the clock charmcl, and a sourcc sidc
`receiver configured to receive the additional data ir1 the third
`mode from the sink device via the clock channel. The sink
`side transmitter is disabled in the first mode and the second
`mode, and tl1e source side transmitter is disabled i11 tl1e third
`mode.
`In one embodiment, the additional data transmitted via the
`clock channel from the source device to the sink device
`includes a control packet indicating whether subsequent pay-
`load data to be transmitted via the clock channel is in a first
`direction from the source device to the sink device or in a
`second direction fror11 tl1e sink device to tl1e source device.
`The digital video interface system of the present invention
`enables a bi-directional, half-duplex, auxiliary data channel
`using the clock channel of the digital video interface, yet
`neither changing the channel composition nor sacrificing the
`performance of tlie data cl1ar1r1els of tlie digital video inter-
`face. Thus, thc clock chaimcl is morc cfficicntly uscd, and
`more data can be communicated between the source device
`and the sink device without making any significant changes to
`the charmel composition of the digital video interfaces.
`The features and advantages described in the specification
`arc not all inclusivc and, in particular, many additional fca-
`tures and advantages will be apparent to one of ordinary skill
`in the art in view of the drawings, specification, and claims.
`Moreover, it should be noted that the language used in the
`specification has been principally selected for readability and
`instructional purposes, and may not have been selected to
`delineate or circumscribe the inventive subject matter.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The teachings of thc cmbodimcnts ofthe present invcntion
`can be readily understood by considering the following
`detailed description in conjunction with the accompanying
`drawings.
`
`

`
`US 7,940,809 B2
`
`3
`FIG. 1 is a conceptual block diagram illustrating the bi-
`directional half—duplex auxiliary data channel using the clock
`chamiel of the digital video interface, according to one
`embodiment of the present invention.
`FIG. 2 illustrates a l1alf-duplex link protocol and the trans-
`ceiver configurations at each TDM (time-division multiplex-
`ing) step for implementing the auxiliary channel using the
`clock charmel of the digital video interface, according to one
`embodiment of the present invention.
`FIG. 3 illustrates the hardware implementation of the bi-
`directional auxiliary data channel using the clock channel of
`the digital video interface, according to one embodiment of
`the present invention.
`FIG. 4 illustrates the operation of the clock data recovery
`(CDR) circuits of the RGB channels, according to one
`cmbodimcnt of thc prcscnt invcntion.
`DETAILED DESCRIPTION OF EMBODIMENTS
`
`The Figures (FIG.) and the following description relate to
`preferred emnodiments of tl1e present invention by way of
`illustration only. It should be noted that from the following
`discussion, altcmativc cmbodimcnts of thc structures and
`methods disc osed herein will be readily recognized as viable
`altematives that may be employed without departing from the ,
`principles of the claimed invention.
`Reference will now be made in detail to several embodi-
`ments of the present invention(s), examples of which are
`illustrated in the accompanying figures. It is noted that wher-
`ever practicable similar or like reference numbers may be
`used in the figures and may indicate similar or like f1u1ction-
`ality. The figures depict embodiments ofthe present invention
`for purposes of illustration only. One skilled in the art will
`readily recognize from the following description that alterna-
`tive embodiments of the structures and methods illustrated
`herein may be employed without departing from the prin-
`ciplcs of thc invention described herein.
`FIG. 1 is a conceptual block diagram illustrating the bi-
`directional half-duplex auxiliary data channel using tl1e clock
`channel of the digital video interface 100, according to one
`embodiment ofthe present invention. The digital video inter-
`face 100 transmits digital video data, control data, and clock
`signals from the video source device 102 to the video sink
`device 104. The digital video interface 100 includes transmit-
`ters
`108, 110, 112 for transmitting R, G, B digital video
`data, respectively, from the vidco source 102 over the video
`cables 106 to the video sink device 104. The digital video
`interface 100 also includes receivers
`114, 116, 118 for
`receiving the R, G, B digital video data, respectively, over
`video cables 106 at the video sink 104. The R, G, B channels ,
`are unidirectional from the video source 1 02 to the video sink
`104. The video cables 106 include 4 differential pairs (3+l) of
`2 wires, with each ofthe 4 pairs corresponding to tl1e R, G, B,
`and clock channels, respectively.
`The digital vidco interface 100 also includcs a clock chan-
`nel 120. The clock channel 120 includes a transmitter 124 for
`transmitting clock and data from the video source 102 to tl1e
`video sink 104 via tl1e video cable 106 and a receiver 126 for
`receiving the clock and data from the video source 102 at the
`video sink 104 via the video cable 106. Thus, unlike the clock
`chamiel of conventional digital video interfaces, the clock
`channel 120 of tl1e digital video interface 120 of the present
`invention is used to transmit both clock and data. The clock
`chamicl 120 also includes a transmitter 128 for transmitting
`data from the video sink 104 to the video source 102 via the
`video cable 106 and a receiver 122 for receiving the data from
`the video sink 104 at tl1e video source 102 via tl1e video cable
`
`4
`106. Thus, unlike the clock channel of conventional digital
`video interfaces, the clock charmel 120 of the digital video
`interface 120 ofthe present invention is bi-directional and can
`be used to transmit data in both directions between the video
`source 102 and thc vidco sink 104.
`As shown in FIG. 1, the conventional digital video inter-
`face protocol consists of repetitive ‘V—blank’ (Vertical Blank)
`and ‘active’ sequences (or time slots) alternating in a time-
`divisional multiplexing (TDM) manner. The RGB channels
`131 transmit control signals (Ctrl) during the V—blank
`sequences and video data (Data) during the active sequences
`in an alternating manner. The clock channel 130 of the con-
`ventional digital video interface continuously transmits the
`clock signal 129 rcgardlcss of whether the RGB channels are
`in the V—blar1k sequences or in the active sequences.
`In contrast, the clock chamiel 120 of the present invention
`is configured to transmit data (in addition to tl1e RGB data
`transmitted via the RGB channel) as well as clock signals.
`The clock charmel 120 of the present invention applies time-
`‘ division multiplexing (TDM) to the clock charmel to enhance
`the clock channel utility. The clock channel 120 is configured
`to transmit clock signals and additional control signals (e.g.,
`framc hcadcrs, control packcts, ctc.) 138 while thc RGB
`charmel 119 transmits control data (Ctrl) 143 during the
`V—blank sequences, and transmits data signals (Data) 140,
`142 while the RGB chamiel 119 transmits video data (Data)
`144 during the active sequences. The TDM of the clock chan-
`nel 120 is synchronized to the sequences (video channel
`periods) of the RGB channels 121.
`The data 140, 142 may be, for example, audio data or other
`types of data. The clock channel 120 transmits data signals
`140, 142 bidirectionally. For example, the data 140 is trans-
`mitted in the direction from the video source 102 to the video
`sink 104 via the clock charmel 120, and the data 142 is
`transmitted in tlie direction fron1 tl1e video sink 104 to the
`video source 102 via the clock channel 120. Thus, an auxil-
`iary data chamicl in addition to thc RGB channels 121 is
`enabled by the clock channel 120. The clock channel 120 is
`bi-directional but half-duplex iii the sense that data 140 and
`142 are in different directions but that data can be transmitted
`only uni-directionally at a time in each sequence. Thus, the
`clock charmel 120 does not transmit data in both directions at
`the same time. By adopting a half-duplex protocol, the aux-
`iliary data cl1am1el can be easily transformed to a bi-direc-
`tional link, providing great flexibility in dynamic allocation
`of bandwidth, compared to thc convcntional digital vidco
`interfaces.
`FIG. 2 illustrates a half-duplex link protocol and tl1e trans-
`ceiver configurations at each TDM step for implementing the
`auxiliary channel over the clock channel of the digital video
`interface, according to one embodiment ofthe present inven-
`tion. The clock-embedded, half-duplex data channel imple-
`mented over the clock channel 120 is comprised of trans-
`ceiver cores in each video source/sink sides and a TDM
`protocol to control thcm.
`As shown in FIG. 2, the clock channel 120 and transceiver
`pairs have 3 operation modes A, B, a11d C. In mode A, the
`clock pattern 138 is transmitted from the video source 102 to
`the video sink 104 via the clock channel 120 during V—blank
`sequences (time slots) of the RGB channels 121. In mode B,
`data 140 (NRZ (Non-Return to Zero) data) is transmitted
`from the video source 102 to the video sink 104 via the clock
`channel 120 during active sequences (time slots) of the RGB
`charmcls 121. In modc C, data 142 (NRZ pattern) is transmit-
`ted in the opposite direction from the video sink 104 to the
`video source 102 via the clock charmel during V—blank
`sequences of the RGB cha1111els 121. Therefore, in modes A
`
`,
`
`

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`US 7,940,809 B2
`
`5
`and B, the source receiver 122 and the sink transmitter 128 are
`disabled (as illustrated by the high impedance notation Z in
`the sink transmitter 128). Ir1 mode C, the source transmitter
`124 and the sink receiver 126 are disabled (as illustrated by
`the high impedance notation Z in the source transmitter 124).
`Referring to the example sequence of modes as shown in
`FIG. 2, in mode B 150, the data 140 (the frame header 170) is
`transmitted fro111 tl1e video source 102 to the video sink 104
`during the V—blank time slot via the clock channel 120 using
`the transmitter 124 and the receiver 126. In mode A 152, the
`clock signal 138 (which is the training sequence 172) is
`transmitted fror11 tl1e video source 102 to tl1e video sink 104
`during the V-blank time slot via the clock channel 120 using
`the transmitter 124 and the receiver 126. The clock sequence
`138 is used as a frequency reference for main RGB data
`channels while subsequent control packet sets up a link pro-
`tocol for the auxiliary data channel. In 111ode B 154, data 140
`which is a control packet 174 is transmitted from the video
`source 102 to the video sink 104 during the V—blank time slot
`via the clock channel 120 using the transmitter 124 and the
`receiver 126. The control packet 174 indicates wl1etl1er tl1e
`next data stream is upward (from sink to source) or downward
`(from source to sink), and the subsequent data stream is
`transferred accordingly during the active period. For
`example, the control packet 174 indicates downstream traffic.
`I11 addition, the control packet 174 may contains trair1ing
`sequences which help the auxiliary channel transmitter/re-
`ceiver switch their operation mode smoothly.
`Still in mode B 154, data 140 which is payload data 176,
`178 are transmitted fror11 the video source 102 to tl1e video
`sink 104 during the active time slot via the clock channel 120
`using the transmitter 124 andthe receiver 1 26. Additionally in
`mode B 154, data 140 which is a frame header 180 is also
`transmitted from the video source 102 to the video sink 104
`during aV-blank time slot via the clock channel 120 using the
`transmitter 124 and the receiver 126. Next, in mode A 156,
`another clock signal 138 (training sequence 182) is transmit-
`ted from the video source 102 to the video sink 104 during the
`V—blank time slot via the clock channel 120 using the trans-
`mitter 124 and the receiver 126. In mode B 158, data 140
`(control packet 182) is transmitted from the video source 102
`to the video sink 104 via the clock channel 120 during the
`V—blank time slot using the transmitter 124 and the receiver
`126. This time, the control packet 182 indicates that tl1e
`subsequent data stream will be transferred in the opposite
`direction from the video sink 104 to the video source 102.
`Thus, in mode C 160, data 142 (payload data 184, 186) is
`transmitted from the video sink 104 to the video source 102
`during the active time slot via the clock channel 120 using the
`transmitter 128 and the receiver 122.
`The auxiliary data charmel using the clock channel 120 of
`the present invention has an aggregate bandwidth comparable
`to one of tl1e r11air1 stream channels (R, G, or B). The source
`device can control
`the bandwidth allocation between
`upstream traffic and downstream traffic between the video
`source 102 and the video sink 104. Through a dynamic band-
`width allocation, the auxiliary channel ca11 be either dedicated
`to uni -directional communication or shared by tl1e upward or
`downward data stream s, maximizing bandwidth efficiency.
`FIG. 3 illustrates the hardware implementation 300 of the
`bi-directional auxiliary data charmel using the clock channel
`ofthe digital video interface, according to one embodiment of
`the present invention. Note that FIG. 3 only shows compo-
`nents necessary for illustrating the present invention, but the
`hardware may include other components not shown in FIG. 3
`in actual implementations. The hardware 300 includes a mas-
`ter li11k layer 302 corresponding to the video source 102, a
`
`.
`
`5
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`6
`slave link layer 304 corresponding to the video sink 104,
`wires 106 cormecting the master link layer 302 with the slave
`link layer 304, source side transmitter 124 for tl1e clock chan-
`nel 120, source side receiver 122 for the clock channel 120,
`sink side receiver 126 for the clock channel 120, and sink side
`transmitter 128 for the clock chamiel 120.
`The RGB charmels include latches 350 for storing RGB
`data, output drivers 352 for sending tl1e RGB data via the
`cable 106, receiver buffers 354 for receiving and storing the
`received RGB data, and clock data recovery (CDR) circuits
`356 for recovering the data and clock signals. RGB data are
`transmitted over tl1e RGB channels at tl1e frequency of tl1e
`transmitter clock Tclk as provided by the phase locked loop
`(PLL) 318 ofthe source side transmitter 124. Note that, in one
`embodiment, three identical data charmels exist (as shown in
`the three overlapping blocks in FIG. 3), one each for R, G, B.
`As will be explained in more detail witl1 reference to FIG. 4,
`the RGB CDRS 356 acquire a frequency lock during the
`period when the clock pattern 138 is transmitted over the
`‘ auxiliary charmel implemented by the clock channel 120,
`then acquire phase lock to tl1e incoming RGB data, ar1d pro-
`vide a stable receiver clock (Rclk) to the sink side transmitter
`128 while it delivers NRZ data from the sink device 104 to the
`source device 102.
`As illustrated above, the source side transmitter 124 is
`active i11 111ode A and r11ode B, and includes a phase locked
`loop (PLL) circuit 318, a multiplexer 316, a latch 322, and an
`output driver 324. The multiplexer 316 is configured to select
`the clock signal Tclk 138 in mode A and the data 140 in mode
`B ir1 response to a selection signal (not shown herein). The
`PLL 318 synchronizes to the clock signal Tclk and provides
`the synchronized clock signal to the latch 322, the multiplexer
`346 in the source side receiver 122, and the latches 350 in the
`RGB charmels. The latch 322 temporarily stores the output
`(either Tclk 138 in mode A or data 140 in r11ode B) of the
`multiplexer 316, and the output driver 324 transmits the
`stored clock signal Tclk 138 or data 140 over the cable 106 to
`the sink side receiver 126.
`The sink side receiver 126 is active in modeA and mode B,
`and includes a receiver buffer 340, a multiplexer 332, and a
`clock data recovery (CDR) circuit 330. The receiver buffer
`340 receives the clock signal Tclk 138 in mode A or the data
`140 in mode B as transmitted by the source side transmitter
`124. Ir1 mode A, tl1e received clock signal Tclk 138 is pro-
`, vided to the CDR circuit 356 of the RGB channels, so that the
`CDR circuit 356 can be tuned to the proper frequency to
`recover RGB data correctly. Additional detailed explanation
`regarding tl1e operation of the CDR circuit 356 is set forth
`below with reference to FIG . 4. In mode B the multiplexer 332
`selects the received data signal 140, but in mode A or mode C
`the multiplexer 332 selects the output clock 346 of the PLL
`336 for idling. In mode B, the CDR circuit 330 recovers NRZ
`data (data) fron1tl1e received data signal 140 and provides tl1e
`recovered NRZ data 360 to the synchronization circuitry 308
`of the slave link layer 304. The synchronization circuitry 308
`synchronizes the recovered NRZ data 360 with the receiver
`clock Rclk recovered by the CDR circuit 356 of the RGB
`channels.
`The sink side transmitter 128 is active in mode C, and
`includes a phase locked loop (PLL) circuit 366, a latch 334,
`and an output driver 338. The PLL 336 synchronizes to the
`receiver clock signal Rclk recovered by tl1e CDR circuit 356
`of the RGB channels, and provides the synchronized clock
`signal to the latch 334 and the multiplexer 332 in the sink side
`receiver 126. The latch 334 temporarily stores the data 142,
`and the output driver 338 sends the stored data 142 over the
`cable 106 to the source side receiver 122.
`
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`US 7,940,809 B2
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`7
`The source side receiver 122 is active in mode C, and
`includes a receiver buffer 326, a multiplexer 346, and a clock
`data recovery (CDR) circuit 328. The receiver buffer 326
`receives the data 142 in mode C as transmitted by the sink side
`transmitter 128 and provides it to the multiplexer 346. In
`mode C the multiplexer 346 selects the received data signal
`142, but in mode A or mode B the multiplexer 346 selects the
`output clock Tclk 344 of the PLL 318 for idling. In mode C,
`the CDR circuit 328 recovers NRZ data (data) from the
`received data signal 142 and provides the recovered NRZ data
`364 to the synchronization circuitry 306 of the master link
`layer 302. The synchronization circuitry 306 synchronizes
`the recovered NRZ data 364 with the transmitter clock Tclk.
`As illustrated above, tl1e architecture of each transmitter
`and receiver is different from conventional implementations,
`for example ir1 the reference clock configuration. The CDRs
`in the auxiliary data cl1a1mel (implemented by the clock chan-
`nel 120) alternates its reference between system clock (Tclk
`in Source a11d Rclk in Sink) a11d incoming data according to
`the link operation mode. In modes A and B, the source side
`CDR 328 is synchronized to the system clock (Tclk) from the
`PLL 318 while the sink side CDR 330 is synchronized to the
`incoming data (data 140). In mode C, the source side CDR
`328 is synchronized to the incoming data (data 142) while the .
`sink side CDR 330 is synchronized to the system clock (Rclk)
`from the PLL 336. When the CDRs 328, 330 change their
`reference, a lock—in period is needed for the CDR loops to
`settle. The training sequences 172, 182 in the control packets
`help the CDRs 328, 330 switch their reference quickly and
`smoothly.
`As shown in FIG. 3, the source and sink devices are in a
`single mesochronous clock system, in which all the building
`blocks operate in a single frequency domain but may not be
`aligned in phase. Thus, the phase synchronizationblocks 306,
`308 are used at the boundary of the two different clock
`domains, but the cost of such phase synchronization blocks
`306, 308 is very low because the data rates are exactly iden-
`tical. No flow control such as data rate conversion is required.
`Hence the phase synchronization blocks 306, 308 align the
`recovered data phase with the system clock phase to maxi-
`mize setup/hold time margins.
`As shown in FIG. 3, the master link layer 302 handles the
`TDM based half-duplex communication protocol and
`dynamically allocates the auxiliary channel bandwidth to the
`upward or downward data stream. Since the uni-directional
`RGB chaimels are independent and identical to conventional
`DVI and HDMI RGB channels, the digital video interface of
`the present invention can be fully compatible with conven-
`tional digital video interfaces by simply disabling the TDM ,
`operation in the clock charmel 120.
`FIG. 4 illustrates the operation of the clock data recovery
`(CDR) circuits 356 of the RGB channels, according to one
`embodiment of the present invention. Each of the CDR cir-
`cuits 356 for the RGB charmel includes a data recovery loop
`402 and a frequency tracking loop 404. The data recovery
`loop 402 recovers RGB data from the NRZ RGB data
`received over the RGB data channel using conventional data
`recovery circuits and techniques. The frequency tracking
`loop 404 tunes the center frequency ofthe CDR circuit 356 to
`the NRZ data rate of the RGB channel using conventional
`frequency tracking techniques, and the data recovery loop
`402 also regenerates the receiver clock signal Rclk based on
`the tuned (locked) frequency. However, the data recovery
`loop 402 and the frequency tracking loop 404 are unique and
`different from the conventional data recovery loop and the
`conventional frequency tracking loop in conventional CDR
`
`8
`in that they are enabled or
`circuits for the RGB channel,
`disabled also in a time-division multiplexed manner.
`Specifically, the data recovery loop 402 and the frequency
`tracking loop 404 are enabled or disabled depending upon the
`operation modes of the auxiliary data channel implemented
`by the clock channel 120 and what auxiliary channel data
`(clock Tclk 138 or data 140) are received over the auxiliary
`data channel. As shown in FIG. 4 together with reference to
`FIG. 3, when the receiver buffer 340 receives and outputs the
`clock signal Tclk 138 over the auxiliary data channel during
`the V—blank period of the RGB channel, the CDR 356 is in
`frequency tracking mode. In the frequency tracking mode, the
`frequency tracking loop 404 is enabled, tuning the center
`frequency of the CDR circuit 356 to the NRZ data rate of the
`RGB charmel, while the data recovery loop 402 is disabled.
`Once the frequency tuning is done, the freq_lock signal is
`asserted from the frequency tracking loop 404 to the data
`recovery loop 402. This freq_lock signal enables the data
`recovery loop 402 to recover the RGB data from the NRZ
`‘ RGB data and regenerate the receiver clock Rclk,