MELVIN RAY MERCER
`Independent Consultant
`and
`Professor Emeritus
`Department of Electrical and Computer Engineering
`Texas A & M University
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`BUSINESS ADDRESS:
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`EDUCATION:
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`PROFESSIONAL REGISTRATION: Texas #62016
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`ACADEMIC POSITIONS:
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`Texas A & M University, Professor Emeritus, 2006
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`Texas A & M University, Professor and Chair Holder, 1/95-9/2005
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`University of Texas at Austin, Professor, 9/91-12/94
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`University of Texas at Austin, Associate Professor, 9/87-8/91
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`University of Texas at Austin, Assistant Professor, 1/83-8/87
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`University of Texas at San Antonio, Lecturer, 1977-80
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`OTHER PROFESSIONAL EXPERIENCE:
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`Independent Consultant for Mercer and Associates, Inc., Dallas, TX 1984-present
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`Member of Technical Staff, Bell Laboratories, Murray Hill, NJ, 1980-83
`Member of Technical Staff, Hewlett-Packard Laboratories, Palo Alto, CA, 1973-77
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`Research/Development Engineer, GTE Sylvania, Mountain View, CA, 1968-73
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`(in 2000, GTE merged with Bell Atlantic to form Verizon)
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`CONSULTING:
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`Hale and Dorr, Boston, Massachusetts, Intel, 2001
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`Fulbright and Jaworski, Houston, TX, Emachines, 1999-2000
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`Akin, Gump, Strauss, Hauer & Feld, 2000
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`Harris Corporation, Melbourne, FL, 1999-2001
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`SigmaTel, Austin, TX, 1999-2000
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`Martin Gruppen, Denmark, 1999
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`AT&T, Inc., Murray Hill, NJ, 1995-98
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`Sematech, Inc., Austin, TX 1994
`Teradyne, Inc., Boston, MA, 1993-94
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`Integri-Test Corp., Commack, NY 1993
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`Spectrum Information Technologies, Dallas, TX 1993
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`Motorola Semiconductor, Austin, TX, 1987-88, 1991-99
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`Rockwell International, Newport Beach, CA, 1991, 1995
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`Teltech Resource Network, Minneapolis, MN, 1986-93
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`Cimflex Teknowledge, Pittsburgh, PA, 1989-90
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`IBM, Inc., Austin, TX, 1984, 1988-90
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`The University of Texas at Austin, Ph.D., 1980
`Stanford University, MS, 1971
`Texas Tech University, BS, 1968
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`Mercer, p. 1
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`10801 Branch Oaks Circle
`Dallas, TX 75230
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`PHONE:
`CELL:
`FAX:
`EMAIL:
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`(469) 458-3770
`(979) 676-3109
`(866) 769-1967
`ray@rmercer.com
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`VALMONT 2016
`Lindsay v. Valmont
`IPR2015-01039
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`MCC, Austin, TX, 1989
`CBS, New York, NY, 1985-86
`Harris Data Communications Inc., Dallas, TX, 1984-86
`Cellular Technology, Inc., Lubbock, TX 1985 - 87
`Attorney General's Office, State of Texas, Austin, TX, 1984
`Lockheed Missiles and Space Company, Austin, TX, 1983
`Rothe Development Company, San Antonio, TX, 1979
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`TECHNOLOGY BASED BUSINESS EXPERIENCE:
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`Founder, Technical Advisor, and Owner of Conference Management Services, Inc., 1993 – 2013
`Technical Advisory Board Member, Test Systems Strategies, Inc., Beaverton, OR, 1988-93
`Advisor and Survey Developer, IBM, Inc., Austin, TX, 1988-90
`Advisor, Early Cellular Telephone Minority Carriers, Lubbock, Texas, 1983 - 1987
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`HONORS AND AWARDS:
`National and International:
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`Fellow of the Institute of Electrical and Electronics Engineers, 1994
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`National Science Foundation -- Presidential Young Investigator, 1986
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`Best Paper Award, VLSI Test Conference, Dana Point, CA, 1999
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`Best Paper Award, Design Automation Conference, San Francisco, CA, 1991
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`Best Paper Award, International Test Conference, Philadelphia, PA, 1982
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`Best Paper Award, Honorable Mention, Int. Test Conference, Washington, DC, 1988
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`Texas Tech Electrical Engineering Academy, Lubbock, Texas, 1999
`Who's Who in America, 48th, 49th, 50th, 56th, 58th, 59th, 63rd, 67th and 69th Editions, 1994, 1995, 1996,
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`2000, 2002, 2004, 2005, 2009, 2012, and 2015
`Who's Who in American Education, 3rd Edition, 1992-1993
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`Who's Who in America Finance and Industry, 31st Edition, 1999
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`Who's Who of Emerging Leaders in America, 7th Edition, 1990 & 1992
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`Who's Who in Science and Engineering, 3rd, 4th, 7th, 9th & 10th Editions, 2003-2009
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`Who's Who in the South and Southwest, 21st, 22nd, 23rd, 24th, 37th, 38th , 40th & 41st Editions,
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`1988, 1990, 1992, 1995, 2011, 2012, 2013, 2014, & 2015
`Who's Who in the World, 10th, 11th, 17th, and 21st Editions, 1991, 1992, 2000 & 2004
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`Meritorious Service Award, IEEE Computer Society, 1993
`Faculty Nominator and Advisor for Jennifer Dworak – Recipient of a National Science Foundation
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`Graduate Research Fellowship 2000 – 2003
`Co-Author and Advisor for Jennifer Dworak and Amy Wang – Recipient of the “IEEE Test Technology
`Technical Council Naveena Nagi Award for 2004” presented in Napa Valley, California
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`Local:
`Computer Engineering Chair in Electrical Engineering, A&M, 1995-2005
`Faculty Nominator and Advisor for Jennifer Dworak – Recipient of The Ethel Ashworth-Tsutsui
`Memorial Award for Graduate Student Research 2002
`Texas A&M Outstanding Masters Thesis Award: Jennifer Dworak, 1999-2000
`Listed in the Texas A&M Center for Teaching Excellence 2002 Eagle Award Booklet, May 3, 2002
`Temple Foundation Endowed Professorship #3 in Engineering, UT, 1991-94
`Engineering Foundation Endowed Faculty Fellowship in Engineering, UT, 1990-91
`Werner W. Dornberger Centennial Teaching Fellowship in Engineering, UT, 1984-90
`Engineering Foundation Faculty Award, UT, 1986
`Outstanding Doctoral Dissertation: Honorable Mention, T. E. Kirkland, UT, 1986-87
`MCC Sponsored Outstanding Student Paper Award: Bill Underwood, 1991-92
`High School Valedictorian
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`Mercer, p. 2
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`PROFESSIONAL SOCIETIES AND ACTIVITIES:
`Government:
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`National Science Foundation Advisory Committee for Microelectronic Information
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`Processing Systems (MIPS), 1987-88
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`National Science Foundation Engineering Initiation Awards Evaluation Panel Member
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`––Design, Tools and Test Program, 1987 and 1993
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`National Science Foundation Advisory Workshops
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`Future of Testing and Design for Testability, June 30, 1989
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`Future of VLSI and Computer-Aided Design, October 15-16, 1992
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`Presentation to the Texas State Board of Registration for Professional Engineers on
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`Computer Engineering and suitable criteria for registration, 1985
`Journals and Archival Publications:
`Guest Editor, Special Issue on Design for Testability, IEEE Design and Test of Computers, October, 1986
`Editor, Design for Testability, IEEE Design and Test of Computers, 1985-88
`Guest Editor, IEEE Transactions on Computer-Aided Design of Circuits and Systems, 1988
`Guest Editor, Special Issue on 1989 International Test Conference, IEEE Design and Test of Computers,
`April 1990.
`Editorial Board Member, Journal of Electronic Testing: Theory and Applications, 1990-92
`Editorial Advisory Board, Microelectronics Journal: Circuits and Systems, 2000 – 2003
`Conferences and Workshops:
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`Finance Chair, Third IEEE Workshop on Microprocessor Test and Verification, (MTV’02), 2002
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`Program Committee, Ninth IEEE International Test Synthesis Workshop, (ITSW), 2002
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`Program Committee, Second IEEE Workshop on Microprocessor Test and Verification, (MTV 99), 1999
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`Exhibits Chairman, Fault-Tolerant Computing Symposium 1994
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`Planning Chairman, International Test Conference, 1992-93
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`Marketing Vice-Chairman, International Test Conference, 1990
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`Program Chairman, International Test Conference, 1989
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`Program Vice-Chairman, International Test Conference, 1988
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`Steering Committee, International Test Conference, 1987-93
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`Program Committee, International Test Conference, 1986-89
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`Program Committee, IEEE Design for Testability Workshop, 1988-96
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`Program Committee, International Conference on Computer-Aided Design, 1987
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`Program Committee, First MCC-University Research Symposium, Austin, TX, 1987
`Local Offices:
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`Vice-Chairman, Central Texas Chapter, IEEE Computer Society, 1983-85
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`Chairman, Central Texas Chapter, IEEE Computer Society, 1985-86
`Memberships:
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`Institute of Electrical and Electronics Engineers (IEEE), Fellow 1994, Life Member 2012
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`TEXAS A & M UNIVERSITY COMMITTEE ASSIGNMENTS:
`City/County Committees:
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`Bryan/College Station Economic Development Group
`Marketing Committee for the Information Technology Task Force, 1999
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`University Committees:
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`Search Committee -- Associate Provost for Information Technology, 1997-99
`Research Infrastructure Committee, 1998-99
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`College of Engineering Committees:
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`Computer Engineering Committee, Chairman, 2002
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`Tenure and Promotion Committee, 2000 - 2002
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`Computer Engineering Committee, Chairman, 1996-1999
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`Chair Holders Committee, 1995-
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`Compaq Liaison Committee 1996-
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`Computer Science Department Head Search Committee, 1996-98
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`ABET Review Committee, Computer Engineering, 1995
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`Mercer, p. 3
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`ABET Review Committee, Computer Engineering, Chair, 1998
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`Ad Hoc Committee to Study the Merger of the CS and EE Departments, 1996
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`PAM Advisory Committee, 1995-96
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`Spencer J. Buchanan Professorship Review Committee, 1997
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`Departmental Committees:
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`Computer Engineering Area Leader, 1995-present
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`Faculty Search Committee for the Computer Engineering Group, Chairman, 1995-present
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`Teaching Assignments for the Computer Engineering Group, 1995-present
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`Tenure and Promotion Committee, 1996-98, 2000-02, 2003-2005
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`Graduate Studies Committee, 1996-present
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`Faculty Advisory Committee, 1997-99
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`Strategic Planning Committee, 1998
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`Search Committee for the Eugene Webb Professorship, 1998-99
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`Search Committee for the Texas Instruments Jack Kilby Chair in Analog Engineering, 1998-99
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`UNIVERSITY OF TEXAS COMMITTEE ASSIGNMENTS:
`University Committees:
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`Presentation to the MCC Site Selection Committee, the MCC Fact Finding Committee,
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`and the MCC Technology Advisory Board, 1983
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`Science and Engineering Development Program Review for Dr. Thomas Everhart
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`and Dr. Frank Press, National Academy of Sciences, 1984
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`Parking and Traffic Panel of the General Faculty, 1983-85
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`Hearing Officer for Faculty Grievances, 1987-88
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`University Council Representative, 1992-94
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`University Faculty Senate, 1992-94
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`Faculty Governance Committee, 1992-93
`College of Engineering Committees:
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`Scholastic Appeals Committee, 1983-84
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`Ad Hoc Committee to Prepare a DOD Proposal for a Software Engr. Institute, 1984
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`State Agency Research Forum Speaker, May 10, 1984
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`Continuing Engineering Studies Committee, 1984-85
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`Ad Hoc Committee on Microelectronics and Computer Engineering, 1983-85
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`Presentation to Heads of State Agencies and Selected Federal Personnel, 1985
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`Computer Committee, 1985-86
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`GEC Faculty Meritorious Service Award Committee, 1987
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`Presentation to Industrial Representatives Research Forum, April 30, 1987
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`Undergraduate Degree Program Evaluation, 1986-88
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`Continuing Engineering Studies Committee, 1986-88
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`Televised Instruction Committee, 1987-91
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`Briefing for AT&T Visitors, November 21, 1991
`Departmental Committees:
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`Committee on CAD/CAM and Advanced Graphics, 1983
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`Chairman, MCC Graduate Fellowships Recruiting Poster Committee, 1984
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`Microelectronics and Computer Engineering Research Support Committee, 1984
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`Chairman, Computation, Word Processing, and Telecom. Committee, 1984-85
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`Chairman, Industrial Liaison Committee, 1985-86
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`Computation, Word Processing, and Telecommunications Committee, 1985-86
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`Equipment Committee, 1984-86
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`ABET Accreditation for ECE in Computer Engineering (Site Visit), 1987
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`VLSI Course Area Committee, 1986-87
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`Chairman, Local Area Network Committee, 1987-88
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`Search Committee for New ECE Chairman, 1988-89
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`ECE Visiting Committee, 1989-90
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`Chairman, Annual Research Review Committee, 1988-92
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`Mercer, p. 4
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`Graduate Student Recruitment at Stanford University, January 1992
`Alumni Committee 1992-93
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`Computer Engineering Research Center Executive Committee, 1988-93
`Computer Sciences Liaison, 1988-93
`Digital Systems Course Area Committee, 1988-93
`Chairman, Teaching Effectiveness Committee, 1991-94
`Budget Council, 1991-94
`Computer Engineering Representative to the ECE Area Committee 1993-94
`Junior Faculty Recruiting Committee, Computer Engineering, 1985-94
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`PUBLICATIONS:
`Refereed Conference and Archival Journal Publications:
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`M. R. Mercer and V. D. Agrawal, "A Novel Clocking Technique for VLSI Circuit Testability," IEEE Journal of
`Solid-State Circuits, Vol. SC-19, April 1984, pp. 207-212.
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`K. S. Hwang and M. R. Mercer, "Derivation and Refinement of Fanout Constraints to Generate Tests in
`Combinational Logic Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
`October 1986, pp. 564-572.
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`T. Kirkland and M. R. Mercer, "Automatic Test Pattern Generation Algorithms," IEEE Design and Test of
`Computers, June 1988, pp. 43-55.
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`E. S. Park, M. R. Mercer, and T. W. Williams, "A Statistical Model for Delay-Fault Testing," IEEE Design and Test
`of Computers, February 1989, pp. 45-55. { NSF, ONR}
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`D. E. Ross, K. M. Butler, and M. R. Mercer, "Exact Ordered Binary Decision Diagram Size When Representing
`Classes of Symmetric Functions," Journal of Electronic Testing: Theory and Applications, vol. 2, no. 3, August
`1991, pp. 243-259. { NSF}
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`E. S. Park, M. R. Mercer, and T. W. Williams, "The Total Delay Fault Model and Statistical Delay Fault Coverage,"
`IEEE Transactions on Computers, vol. 41, no. 6, June 1992, pp. 688-698. { NSF, ONR}
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`E. S. Park and M. R. Mercer, "An Efficient Delay Test Generation System for Combinational Logic Circuits," IEEE
`Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 11, no. 7, July 1992, pp. 926-938.
`{NSF, ONR, TATP}
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`R. Kapur and M. R. Mercer, "Bounding Signal Probabilities for Testability Measurement Using Conditional
`Syndromes," IEEE Transactions on Computers, vol. 41, no. 12, December 1992, pp. 1580-1588. { NSF, ONR,
`SRC}
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`M. Heap and M. R. Mercer, "Least Upper Bounds on OBDD Sizes," IEEE Transactions on Computers, accepted for
`publication, July 1993.
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`C. Oh and M. R. Mercer, "Efficient Logic-Level Timing Analysis Using Constraint-Guided Critical Path Search,"
`IEEE Transactions on VLSI, September 1996. {ONR}
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`J. Dworak, J. Wicker, S. Lee, M. R. Grimaila, K. M. Butler, B. Stewart, L-C. Wang, and M. R. Mercer, "Defect-
`Oriented Testing and Defective-Part-Level Prediction,” IEEE Design and Test of Computers, January-February,
`2001, Vol. 18, No. 1, pp. 31 - 41. {SRC, NSF, TATP}
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`Mercer, p. 5
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`M. R. Mercer, V. D. Agrawal and C. M. Roman, "Test Generation for Highly Sequential Scan-Testable Circuits
`through Logic Transformation," International Test Conference 1981, Philadelphia, PA, October 1981, pp. 561-565.
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`V. D. Agrawal and M. R. Mercer, "Testability Measures -- What Do They Tell Us?," International Test Conference
`1982, Philadelphia, PA, November 1982, pp. 391-396. (Best Paper of the 1982 ITC)
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`M. R. Mercer and B. Underwood, "Correlating Testability with Fault Detection," International Test Conference
`1984, Philadelphia, PA, October 1984, pp. 697-704.
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`E. Schell and M. R. Mercer, "CADTOOLS: A CAD Algorithm Development System," The ACM/IEEE Design
`Automation Conference (22nd) Proceedings, Las Vegas, NV, June 23-26, 1985, pp. 658-666.
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`J. Salick and M. R. Mercer, "Built-In Self Test Input Generator for Programmable Logic Arrays," International Test
`Conference 1985, Philadelphia, PA, November 1985, pp. 115-125.
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`K. S. Hwang and M. R. Mercer, "Derivation and Refinement of Fanout Constraints to Generate Tests in
`Combinational Logic Circuits," IEEE International Conference on Computer-Aided Design, Santa Clara, CA,
`November 1985, pp. 10-12.
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`K. S. Hwang and M. R. Mercer, "Informed Test Generation Guidance Using Partially Specified Fanout Constraints,"
`1986 International Test Conference, Washington, DC, September 8, 1986, pp. 113-119.
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`R. K. Gaede, M. R. Mercer and B. Underwood, "Calculation of Greatest Lower Bounds Obtainable by the Cutting
`Algorithm," 1986 International Test Conference, Washington, DC, September 9, 1986, pp. 498-505.
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`M. R. Mercer, "Logic Elements for Universally Testable Circuits," 1986 International Test Conference,
`Washington, DC, September 9, 1986, pp. 493-497.
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`T. E. Kirkland and M. R. Mercer, "A Two Level Guidance Heuristic for ATPG," IEEE Fall Joint Computer
`Conference, Dallas, TX, November 2-6, 1986, pp. 841-847.
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`B. Underwood, J. Salick, M. R. Mercer and J. Kuban, "An Automatic Test Pattern Generation Algorithm for PLAs,"
`IEEE International Conference on Computer-Aided Design, Santa Clara, CA, November 10-13, 1986, pp. 152-155.
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`T. Kirkland and M. R. Mercer, "A Topological Search Algorithm for ATPG," The ACM/IEEE Design Automation
`Conference (24th) Proceedings, Miami, FL, June 28-July 1, 1987, pp. 502-508.
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`S. P. Smith, M. R. Mercer and B. Brock, "Demand Driven Simulation: BACKSIM," The ACM/IEEE Design
`Automation Conference (24th) Proceedings, Miami, FL, June 28-July 1, 1987, pp. 181-187.
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`E. J. Aas and M. R. Mercer, "Algebraic and Structural Computation of Signal Probability and Fault Detectability in
`Combinational Circuits," Proceedings of the 17th International Symposium on Fault-Tolerant Computing,
`Pittsburgh, PA, July 6-8, 1987, pp. 72-77.
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`D. E. Ross and M. R. Mercer, "WAVE, A Concurrent Approach to Combinational Test Pattern Generation,"
`Proceedings of the MCC-University Research Symposium, Austin, TX, July 14, 1987.
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`E. S. Park and M. R. Mercer, "Robust and Nonrobust Tests for Path Delay Faults of a Combinational Circuit," Proc.
`1987 International Test Conference, Washington, DC, September 1-3, 1987, pp. 1027-1034.
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`S. P. Smith, B. Underwood and M. R. Mercer, "An Analysis of Several Approaches to Circuit Partitioning for
`Parallel Logic Simulation," Proc. 1987 IEEE International Conference on Computer Design, Rye Brook, NY,
`October 5-8, 1987, pp. 664-667.
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`Mercer, p. 6
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`C. T. Glover and M. R. Mercer, "A Method of Delay Fault Test Generation," Proc. 25th ACM/IEEE Design
`Automation Conference, Anaheim, CA, June 13-15, 1988, pp. 90-95.
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`R. K. Gaede, M. R. Mercer, K. M. Butler, and D. E. Ross, "CATAPULT: Concurrent Automatic Testing Allowing
`Parallelization and Using Limited Topology," Proc. 25th ACM/IEEE Design Automation Conference, Anaheim, CA,
`June 13-15, 1988, pp. 597-600.
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`E. S. Park, M. R. Mercer, and T. W. Williams, "Statistical Delay Fault Coverage and Defect Level for Delay Faults,"
`Proc. 1988 International Test Conference, Washington, DC, September 12-14, 1988, pp. 492-499. (Honorable
`Mention for Best Paper of the 1988 ITC)
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`S. P. Smith, B. Underwood, and M. R. Mercer, "D3FS: Demand Driven Time First Deductive Fault Simulation,"
`Proc. 1988 International Test Conference, Washington, DC, September 12-14, 1988, pp. 582-592.
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`C. T. Glover and M.R. Mercer, "A Deterministic Approach to Adjacency Testing for Delay Faults," Proc. 26th
`ACM/IEEE Design Automation Conference, Las Vegas, NV, June 25-29, 1989, pp. 351-356.
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`E. S. Park and M.R. Mercer, "An Efficient Delay Test Generation System for Combinational Logic Circuits," Proc.
`27th ACM/IEEE Design Automation Conference, Orlando, FL, June 24-28, 1990, pp. 522-528.
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`K. M. Butler and M.R. Mercer, "The Influences of Fault Type and Topology on Fault Model Performance and the
`Implications to Test and Testable Design," Proc. 27th ACM/IEEE Design Automation Conference, Orlando, FL,
`June 24-28, 1990, pp. 673-678. {NSF, SRC}
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`D. E. Ross, K. M. Butler, R. Kapur, and M. R. Mercer, "Fast Functional Evaluation of Candidate OBDD Variable
`Orderings," Proc. of The European Conference on Design Automation, Amsterdam, The Netherlands, February 25-
`28, 1991, pp. 4-10. {NSF, ONR, SRC}
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`R. Kapur, K. M. Butler, D. E. Ross, and M. R. Mercer, "On Bridging Fault Controllability and Observability and
`Their Correlations to Detectability,” Proc. of The European Test Conference, Munich, Germany, April 10-12, 1991,
`pp. 333-339. {NSF, ONR, SRC}
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`K. M. Butler and M. R. Mercer, "Quantifying Non-Target Defect Detection by Target Fault Test Sets," Proc. of The
`European Test Conference, Munich, Germany, April 10-12, 1991, pp. 91-100. {NSF, SRC}
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`T. W. Williams, B. Underwood, and M. R. Mercer, "The Interdependence Between Delay-Optimization of
`Synthesized Networks and Testing," Proc. 28th ACM/IEEE Design Automation Conference, San Francisco,
`California, June 17-19, 1991, pp. 87-92. (Best Paper Award at 1991 DAC) {none}
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`K. M. Butler, D. E. Ross, R. Kapur, and M. R. Mercer, "Heuristics to Compute Variable Orderings for Efficient
`Manipulation of Ordered Binary Decision Diagrams," Proc. 28th ACM/IEEE Design Automation Conference, San
`Francisco, California, June 17-19, 1991, pp. 417-420. {NSF, ONR, SRC}
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`E. S. Park, B. Underwood, T. W. Williams, and M. R. Mercer, "Delay Testing Quality in Timing-Optimized
`Designs," Proc. 1991 International Test Conference, Nashville, TN, October 28 - November 1, 1991, pp. 897-905.
`{NSF, ONR, TATP}
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`K. M. Butler, R. Kapur, D. E. Ross, and M. R. Mercer, "The Roles of Controllability and Observability in Design
`for Test," Proc. 1992 IEEE VLSI Test Symposium, Atlantic City, New Jersey, April 6-9, 1992. {NSF, ONR, SRC}
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`M. R. Mercer, R. Kapur, and D. E. Ross, "Functional Approaches to Generating Orderings for Efficient Symbolic
`Representations," Proc. 29th ACM/IEEE Design Automation Conference, Anaheim, California, June 9-11, 1992, pp.
`624-627. {NSF, ONR, SRC}
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`Mercer, p. 7
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`R. Kapur, J. Park, and M. R. Mercer, "All Tests for a Fault are Not Equally Valuable for Defect Detection," Proc.
`1992 International Test Conference, Baltimore, MD, September 20-24, 1992, pp. 762-769. {NSF, ONR, SRC}
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`M. A. Heap, W. A. Rogers, and M. R. Mercer, "A Synthesis Algorithm for Two-Level XOR Based Circuits," Proc.
`IEEE International Conference on Computer Design, Cambridge, MA, October 11-14, 1992, pp. 459-462.
`{TARP}
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`R. B. Brashear, D. R. Holberg, M. R. Mercer and L. Pillage, "ETA: Electrical-Level Timing Analysis," IEEE
`International Conference on Computer-Aided Design, Santa Clara, CA, November 8-12, 1992, pp. 258-262. {IBM,
`MOTO, ONR, SRC, TATP}
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`J. Park and M. R. Mercer, "An Efficient Symbolic Design Verification System," Proc. IEEE International
`Conference on Computer Design, Cambridge, MA, October 3-6, 1993, pp. 294-298. {SRC}
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`Eun Sei Park, and M. R. Mercer, "Switch-Level ATPG Using Constraint-Guided Line Justification," Proc. 1993
`International Test Conference, Baltimore, MD, October 17-21, 1993, pp. 616-625. {none}
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`R. B. Brashear, N. Menezes, C. Oh, L. Pillage, and M. R. Mercer, "Predicting Circuit Performance Using Circuit-
`Level Statistical Timing Analysis," Proc. of The European Design and Test Conference, Paris, France, February 28-
`March 3, 1994. {ARPA, ONR, SRC}
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`J. Park, M. Naivar, R. Kapur, M. R. Mercer, and T. W. Williams, "Limitations in Predicting Defect Level Based on
`Stuck-at-Fault Coverage," Proc. 1994 IEEE VLSI Test Symposium, Cherry Hill, NJ, April 25-28, 1994, pp. 186-191.
`{ONR, SRC}
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`L-C Wang, M. R. Mercer, and T. W. Williams, "Enhanced Testing Performance via Unbiased Test Sets," Proc. of
`The European Design and Test Conference, Paris, France, March 6-9, 1995, pp. 294-302. {SRC}
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`J. Park, C. Oh, and M. R. Mercer, "Improved Sequential ATPG Using Functional Observation Information and New
`Justification Methods," Proc. of The European Design and Test Conference, Paris, France, March 6-9, 1995, pp.
`262-266. {ARPA, SRC}
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`L-C. Wang, Sophia Kao, M. R. Mercer, and T. W. Williams, "On the Decline of Testing Efficiency as Fault
`Coverage Approaches 100%," Proc. 1995 IEEE VLSI Test Symposium, Princeton, NJ, April 30- May 3, 1995, pp. 74
`- 83. {ONR, SRC}
`
`C. Oh and M. R. Mercer, "Efficient Timing Analysis Using Constraint-Guided Critical Path Search," Proc. Eighth
`Annual IEEE ASIC Conference and Exhibit, Austin, TX, Sept. 18 - 20, 1995, pp. 289 - 293. {ARPA, ONR}
`
`L-C. Wang, M. R. Mercer, and T. W. Williams, "On Efficiently and Reliably Achieving Low Defective Part
`Levels," Proc. 1995 International Test Conference, Washington, DC, October 23 - 25, 1995, pp. 616-625. {SRC,
`ONR}
`
`T. W. Williams, R. Kapur, M. R. Mercer, R. H. Dennard, and W. Maly, "IDDQ Testing for High Performance
`CMOS -- The Next Ten Years," Proc. of The European Design and Test Conference, Paris, France, March 11-13,
`1996, pp. 578-583. {none}
`
`L-C. Wang and M. R. Mercer, "A Better ATPG Algorithm and Its Design Principles," Proc. 1996 International
`Conference on Computer Design, Austin, TX, October 7 - 9, 1996, pp. 248-253. {SRC}
`
`J. Park and M. R. Mercer, "Using Functional Information and Strategy Switching in Sequential ATPG," Proc. 1996
`International Conference on Computer Design, Austin, TX, October 7 - 9, 1996, pp. 254-260. {SRC}
`
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`Mercer, p. 8
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`L-C. Wang, M. R. Mercer, and T. W. Williams, "Using Target Faults to Detect Non-Target Defects," Proc. 1996
`International Test Conference, Washington, DC, October 22 - 24, 1996, pp. 629-638. {SRC}
`
`T. W. Williams, R. H. Dennard, R. Kapur, M. R. Mercer, and W. Maly, "IDDQ Test: Sensitivity Analysis of
`Scaling," Proc. 1996 International Test Conference, Washington, DC, October 22 - 24, 1996, pp. 786-792. {none}
`
`M. R. Grimaila, S. Lee, J. Dworak, K. M. Butler, B. Stewart, H. Balachandran, B. Houchins, V. Mathur, J. Park, L-
`C. Wang, and M. R. Mercer, "REDO -- Random Excitation and Deterministic Observation -- First Commercial
`Experiment," Proc. 1999 IEEE VLSI Test Symposium, Dana Point, Calif., April 25 - 29, 1999, pp. 268-274.
`(Best Paper Award at 1999 VLSI Test Symposium) {TATP}
`
`J. Dworak, M. R. Grimaila, S. Lee, L-C. Wang, and M. R. Mercer, "Modeling the Probability of Defect Excitation
`for a Commercial IC with Implications for Stuck-at Fault-Based ATPG Strategies," Proc. 1999 International Test
`Conference, Atlantic City, NJ, September 28 - 30, 1999, pp. 1031-1037. {TATP}
`
`R. Mehler and M. R. Mercer, "Multi-level Logic Minimization Through Fault Dictionary Analysis," Proceedings of
`the 1999 International Conference on Computer Design, Austin, TX, October 10 - 13, 1999, pp. 315-318.
`
`J. Dworak, M. R. Grimaila, S. Lee, L-C. Wang, and M. R. Mercer, "Enhanced DO-RE-ME Based Defect Level
`Prediction Using Defect Site Aggregation – MPG-D," Proceedings of the 2000 International Test Conference,
`Atlantic City, NJ, October 3 - 5, 2000, pp. 930-939. {TATP}
`
`J. Dworak, M. R. Grimaila, B. Cobb, T-C. Wang, Li-C. Wang, and M. R. Mercer “On the Superiority of DO-RE-
`ME / MPG-D Over Stuck-at-Based Defective Part Level Prediction,” Proceedings of the Ninth Asian Test
`Symposium, Taipei, Taiwan, December 4-6, 2000, pp. 151-157. {NSF, TATP}
`
`T. W. Williams, M. R. Mercer, J. P. Mucha, and R. Kapur, “Code Coverage, What Does It Mean in Terms of
`Quality?” Proceedings of the 2001 Annual Reliability and Maintainability Symposium, Philadelphia, PA, January
`22-25, 2001, pp. 420-424. {none}
`
`S. Lee, B. Cobb, J. Dworak, M. R. Grimaila, and M. R. Mercer, “A New ATPG Algorithm to Limit Test Set Size
`and Achieve Multiple Detections of all Faults, Proceedings of Design Automation and Test In Europe – DATE 2002,
`Paris, France, March 4 – 8, 2002, pp. 94 - 99. {SRC, NSF}
`
`J-J Liou, Li-C Wang, K-T Cheng, J. Dworak, M. R. Mercer, R. Kapur, and T. W. Williams, “Enhancing Test
`Efficiency for Delay Fault Testing Using Multiple-Clocked Schemes,” Proceedings of The 39th Design Automation
`Conference, New Orleans, Louisiana, June 10 - 14, 2002, pp. 371 - 374.
`
`J.-J. Liou, L.-C. Wang, K.-T. Cheng, J. Dworak, M. R. Mercer, R. Kapur, and T. W. Williams, “Analysis of Delay
`Test Effectiveness with a Multiple-Clock Scheme,” Proc. 2002 International Test Conference, Baltimore, MD,
`October 8 - 10, 2002, pp. 407 - 416.
`
`J. Dworak, J. Wingfield, B. Cobb, S. Lee, Li-C Wang, and M. R. Mercer, "Fortuitous Detection and its Impact on
`Test Set Sizes Using Stuck-at and Transition Faults," Proceedings of the 2002 International Symposium on Defect
`and Fault Tolerance in VLSI Systems (DFT 2002), Vancouver, Canada, November 6-8, 2002, pp. 177 - 185.
`
`Li-C. Wang, A. Krstic, L. Lee, K-T. Cheng, M. R. Mercer, T. W. Williams, and M. S. Abadir, "Using Logic Models
`to Predict the Detection Behavior of Statistical Timing Defects," Proceedings of the 2003 International Test
`Conference, Charlotte, NC, September 30 - October 2, 2003, pp.1041 - 1050.
`
`Y. Tian, M. R. Grimaila, W. Shi, and M. R. Mercer, "Minimizing Defect Levels Using a Linear Programming Based
`Optimal Test Selection Method," Proceedings of the 2003 Asian Test Symposium, Xi’an, P. R. China, November 17
`- 19, 2003.
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`Mercer, p. 9
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`J. Wingfield, J. Dworak, and M. R. Mercer, "Function-Based Dynamic Compaction and its Impact on Test Set
`Sizes," Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems,
`Boston, MA, November 3 - 5, 2003, pp. 167 - 174.
`
`J. Dworak, J. Wingfield, B. Cobb, and M. R. Mercer, “Balanced Excitation and its Effect on the Fortuitous
`Detection of Dynamic Defects," Proceedings of Design Automation and Test In Europe – DATE 2004, Paris, France,
`February 16 -20, 2004, pp. 1,066 – 1,071.
`
`J. Dworak, D. Dorsey, A. Wang, and M. R. Mercer, “Excitation, Observation, and ELF-MD: Optimization Criteria
`for High Quality Test Sets," Proceedings of the 2004 IEEE VLSI Test Symposium (VTS'04), Napa Valley, CA, USA,
`April 25th - April 29th, 2004, pp. 9 - 15. (IEEE Test Technology Technical Council Naveena Nagi Award for
`2004)
`
`J. Dworak, J. Wingfield, and M. R. Mercer, "A Preliminary Investigation of Observation Diversity for Enhancing
`Fortuitous Detection of Defects," Proceedings of the 19th IEEE International Symposium on Defect and Fault
`Tolerance in VLSI Systems, Cannes, France, October 11 - 13, 2004, pp. 460 - 468.
`
`Chapters and Books:
`
`K. M. Butler and M. R. Mercer, Assessing Fault Model and Test Quality, Kluwer Academic Publishers, 1991, ISBN
`0 - 7923 - 9222 - 1.
`
`V. D. Agrawal and M. R. Mercer, "Testability Measures -- What Do They Tell Us?," in VLSI Testing and Validation
`Techniques, IEEE Tutorial, H. Reghbati, editor, 1985, pp. 401-406.
`
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`Technical Reports:
`
`M. R. Mercer and V. D. Agrawal, "Use of Clock Signal Redundancy for Testability," Bell Laboratories Technical
`Memorandum, July 1981.
`
`C. M. Roman, V. D. Agrawal and M. R. Mercer, "An LSI Chip Designed for Testability," Proceedings of the Bell
`System Conference on Electronic Testing, Princeton, NJ, September 1981.
`
`M. R. Mercer and V. D. Agrawal, "Applications for Testability Measures in VLSI Design," Proceedings of the Bell
`System Conference on Electronic Testing, Princeton, NJ, October 1982, pp. 52-58.
`
`M. R. Mercer, "Computer Aided Design of Digital Systems," Discovery -- Research and Scholarship at The
`University of Texas at Austin, Vol. 9, No. 3, 1985, pp 17-21.
`
`M. R. Mercer, "Testing and Design Verification of Electronic Components -- a Perspective of the Last 40 Years,"
`IEEE Computer, (Invited Publication for the 40th Anniversary Issue), September, 1991.
`
`Other publications:
`
`J. Dworak, D. Dorsey, A. Wang, and M. R. Mercer with IBM Technical Contact M. W. Mehalic, “Estimating Mean
`Time to Failure in Digital Systems Using Manufacturing Defective Part Level,” 4th Annual IBM Austin Center for
`Advanced Studies Conference, Austin, TX, February 21, 2003.
`
`PROFESSIONAL SOCIETY PRESENTATIONS:
`
`"Testability Strategies for Custom Polycell Designs," Computer Elements Workshop on VLSI Debug and Diagnosis,
`IEEE Computer Society, New York, NY, May 1982.
`
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`Mercer, p. 10
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`"Interpretations of Testability Measures," IEEE Design Automation Workshop, Michigan State University, East
`Lansing, MI, October 1982.
`
`"Testability Measures -- What Do They Tell Us?," Automatic Testing and Measurement Exhibition, Wiesbaden,
`West Germany, March 1983 (by invitation as part of the "Best of Cherry Hill" Session).
`
`"Testing Issues at the University of Texas," International Test Conference 1983, Philadelphia, PA, October 1983.
`
`"Refinement of Statistical Evaluation of Testability Algorithms," (with B. Underwood), Seventh Annual IEEE
`Workshop on Design for Testability, Vail, CO, April 1984.
`
`"SUBTLE -- A New Methodology for Structured Testability," Seventh Annual IEEE Workshop on Design for
`Testability, Vail, CO, April 1984.
`
`"Why Calculating Observability is More Difficult than Controllability," Eighth Annual IEEE Workshop on Design
`for Testability, Vail, CO, April 1985.
`
`"Automatic Test Pattern Generation for PLA's," (with J. Salick and B. Underwood), Fifth Annual IEEE West Co