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`
`USIJ0646014631
`
`(12)
`
`United States Patent
`US 6,460,146 B1
`(10) Patent N0.:
`
`(45) Date of Patent: *0ct. 1, 2002
`Mobcrg et al.
`
`(54)
`
`(75)
`
`( 73)
`
`(*l
`
`(31)
`
`(22
`
`(51)
`(52)
`(58)
`
`(56)
`
`SYSTEM AND METHOD FOR
`ESTABLISHING PROCESSOR
`REDUNDANCY
`
`5,903,448 A * 10:19.99 Flood ct a].
`6,023,330? A *
`ZQUUU Wookcy
`6,085,244 A *
`ItZUt'I} Wookey
`6,118,?68 A
`QIZUUU Bhatia et al.
`
`364.318?
`38t1t21
`7’09324
`.. 3?i.1.-"254
`
`
`
`Inventors: Kenneth Matte-1g, Boulder Creek, CA
`E32? William May, Sunnyvale, CA
`
`Assignee: CiSCIJ Technology. Inc., San Jose, CA
`US
`(
`)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 15403) by 0 days.
`
`Notice:
`
`114p
`
`6,263,432 Bl
`* morn Jewett et at.
`OTHER PUBLICATIONS
`Jack Jenney, "Dual RSP—Iligh System Availability SW
`Functional Spec", Oct. 6, 1905, Cisoo Systems, Inc.
`“ cited by examiner
`_
`.
`_
`Primal?" BrarrrrnerfiQCott Bad‘erman
`Assistant L'xrrtrdner—Rita A Ztemcr
`(74) Attorney, Agent, or Firm—Van Pelt & Yi [LP
`
`Appl. No.: 09t205,577
`
`(57)
`
`ABSTRAC’ *
`
`Dec. 4' 1998
`
`Filed:
`H02H 3,105
`Int. CL?
`714t10; 712,20; 709t222
`U.S. Cl.
`,.
`.
`led of Search 7{)9t’}387:’i41.311014701122726
`"‘ ’
`"If
`’
`’
`’ '
`References Cited
`
`US. PA'I‘EN'I' DOCUMENTS
`a
`._
`a :2
`
`5336398 A ,
`8;]992 McLaughlin at al.
`364tl84
`3451653 A ==
`trutonz Major ct al.
`3mm
`5,455,932 A it
`[Wit/’95 Major et a" ................ 3952'489
`5,4?3,599 A
`12,!1995 Li el al.
`.. 37mm
`..........
`. 370x402
`5,572,528 A * 1tr1996 Shuert
`
`5.590324 A
`W997 VerdgikOVSkY
`175:5?
`3935i [8321
`5’04“»??? A t
`83'1”“ Izuta‘et 3"
`34315-1be A
`{”1998 iIashunoto
`39:2900‘38
`5,8?i),35? A
`21999 Beliovm cl al.
`..
`.. 393t200.54
`
`sneer} roam el al.
`.
`370nm
`5,014,953 A
`
`.. 714f13
`..
`5,919,266 A *
`791999 Sud et al.
`
`
`709,242
`5,928,332 A *
`7l1999 Pierce
`
`The present invention relates to providing processor redunfi
`dancy in a System such as a-route-r. According to an embodi-
`merit Of the present rnpention, 1n :1 system ha“? 30.0:
`H1011:
`l'OCCSSOl'S,
`ll'llila lZallOH SB uence IS starle .
`unn
`the iniiialization sequence, a reduqndancy subsystem is in?
`tialized. The redundancy subsystem identifies the projects or
`assignments that are to be on loaded from the primary
`processor
`to the secondary processor. According to an
`embodiment of the present
`invention,
`the initialization
`sequence is then suspended and a discovery process is
`99%
`whether the processor runnmg the inlttallaation sequence 15
`8 Primary 0f 3 5600942}? prose-Wir- If n 15 a SCPOUdary
`DHJCUSSLH‘,
`ihtifl
`Ii'll’}
`ll‘llilflll'fiililt‘ll'} sequence remains SUS-
`pended and the secondary processor monitors the health of
`the primary processor until a failure of the primary processor
`occurs.
`If a primary processor failure oceurs,
`then the
`initialization process is resumed for the secondary processor.
`hence establishing the secondary processor as the new
`.
`pn'm'y pmmswr‘
`
`19 Claims, 8 Drawing Sheets
`
`300
`_
`
`}”
`sun initialization sequence
`‘302
`‘
`I
`_
`Subsystem 'ltitialiaatlon including initializing /
`secondary project :ubayalnm
`...i
`
`
`
`
`
`
` E
`
`
`"
`.
`.
`.
`_
`Suspend inilinlinuon amt-«I an and Mrforlll
`rosemary process
`
`3‘3"
`,4
`
`Member
`_ 310
`—_I
`health at
`1}
`_
`
`mid-Ila: dl'lW subsystems Primary
`
`313
`
`(cid:20)
`
`ARISTA 1005
`(cid:36)(cid:53)(cid:44)(cid:54)(cid:55)(cid:36)(cid:3)(cid:20)(cid:19)(cid:19)(cid:24)
`
`

`

`US. Patent
`
`Oct. 1, 2002
`
`Sheet 1 0f 8
`
`US 6,460,146 B1
`
`UJ
`(D
`
`FIG.1
`
`(cid:21)
`
`<a
`
`.
`an
`m
`
`
`
`

`

`US. Patent
`
`Oct. 1, 2002
`
`Sheet 2 0f 8
`
`US 6,460,146 B1
`
`100
`
`HW discovery and boot IOS
`
`ROM reads HW register (NVRAM)
`
`102
`
`104
`
`106
`
`
` processor a
`secondary
`
`N
`
`Y
`
`Boot secondary
`image
`
`108
`
`112
`
`Boot primary image
`
`processor
`
`“0
`
`Initiate secondary
`
`Initiate primary processor
`
`1 14
`
`
`
`
`Master
`processor
`failure ?
`
`
`
`“8
`
`Reboot [OS and
`establish this
`processor as
`
`primary
`
`
`
`FIG. 2
`
`(cid:22)
`
`

`

`US. Patent
`
`Oct. 1, 2002
`
`Sheet 3 0f 8
`
`US 6,460,146 B1
`
`INTERFACE .................................................................
`
`SERIAL
`
`COMM.
`
`INTERFACE
`
`MULTIPORT
`
`COMMUNICATIONS
`
`
`MULTIPORT
`ETHERNET
`
`
`
`
`
`FDDI
`INTERFACE
`
`
`164
`
`PRIMARY
`
`170
`
`CONTROLLER
`
`166
`
`168
`
`1 2
`
`SECONDARY
`CPU
`
`REGISTERS .
`
`182
`
`134
`
`FIG. 3
`
`(cid:23)
`
`

`

`US. Patent
`
`Oct. 1, 2002
`
`Sheet 4 0f 8
`
`US 6,460,146 B1
`
`
`
`200
`
`
`
`202
`
`
`
`204
`
`
`
`206
`
`
`
`
`
`
`
`FIG. 4
`
`(cid:24)
`
`

`

`US. Patent
`
`Oct. 1, 2002
`
`Sheets of 8
`
`US 6,460,146 B1
`
`Start initialization sequence
`
`
`
`Subsystem initialization including initializing
`secondary project subsystem
`
`
`
`Suspend initialization sequence and perform
`discovery process
`
`300
`
`302
`
`304
`
`306
`
`Y
`
`Remain
`suspended
`
`
`
`processor
`secondary
`
`
`N
`
`310
`
`.
`.
`.
`.
`Initialize drwer subsystems
`
`Monitor
`
`health of
`Primary
`
`308
`
`316
`
`Finish initialization sequence
`
`312
`
`314
`
`FIG. 5
`
`(cid:25)
`
`

`

`US. Patent
`
`Oct. 1, 2002
`
`Sheet 6 0f 8
`
`US 6,460,146 B1
`
`402
`
`406
`
`408
`
`412
`
`400
`
`[S
`
`
`
`
`
`
`- nother processor
`
`Y
`
`404
`
`
`
`
`processor a
`primary
`
`N
`
`~
`
`Y
`
`8:32:38
`procedure
`
`_
`Start primary
`background
`process
`
`Start secondary background process
`
`410
`
`
`
`Y
`
`.
`
`Receive
`Resume
`command to switch
`initialization
`
`process
`
`with primary
`
`
`Failure
`of primary
`
`
`
`
`
`41B
`
`Remain
`
`suspended
`
`FIG. 6
`
`(cid:26)
`
`

`

`US. Patent
`
`Oct. 1, 2002
`
`Sheet 7 0f 8
`
`US 6,460,146 B1
`
`Establish communication with secondary
`
`Initiate monitoring of health of secondary
`
`500
`
`502
`
`Resume initialization
`
`314
`
`
`
`Is
`n
`seco dary
`
`heaflhy
`?
`
`
`N
`
`Change state to stand alone
`
`504
`
`510
`
`FIG. 7
`
`(cid:27)
`
`

`

`US. Patent
`
`Oct. 1, 2002
`
`Sheet 8 0f 8
`
`US 6,460,146 B1
`
`Establish communication to primary processor
`
`Initiate health monitoring of primary
`
`600
`
`602
`
`604
`
`
`
`
`
`
`
`
`
`
`there any
`processing which
`primary wants to
`offload
`
`?
`
`Y
`
`Primary offloads processing to secondary
`
`
`
`Suspend initialization process
`
`Continue monitoring health
`
`608
`
`
`
`
`610
`
`FIG. 8
`
`(cid:28)
`
`

`

`US 6,460,146 B]
`
`l
`SYSTEM AND METHOD FOR
`ESTABLISHING PROCESSOR
`REDUNDANCY
`
`FIELD OF THE INVENTION
`
`The present invention relates to computer networks. In
`particular, the present invention relates to establishing pro-
`cessor redundancy.
`BACKGROUND OF THE INVENTION
`
`A network is a communication system that allows users to
`access resources on other computers and exchange messages
`with other users. A network is typically a data communica-
`tion system that links two or more computers and peripheral
`devices.
`It allows users to share resources on their own
`systems with other network users and to access information
`on centrally located systems or systems that are located at
`remote offices. It may provide connections to the Internet or
`the networks of other organizations. The network typically
`includes a cable that attaches to network interface cards
`(NIC) in each of the devices within the network. Users may
`interact with network-enabled software applications to make
`a network request (such as to get a file or print on a network
`printer). The application may also communicate with the
`network software and network software then may interact
`with the network hardware to transmit infom‘tation to other
`devices attached to the network.
`
`An example of a network is a local area network (LAN).
`A LAN is a network that is located in a relatively small area,
`such as a department or building. A LAN typically includes
`a shared medium to which workstations attach and commu—
`nicate with one another by using broadcast methods. With
`broadcasting, any device on the LAN can transmit a message
`that all other devices on the LAN can listen to. The device
`to which the message is addressed actually receives the
`message. Data is typically packaged into frames for trans~
`mission on the LAN.
`
`It)
`
`15
`
`“
`
`3o
`
`35
`
`4!)
`
`FIG. 1 is a block diagram illustrating a network connec-
`tion between a user 10 and a particular web page 20. This
`FIG. is an example which may be consistent with any type
`of network, including a LAN, :1 wide are network (WAN), or
`a combination of networks, such as the lnternet.
`When a user 10 connects to a particular destination, such
`as a requester] web page 20, the connection from the user It]
`to the web page 20 is typically routed through several routers
`12A—12D. Routers are internetworking devices. They are
`typically used to connect similar and heterogeneous network
`segments into internetworks. For example, two LANs may
`be connected across a dial-up.
`integrated services digital
`network (ISIJN), or a leased line via routers. Routers may
`also be found throughout
`the Internet. End users may
`connect
`to a
`local
`lntemet service provider (IS?) (not
`shown), which are typically connected via routers to
`regional ISPs, which are in turn typically connected via _
`routers to national 1895.
`
`45
`
`50
`
`If a router, such as router 12C, fails and is no longer able
`to route the desired connection, then the desired connection
`between the user 10 the desired web page 20 may be
`significantly delayed or unable to connect at all. To avoid
`this problem, a solution has been implemented by router
`manufacturers, such as Ciseo Systems,
`that
`include two
`processors, a primary processor and a secondary processor,
`such that the secondary processor may take over as the main
`processor if the primary processor has either a hardware or
`software failure. Accordingly, such a solution provides
`redundancy to avoid failure of the router.
`
`60
`
`65
`
`10
`(cid:20)(cid:19)
`
`2
`If the secondary processor is required to switch iLself over
`to the primary processor,
`then the secondary processor
`typically reboots, establishes itself as the primary processor,
`and re-initialines the entire router to become the primary
`processor. The re—booting and re—initializing process can
`take a substantial amount of time, such as minutes, since
`software is typically reloaded from either the network or
`flash memory and the new primary processor needs to run
`through the router configuration. The router configuration
`typically controls how the router moves data traffic. The
`configuration typically controls the path of network packets
`on their way to their final destination. The router configu-
`ration can be highly complex. The more complex the router
`configuration, the longer it typically takes to configure the
`router. Re-booting the router may take approximately 30
`seconds to 5 minutes.
`
`Although such redundancy routers may contain two
`processors, the secondary processor is typically unavailable
`for any work which is normally assigned to the primary
`processor. The secondary processor typically runs an image
`that is separate and different from the image which is run by
`the primary processor. Accordingly, the secondary processor
`is typically unavailable for offloading any work from the
`primary processor.
`It would be desirable for a router to provide redundancy
`without a substantial amount of down time for re-booting. It
`would also be desirable for such a router to offer an option
`of the secondary processor being able to off load work from
`the primary processor, thus making use of both processors
`simultaneously. The present invention addresses such needs.
`SUMMARY OF THE INVENTION
`
`invention relates to providing processor
`The present
`redundancy in a system such as a router. According to an
`embodiment ofthe present invention, in a system having two
`or more processors, initialization sequence is started. During
`the initialization sequence, a redundancy subsystem is ini~
`tialized. The redundancy subsystem identities the projects or
`assignments that are to be otI loaded from the primary
`processor
`to the secondary processor. According to an
`embodiment of the present
`invention,
`the initialization
`sequence is then suspended and a discovery process is
`performed. During the discovery process, it is determined
`whether the processor running the initialization sequence is
`a primary or a secondary processor. If it
`is a secondary
`processor,
`then the initialization sequence remains sus~
`pended and the secondary processor monitors the health of
`the primary processor until a failure of the primary processor
`occurs.
`If a primary processor failure occurs,
`then the
`initialization process is resumed for the secondary processor,
`hence establishing the secondary processor as the new
`primary processor.
`According to an embodiment of the present invention, if
`the processor running the initialization sequence is the
`primary processor, then the initialization process is resumed.
`Also according to an embodiment of the present invention,
`the suspension of the initialization sequence and perfor-
`mance of the discovery process preferably occurs prior to
`initialization of the driver subsystems. The remaining ini-
`tialization sequence is then finished, and the system is run.
`According to an embodiment of the present
`invention,
`each processor, both secondary and primary have the same
`image such that
`the same initialization sequence and sus—
`pension with the discovery process is performed in both the
`primary and secondary processors.
`A method according to an embodiment of the present
`invention for establishing processor redundancy is pre-
`
`

`

`US 6,460,146 B1
`
`3
`senled. The method comprises providing a processor and
`suspending an initialization sequence of the processor. The
`method also determines whether the processor is a second-
`ary processor; and resumes the initialization sequence if the
`processor is not a secondary processor.
`A system according to an embodiment of the present
`invention for establishing processor redundancy is also
`presented. The system comprises a processor configured to
`suspend an initialization sequence of the processor. The
`processor is also configured to determine whether it is a
`secondary processor, and resumes the initialization sequence
`if the processor is not a secondary processor. The system
`also includes a memory coupled to the processor, and the
`memory is configured to provide instructions to the proces-
`sor.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a block diagram of an example of a network
`connection between a user and a web page.
`FIG. 2 is a flow diagram of a conventional method for
`providing redundant processors in a router.
`FIG. 3 is a block diagram of an example of a router
`suitable for implementing an embodiment of the present
`invention.
`
`FIG. 4 is a flow diagram of a method according to an
`embodiment ot‘the present invention for providing processor
`redundancy in a system such as a router.
`FIG. 5 is a flow diagram of a method according to an
`embodiment of the present invention for initializing a pro-
`cessor in a redundant system.
`1'10. 6 is a [low diagram of a method according to an
`embodiment of the present
`invention for performing a
`discovery process.
`l-"tG. 7 is a flow diagram of a method according to an
`embodiment of the present invention for running a primary
`proceSsor background.
`FIG. 8 is a flow diagram of a method according to an
`embodiment of the present invention for running a second-
`ary processor background.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`
`The following description is presented to enable one of
`ordinary skill in the art to make and to use the invention and
`is provided in the context of a patent application and its
`requirements. Various modifications to the preferred
`embodiments will be readily apparent to those skilled in the
`art and the generic principles herein may be applied to other
`embodiments. Thus, the present invention is not intended to
`be limited to the embodiment shown but is to be accorded
`the widest SCUPC consistent with the principles and features
`described herein.
`
`FIG. 2 is a [low diagram of a conventional method [or
`establishing processor redundancy in a router. When power
`is turned on (step 100}, hardware discovery is performed as
`well as booting up of an operating system (such as an
`Internet operating system (IOSD for the router (step 102).
`Memory, such as read—only—memory (ROM) then reads
`hardware registers, such as registers in non-volatile random
`access memory (NVRAM) (step 104).
`the
`It
`is then determined whether this processor (i.e.
`processor that was powered on and is running this software)
`is a secondary processor (step 106). If this processor is not
`a secondary processor, then a primary image is booted up for
`
`10
`
`15
`
`an
`
`40
`
`50
`
`55
`
`60
`
`65
`
`4
`this processor (primary processor) (step 110). An initializa-
`tion sequence is then performed for the primary processor
`(step 114).
`If this processor is determined to be a secondary processor
`(step 106),
`then a secondary image is booted up for the
`secondary processor (step 108). An initialization sequence is
`then performed for the secondary processor (step 112). It is
`then determined whether the primary processor has had a
`failure (step 116). The primary processor’s health is moni-
`tored until it is determined that the primary processor has
`had a failure. Once the primary processor fails,
`then the
`Internet operating system (108) of the router is re-booted
`and this processor (formally the secondary processor) is then
`established as the primary processor (step 1.18). ‘I'hereafter,
`the ROM reads the hardware registers (step 104),
`it
`is
`determined that this processor is now a primary processor
`(step 106), and a primary image is then booted up (step 110).
`As previously mentioned, a potential drawback with this
`conventional method is that if the primary fails and the
`secondary processor takes over the function of the primary
`processor.
`then the entire router system is
`typically
`re-booted and a primary image, different from the secondary
`image,
`is booted and a primary processor
`initialization
`sequence is performed. This process of the secondary pro-
`cessor taking over the functions of the primary processor
`may be substantially time consuming. Additionally, since the
`primary procesSUr and the secondary processor each boot a
`different image, the secondary processor typically performs
`no function other than monitoring the health of the primary
`processor and acting as a standby processor.
`it would be desirable to provide processor redundancy in
`a system such as a router that significantly reduces the time
`required for the secondary processor to take over the func-
`tions of the primary processor in case of a failure of the
`primary processor. It would also be desirable for the sec—
`ondary processor to have the ability to perform some func-
`tions that are conventionally the duties of the primary
`processor. The present invention addresses such needs.
`FIG. 3 is a block diagram of an example of a router
`suitable for implementing an embodiment of the present
`invention. The router 150 is shown to include a primary
`central processing unit (CPU) 166, low and medium speed
`interfaces 158, and high speed interfaces 162. The primary
`CPU 166, may be responsible for such router tasks as
`routing table computations and network management.
`It
`may include one or more microprocessor chips selected
`from complex instruction set computer (CISC) chips (such
`as the Motorola 68040 Microprocessor), reduced instruc-
`tions set computer (RISC) chips, or other available chips.
`Non-volatile RAM andi’or ROM may also form part of the
`primary CPU 166. However, there are many ditIerent ways
`in which memory can be coupled to the system. For
`example, a memory 182 may be coupled with the primary
`CPU 166 via a bus 168. The memory 182 may also be
`coupled with a secondary CPU 180 via the bus 168.
`The memory 182 may include registers 184 which may be
`used for communication between the primary CPU 166 and
`the secondary CPU 180. For example, the registers 184 may
`indicate whether a global lock has been acquired by either
`the primary CPU 166 or the secondary CPU 180; indicate
`states of the processors 166 and 180 such as primary,
`secondary, non—participant, or there are no processor cards
`present; and indicate whether either of the processors 166
`and 180 have had a failure.
`
`The interfaces 158 and 162 are typically provided as
`interface cards. Generally,
`they control
`the sending and
`
`11
`(cid:20)(cid:20)
`
`

`

`US 6,460,146 B1
`
`It)
`
`15
`
`5
`receipt of data packets over the network and sometimes
`support other peripherals used with the router 150.
`Examples of interfaces that maybe included in the low and
`medium interfaces 158 include a multiport communications
`interface 152, a serial communications interface 154. and a
`token ring interface 156. Examples of interfaces that may be
`included in the high speed interfaces 162 include a fiber
`distributed data interface (FDDI) 164 and a multiport Eth~
`emet interface 160. Each of these interfaces {lowr‘medium
`and high speed) may include (1) a plurality of ports appro-
`priate for communication with the appropriate media, and
`(2) an independent processor such as the 2901 bit slice
`processor (available from Advanced Micro Devices Corpo-
`ration of Santa Clara, Calif), and in some instances (3)
`volatile RAM. The independent processors control such
`communication intensive tasks as packet switching and
`filtering, and media control and management. By providing
`separate processors for the communication intensive tastes,
`this architecture permits the primary microprocessor 166 to
`efficiently perform routing computations, network
`diagnostics, security functions, etc.
`The low and medium speed interfaces are shown to be
`coupled to the master CPU 166 through a data, control, and
`address bus 168. High speed interfaces 162 are shown to be
`connected to the bus 168 through a fast data, control, and
`address bus 172 which is in turn connected to a bus “
`controller 170. The bus controller functions are provided by
`a processor such as a 2901 bit slice processor.
`Although the system shown in FIG. 3 is an example of a
`router suitable for implementing an embodiment of the
`present invention, it
`is by no means the only router archi-
`tecture on which the present invention can be implemented.
`For example, an architecture having a single processor that
`handles communications as well as routing computations,
`etc. would also be acceptable. Further, other types of inter—
`faces and media could also be used with the router.
`
`En
`
`35
`
`FIG. 4 is a flow diagram of a method according to an
`embodiment of the present invention for providing processor
`redundancy in a system such as a router. According to an
`embodiment of the present invention, the method shown in
`FIG. 4 is performed for each processor, both primary and
`secondary.
`When the power is turned on (step 200), hardware dis—
`covery is performed and the Internet operating system of the
`router is booted up (step 202). Memory, such as a read-only
`memory,
`then reads hardware registers, which may be
`located in memory such as non-volatile random access
`memory (NVRAM) (step 204). Initialization sequence ofthe
`processor is then performed (step 206), and the router
`system is then run (step 208).
`FIG. 5 is a flow diagram of a method according to an
`embodiment of the present
`invention for performing an
`initialization sequence such as the initialization sequence of
`step 206 shown in FIG. 4. Initialization sequence is started
`(step 300). As part of the initialization sequence, subsystems _
`are also initialized, including a redundancy subsystem (step
`302). There may be several items initialized between the
`start of the initialization sequence and the subsystem ini-
`tialization. For example, items included in the initialization
`sequence may include the system clock, platform hardware
`interrupt, CPU type and CPU family discovery, checksum
`for text segment, memory list manager, memory manager,
`platform exception handler, and console initialization. These
`initialization items and their sequence are well known to
`those of average skill in the art.
`Examples of events occurring during the subsystem ini-
`tialization include finding all subsystems, searching for
`
`4!)
`
`45
`
`50
`
`60
`
`65
`
`12
`(cid:20)(cid:21)
`
`6
`subsystems, enabling interrupts, starting the scheduler, and
`initiating several items such as a kernel subsystem, generic
`network support services, generic system services, system
`logger, platform console lines and auxiliary lines, platform
`interfaces, platform specific memory, platform hardware.
`and communication support. These subsystem initialization
`functions are also well known to those ofaverage skill in the
`art,
`
`According to an embodiment of the present invention, the
`subsystem initialization also includes initializing a redun-
`dancy subsystem. The redundancy subsystem may be a list
`of projects or functions that are to be assigned to and
`performed by the secondary processor. These functions and
`projects may include functions and projects typically per-
`formed by the primary processor. The software designer may
`determine which functions are to be performed by the
`secondary processor rather than the primary processor.
`These functions are listed in the redundancy subsystem.
`Preferably, the redundancy subsystem should be initialized
`prior to initialization of the driver subsystems since the
`initialization sequence for the secondary processor is sus—
`pended prior to the initialization of the driver subsystems
`according to an embodiment of the present
`invention.
`Accordingly, any function that is to be elf—loaded to the
`secondary processor should be assigned prior to the suspen-
`sion of the initialization sequence for the secondary proces-
`SOT.
`
`Initialization sequence is then suspended for both primary
`and secondary processors and a discovery process is per—
`formed (step 304). One of the primary purposes of the
`discovery process is to determine whether the processor
`running this initialization sequence is a primary processor or
`a secondary processor. Further details of the discovery
`process will later he discussed in conjunction with FIG. 6.
`It is then determined whether this processor is a secondary
`processor {step 306). If it
`is a secondary processor,
`the
`initialization sequence remains suspended (step 308). The
`secondary processor then monitors the health of the primary
`processor (step 316).
`If it is determined that this processor is not a secondary
`processor (step 306), then driver subsystems are initialized
`(step 310). Thereafter, the remainder of the initialization
`sequence is completed (step 312), and the router system is
`run (step 314). Examples of the remainder of the initializa-
`tion sequence includes initializing the protocol subsystems,
`library subsystems, management subsystems, print hardware
`configuration on the console, reading stored configuration,
`executing configuration, and ending the initialization pro-
`cess.
`
`FIG. 6 is a flow diagram of a method according to an
`embodiment of the present
`invention for performing a
`discovery process such as the discovery process of step 304
`ofFlG. 5. It is determined whether there is another processor
`other than the one executing this method (step 400). If there
`is no other processor, then the processor acts as a stand alone
`processor (step 402). Astand alone processor procedure may
`simply be a conventional router with a single processor. If,
`however, there is another processor, then it
`is determined
`whether this processor is a primary processor (step 404).
`One example of how this processor may be determined to be
`a primary processor is by reading one of the registers in the
`memory, such as register 184 of FIG. 3. If this processor is
`a primary processor, then a primary background process is
`initiated (step 406). Further details of the primary back-
`ground process will later be discussed in conjunction with
`FIG. 7.
`
`

`

`US 6,460,146 B1
`
`7
`If, however, this processor is not a primary processor (step
`404-), then a secondary background process is initiated (step
`406). Details of the secondary background process will later
`be discussed in conjunction with FIG. 8.
`It
`is then determined whether the secondary processor
`receives a command to switch with the primary processor
`(step 410). The command to switch with the primary pro-
`cessor may be initiated by a user or designed into the
`program under certain conditions by the designer. If the
`command to switch with the primary processor is received,
`then initialization process is resumed for the secondary
`processor (step 412). Thereafter, step 306 of FIG. 5 may be
`executed.
`
`If, however, a command to switch with the primaryr
`processor is not received, then it is determined whether the
`primary processor has failed (step 414). Examples of the
`failure of the primary processor include either a hardware
`failure or a software failure. If the primary processor has
`failed,
`then the initialization process is resumed for the
`Secondary processor {step 412), and step 306 of FIG. 5 is
`then executed.
`
`to
`
`15
`
`8
`secondary background process, such as that described in
`step 408 of F! G. 6. The secondary background process is run
`by the secondary processor. An example of the way the
`health of the other processor is monitored is through the use
`of registers in memory, such as registers 184 of FIG. 3. One
`of the registers may indicate whether the primary processor
`has had a failure, while another register indicates whether
`the secondary processor has had a failure.
`The secondary processor establishes communication with
`the primary processor (step 600). Health monitoring of the
`primary processor is then initiated (step 602).
`It
`is then
`determined whether there is any processing which the pri-
`mary processor is oh" loading to the secondary processor
`(step 604-). This determination may be made by reviewing
`the list in the redundancy subsystem of step 302 of FIG. 5.
`As previously mentioned, the list of functions in the redunfi
`dancy subsystem may be created by the software deveIOper
`and should be initialized prior to the suspension of the
`initialization sequence which preferably occurs prior to
`initializing the driver subsystems. If there is processing that
`the primary processor
`is of].
`loading to the secondary
`processor,
`then these functions listed in the redundancy
`subsystem are oh" loaded to the secondary processor (step
`606).
`The initialization sequence then remains suspended (step
`608), however, anything that was olI-loaded from the pri-
`mary processor to the secondary processor is run by the
`secondary processor.
`If there is no processing to be olI-
`loaded from the primary processor to the secondary
`processor,
`then the initialization sequence also remains
`suspended (step 608). Thereafter, the secondary processor
`continues to monitor the health of the primary processor
`(step 610), and step 410 of FIG. 6 is executed.
`A method and system for establishing processor redun-
`dancy in a system such as a router has been disclosed.
`Software written according to the present invention may be
`stored in some form of computer-readable medium, such as
`memory or CD~ROM, or transmitted over a network, and
`executed by a processor.
`invention has been described in
`Although the present
`accordance with the embodiment shown, one of ordinary
`skill
`in the art will readily recognize that there could be
`variations to the embodiment and these variations would be
`within the spirit and scope of
`the present
`invention.
`Accordingly, many modifications may be made by one of
`ordinary skill in the art without departing from the spirit and
`scope of the appended claims.
`What is claimed:
`1. A method for establishing router redundancy, compris-
`ing:
`providing a router processor;
`suspending an initialization sequence of the router pro—
`cessor;
`
`determining whether the router processor is a secondary
`pIOCCS‘KJI';
`resuming the initialization sequence if the router proces-
`sor is not a secondary processor; and
`continuing to suspend the initialization sequence of the
`router processor if the router processor is a secondary
`processor, whereby the router processor remains in a
`partially initialized state such that it would be ready to
`resume and complete the previously suspended initial-
`ization process in the event it were to become necessary
`for the router processor to become a primary processor.
`2. The method of claim 1, further comprising monitoring
`a health of the secondary processor if the router processor is
`not the secondary processor.
`
`If the primary processor has not failed, then it is deter-
`mined whether the primary processor eard has been removed
`(step 416). If the primary processor has been removed, then
`the initialization process of this processor is resumed (step
`412), and step 306 of FIG. 5 is then executed.
`If the primary processor card has not been removed (step
`416), then the initialization sequence remains suspended for
`the secondary processor (step 418). A command to switch
`with the primary processor.
`the failure of the primary
`processor, and the removal of the primary processor card are
`merely examples of events that may trigger the secondary
`processor taking over the functions of the primary processor.
`Other events may be used as a trigger for the secondary
`processor to take over the functions of the primary proces« ‘
`sor. Accordingly,