Per
`
`WORLD INTELLECTUAL PROPERTY ORGANIZATION
`International Bureau
`
`INTERNATIONAL APPLICATION PUBLISHED UNpER THE PATENT COOPERATION TREATY (PCT)
`wo 93/21574
`
`(51) International Patent Oassification 5 :
`
`(11) International Publication Number:
`
`G06F3/14
`
`Al
`
`(43) International Publication Date:
`
`28 October 1993 (28.10.93)
`
`I ...
`
`~
`
`p;!i
`
`.ll
`
`(21) International Application Number:
`
`PCT/GB93/00749
`
`(22) International Filing Date:
`
`8 Aprill993 (08.04.93)
`
`(74) Agent: ROBSON, Aidan, John; Reddie & Grose, 16 The(cid:173)
`obalds Road, London WClX 8PL (GB).
`
`(30) Priority data:
`9207972.2
`9221026.9
`
`10 Aprill992 (10.04.92)
`6 October 1992 (06.10.92)
`
`GB
`GB
`
`(71) Applicant (for all designated States except US): VIDEO(cid:173)
`LOGIC LIMITED [GB/GB]; Home Park Estate, Kings
`Langley, Hertfordshire WD4 8LZ (GB).
`
`(72) Inventor; and
`(75) Inventor/ Applicant (for US only) : YASSAIE, Hossein [GB/
`GB]; Videologic Limited, Home Park Estate, Kings
`Langley, Hertfordshire WD4 8LZ (GB).
`
`(81) Designated States: GB, JP, US, European patent (AT, BE,
`CH, DE, DK, ES, FR, GB, GR, IE, IT, LU, MC, NL,
`PT, SE).
`
`Published
`With international search report.
`
`(54) Title: MULTIMEDIA DISPLAY
`
`1----R
`1----G
`1----B
`
`MEM BUS
`
`MEMORY
`CONTROLLER
`
`14
`
`CPU
`
`10
`
`AUDIO
`SUBSYSTEM
`
`24
`
`26
`
`SYSTEM
`MEMORY
`
`18
`
`(57) Abstract
`
`A computer which is capable of displaying both video and graphical data is provided with a central processing unit (10), a
`memory controller (14), and a display system (4). These units are all connected to a bus (16). Modular functional units (2), e.g.
`video codecs, TV outputs, audio subsystems, are used to provide optional additional functions for the display system. A coupling
`means (6, 12) is provided to link the modular functional units to the display system (4) and to the memory controller (14).
`
`Petitioner Apple Inc. - Exhibit 1007, p. 1
`
`

`

`FOR THE PURPOSES OF INFORMATION ONLY
`
`Codes used to identify States party to the PCf on the front pages of pamphlets publishing international
`applications under the PCf.
`
`AT
`AU
`88
`BE
`BF
`BG
`BJ
`BR
`CA
`CF
`CG
`CH
`Cl
`CM
`cs
`cz
`D£
`DK
`ES
`Fl
`
`Au• tria
`Australia
`Barbados
`Belgium
`Burkina Faso
`Bulgaria
`Benin
`Brazil
`Canada
`Centr.ll African Republic
`Congo
`Swil7.crland
`Cote d'Ivoire
`Cameroon
`C:r.cchoslovakia
`(3.&..-ch Rcpubli&:
`(icrmany
`Denmark
`Spain
`Finland
`
`FR
`GA
`GB
`GN
`GR
`HU
`IE
`IT
`JP
`KP
`
`KR
`KZ
`1.1
`LK
`I.U
`MC
`MG
`ML
`MN
`
`France
`Gabon
`Umtcd Kingdom
`Guinea
`Greece
`Hungary
`Ireland
`Italy
`Japan
`Democratic People'• Republic
`of Korea
`Republic of Korea
`Ki!7~tkhstan
`Li~o-chtcnstein
`Sri Lanka
`Luxembourg
`Monaco
`Madtiga>car
`Mali
`Mongolia
`
`MR
`MW
`NL
`NO
`NZ
`PL
`PT
`RO
`RU
`SD
`SE
`SK
`SN
`su
`TD
`TG
`UA
`us
`VN
`
`Mauritania
`Malawi
`Netherlamls
`Norway
`New Zealand
`Poland
`Portugal
`Romania
`Russian Federation
`Sudan
`Sweden
`Slovak Republic
`Senegal
`S!lviet Union
`Chad
`Togo
`Ukraine
`United States of America
`VietNam
`
`,
`
`~
`
`Petitioner Apple Inc. - Exhibit 1007, p. 2
`
`

`

`wo 93/21574
`
`PCf/GB93/00749
`
`MULTIMEDIA DISPLAY
`
`FIELD OF THE INVENTION
`This invention relates to computers and in particular to computers
`which can display both video and graphics data.
`
`BACKGROUND OF THE INVENTION
`Historically, computer systems have been designed and produced
`without careful considerations for video and to a lesser extent
`audio capabilities. Many systems have been produced that add video
`capability to the computer system by colour keying and analogue
`multiplexing of the computer's graphics output. For example US
`Patent No. 5,027,212. Such systems generally involve multiple
`frame buffers holding video and graphics data separately. More
`recently a unified approach based on a single frame buffer of the
`type described in our International Patent Application No. PCT
`GB9202164 has been adopted. This approach treats video and
`graphics in exactly the same way. The single frame buffers can be
`based on either triple port memories or time multiplexing of video
`and graphics data on a common bus using suitable rate buffering and
`arbitration as described in the above numbered International patent
`application.
`
`These techniques can be or have been used to integrate video into a
`computer display system. However, to date, such integration has
`been carried out within the constraints of the available personal
`computers and workstations. This has meant that such systems are
`costly and bulky and have limited expandability.
`
`SUMMARY OF THE INVENTION
`In preferred embodiments of this invention a conventional graphics
`subsystem is closely coupled with a video processing subsystem
`capable of performing a number of essential functions described
`below. Both graphics and video processing subsystems have access
`
`- 1 -
`
`Petitioner Apple Inc. - Exhibit 1007, p. 3
`
`

`

`W093/21574
`
`PCI'/GB93/00749
`
`to the shared frame buffer via the techniques described in
`International patent application no. PCT GB9202164. The
`combination consistutues a 11videographics 11 subsystem which caters
`for cost effective. and modular multimedia enablement.
`
`Preferred embodiments of this invention seek to remove these
`limitations by moving to a computer architecture which takes the
`multimedia requirements into account in the initial system
`architecture.
`
`Four preferred embodiments provide architectural structures that
`allow compact and cost effective multimedia computer systems to be
`constructed and configured. The modularity is achieved by
`equipping the base computer system with the required expansion
`capabilities and basic services allowing easy and cost effective
`addition of special function modules for multimedia capability.
`particular the proposed architecture caters for the inevitable
`trend towards very compact personal computers.
`
`In
`
`The proposed systems take into account the need to add efficiently
`special function modules, such as video codecs, (coder/decoders),
`still image compression, analogue video input, TV output and audio
`subsystems to a modern computer system. Four architectures are
`described. The first approach includes a videobus for moving high
`speed data between various functional modules and an integrated
`frame buffer. The integrated frame buffer combines the normal
`computer graphics with the video data. The functional modules are
`centrally controlled and fed with control signals and compressed
`data over a serial communications system. The second approach
`replaces the parallel videobus with a collection of additional
`point-to-point serial communications between the graphics subsystem
`and the functional modules. The third approach is a further
`extension of the first approach in that it combines the
`functionality of the high speed video bus with that of the serial
`connections carrying control/compressed data.
`In this aproach a
`single bus connects the various functional modules to the
`
`- 2 -
`
`Petitioner Apple Inc. - Exhibit 1007, p. 4
`
`

`

`wo 93/21574
`
`PCf/GB93/00749
`
`graphics/video subsystem. This single bus carries both data and
`control tokens which can include uncompressed and compressed
`video/audio data, set up and configuration data as well as other
`control data.
`
`The fourth approach further combines the multimedia bus described
`in the third approach with the main computer bus.
`In this approach
`the single system bus will require to have both the necessary
`bandwidth and the real time capabilities required in a multimedia
`environment. All approaches partition the architecture in such a
`way as to both maximise system performance and minimise system cost
`by proper exploitation of silicon integrated trends.
`
`The invention is defined in the appended claims to which reference
`should now be made.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`The invention will now be described in more detail, by way of
`example, with reference to the accompanying drawings in which:
`
`Figure 1 shows a first computer system embodying the invention;
`
`Figure 2 shows a second computer system embodiying the invention;
`
`Figure 3 shows a third computer system embodying the invention;
`
`Figure 4 shows a computer system, which modifies the embodiment of
`Figure 1; and
`
`Figure 5 shows a fourth embodiment of the invention.
`
`DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
`Videobus Based Architectures
`In this approach, as shown in Figure 1, a plurality of modular
`functional units 2 are directly coupled to and communicate with a
`computer's graphics subsystem 4 via a videobus 6. The base
`
`- 3 -
`
`Petitioner Apple Inc. - Exhibit 1007, p. 5
`
`

`

`W093/21574
`
`PCf/GB93/00749
`
`graphics subsystem includes a video processing unit 8 1 for carrying
`out processes such as format conversions (e.g. YUV to RGB etc.} and
`scaling functions along with a graphics controller 9 and circuits
`for combining video and graphics data in a frame buffer. An
`important feature of the proposed architectures is the
`incorporation of a number of video functions performed by the video
`processing unit in the normal computer graphics subsystem. These
`additional capabilities include but are not limited to:
`
`1. Video scaling which allows the incoming video to be enlarged
`or scaled down before it is written into the shared frame
`buffer. The scaling down can be carried out using techniques
`covered in US Patent No. 5027212. The scale up can use
`techniques such as bilinear interpolation.
`
`2. Video format conversion '111hich supports conversion between
`various YUV and RGB video streams before the video data is
`written to the frame buffer. The particular formats of
`interest are YUV 422 1 YUV 411 1 YUV 444 1 RGB 24 1 RGB 16 (5,5,5
`and 5,6,5) and RGB 8. The format conversion allows a degree
`of data compression as YUV format is denser than the
`conventional RGB. Also direct support for YUV allows lowcost
`interfacing to video digitisers which. generally rely on YUV
`format. Also software video codecs can benefit from hardware
`support for their format conversion and scaling requirements.
`The format conversion can be done using a general 3x3 matrix
`multiplier architecture and conventional interpolating and
`decimating functions.
`
`3. Video windowing which allows certain video pixels to be
`written to specific areas within a shared frame buffer and
`certain video pixels to be masked so that they are. not loaded
`into the frame buffer. This will allow complex video windows
`and graphics overlays to be displayed in the graphics buffer.
`
`_i-
`
`4. A possible capability of the video processing system '111hich is
`
`- 4 -
`
`Petitioner Apple Inc. - Exhibit 1007, p. 6
`
`

`

`W093/21S74
`
`PCf /GB93/007 49
`
`closely coupled to the graphics subsystem is the concept of
`pixel masking. This capability can be supported two ways.
`One is where a mask bit is supplied by a modular function unit
`along a pixel stream. This mask bit determines ~1hether a
`pixel is displayed or thrown away as it enters the shared
`frame buffers. The alternative approach is based on the video
`subsystem accessing a mask plane in the graphics memory and
`depending on the state of the mask bit update the shared frame
`buffer with the pixel data or not.
`
`5.
`
`6.
`
`The video processing unit can access the graphics data and
`colour key the video by choosing a graphics colour for
`deciding whether a pixel i~ the shared frame buffer is
`overwritten by the incoming pixel stream.
`
`The video processing unit has a decompression capability
`whereby it can decompress streams that it receives over the
`video bus or from the host via the graphics subsystem. This
`is necessary where video data has been stored in compressed
`form and is known as sofb1are playback of data.
`
`7. All the features in 1-6 above can be accessed in software as
`an extension to graphics capabilities.
`
`8.
`
`The video processing subsystem and the graphics subsystem both
`have access to a shared frame buffer. The techniques used to
`achieve this are described in International patent aplication
`no. PCT GB9202164 where a small amount of buffer is provided
`for the video channel to deal with the real time needs and the
`shared memory is arbitrated between the packetised video and
`the graphics controller. The buffer on the video channel
`allo~1s critical activities such as memory refresh and screen
`updates to be carried out while the video data is collected in
`the buffer. During non critical graphics activites the video
`buffer is emptied into the shared frame buffer while the
`graphics controller is kept in an inactive state.
`
`- 5 -
`
`Petitioner Apple Inc. - Exhibit 1007, p. 7
`
`

`

`W093/21574
`
`PCf/GB93/00749
`
`9. The video processing unit has an address generation unit
`allowing it to address the shared frame buffer in the required
`manner.
`
`10. The video processing unit can also output proportions of the
`shared frame buffer with optional processing such as scaling
`to the video bus. A video encoder can be used to convert such
`regions of interest to a TV signal.
`
`i
`
`There are two main reasons for including the video postprocessing
`unit 8 as a central resource in the graphics/video (videographics)
`subsystem. One reason is that ~unctions such as scaling and format
`conversion often result in an increase in bandwidth. By including
`these functions as a postprocessing activity in the graphics/video
`subsystem, the actual required bandwidth between the modular
`functional units and the graphics/video subsystem is minimised.
`This results in a much less complex videobus specification and
`demands less performance from the videobus. The second reason for
`the inclusion of the video processing unit as a central resource in
`the graphics/video subsystem is that all the modular functional
`units 2 can share this resource which results in simplifications in
`these units, and hence cost reduction.
`
`The scaling operation can compensate for aspect ratio differences
`between a computer display and the incoming video signal as well as
`up/down scaling of the video to fit users requirements.
`
`The modular functional units communicate with a CPU 10 and are
`controlled via a collection of serial connections 12. These serial
`connections originate from a memory controller 14 and each connects
`to an individual modular functional unit 2. The CPU 10, the memory
`controller 14 and the graphics subsystem 4 are the three main
`elements of the base computer that are tightly coupled over a high
`performance bus 16 (Mem Bus). The memory controller 14 supports
`memory accesses to a system memory 18 originating from the CPU 10
`
`- 6 -
`
`Petitioner Apple Inc. - Exhibit 1007, p. 8
`
`

`

`wo 93/21574
`
`PCf/GB93/00749
`
`and from the graphics subsystem 4 as well as providing direct
`memory access {DMA) channels via the serial connections 12 to the
`modular functional units 2. This arrangement effectively decouples
`the tightly coupled CPU/memory/graphics subsystems from the
`optional and the more loosely coupled multimedia functional units
`2.
`
`The independent DMA support, via the memory controller, for these
`modular functional units 2 ensures that the real time needs of
`these units are met without frequent intervention from the CPU 10.
`
`This approach also reduces the complexity of the support software
`needed in the system. This is ~articularly so since the DMA
`capability and the intelligence level of the memory controller unit
`can be modified towards a balanced operation.
`
`Each modular functional unit 2 can read from or write to a relevant
`region of interest in a display buffer within the video/graphics
`subsystem 4. Mask planes in the graphics subsystem are used to
`control active areas associated with each video window. The access
`of the functional units 2 to the shared videobus is time
`multiplexed. The protocol for this multiplexing can be sub-line,
`line or region oriented. The exact choice will vary the extent of
`the buffering needed in each functional unit and the degree of
`context required in the video processing unit.
`
`Examples of the modular functional units include video Digitisers,
`TV Encoders H261 video conferencing module, MPEG decoder and JPEG
`still image coders/decoders.
`
`An enhanced version of the system is shown in Figure 2, where the
`memory controller 14 incorporates an intelligent router 22 which
`allows functional units 2 to communicate with each other directly.
`In this system by simply adding headers to data packets travelling
`on the serial links, the router will be able to set up dynamic
`circuits between various modules without interfering with the CPU
`
`- 7 -
`
`Petitioner Apple Inc. - Exhibit 1007, p. 9
`
`

`

`W093/21574
`
`PCf/GB93/00749
`
`or the system memory.
`
`Alternatively, the point-to-point connections between the memory
`controller and the functional units 2 can be replaced with a single
`serial bus (not illustrated). Such a system will of course offer
`lower performance.
`
`Also as sho~m in Figure 1, the architecture easily allows inclusion
`of an audio subsystem 24 (digital signal processor, DSP) via a
`serial connection.
`In fact the DMA driven serial connections
`originating from the memo~] controller offer an ideal mechanism for
`adding other key subsystems such as disk 26 (or disk arrays} as
`demonstrated in Figure 1.
`
`Networking (LAN'sr MAN's, WAN's) interfaces can also be added to
`the system in a similar manner. Again the impact of these options
`on the CPU will be minimal as any real time transaction can take
`place via the memory control with little CPU intervention.
`
`Direct Architecture
`In this second approach the videobus is replaced with multiple
`point-to-point serial connections 28 between the functional units 2
`and graphics/video subsystem 4. This is shown in Figure 3 .
`In
`this approach the video processing unit will sufficiently buffer
`the data arriving from or leaving on each serial connection. The.
`video post processing (format conversion/scaling) is then carried
`out on a time multiplexing basis. Leaving the format conversion
`and scaling function to the graphics/video subsystem 4 {as compared
`to the operation being done by individual functional units) ensures
`minimisation of the data rate requirement for the serial
`connections 28.
`
`The basic operation of this approach is very similar to that
`described for the videobus based architecture. The advantage of
`the Direct Architecture is in minimisation of parallel buses. This
`has three major benefits:
`
`- 8 -
`
`Petitioner Apple Inc. - Exhibit 1007, p. 10
`
`

`

`WO 93/21574
`
`PCf/GB93/00749
`
`1.
`
`2.
`
`3.
`
`A vePJ compact base machine can be provided.
`
`Much better utilisation of space on optional functional
`units is possible by virtue of avoiding large connector
`areas; and
`
`Real-time performance requirement can be addressed in a
`much easier way as various activities are highly
`decoupled.
`
`It is proposed that the systems embodying the invention can be
`provided such that each block shown in the figures can be provided
`on a single chip thereby enabling a very compact computer
`to be
`produced. Thus all that is needed is a chip for the CPU, a chip
`for the graphics/video subsystem, and a chip for the memory
`controller/router. Alternatively all may be provided on a single
`chip or combinations of the various units may be provided on single
`chips.
`
`MULTIMEDIA BUS APPROACH
`In Figure 4 there is shown a further extension of the embodiment of
`Figure 1 in which the videobus 6 and serial connectors 12 of the
`system of Figure 1 are combined into a single multimedia bus 30
`which carries both data (video, audio, compressed and
`uncompressed), and the control information previously transmitted
`by serial connectors 12 of Figure 1. This has all the advantages
`associated with a combined graphic and video subsystem, capable of
`video scaling and format conversion.
`
`,.
`
`The multimedia bus 30 operates in a time sharing mode using a
`packetised data/control protocol. The exact nature of the protocol
`employed is not critical to the present invention and various
`options will be kno~In to those skilled in the art. All that is
`
`- 9 -
`
`Petitioner Apple Inc. - Exhibit 1007, p. 11
`
`

`

`W093/21574
`
`PCf/GB93/00749
`
`required is an arbitration and scheduling scheme which can allocate
`sufficient bandwidth to each device and guarantee a worst case
`latency in operation. Such an approach allows the real time need
`needs of the system to be met. For example, a round robin
`scheduler allocating different amounts of time to each device can
`both provide the band~1idth in a predetermined way and obtain a
`worst case system laten~J. Multiple priorities can be added to the
`scheduler to allo~T a reduced latency figure for those devices which
`are allocated a higher priority.
`
`SINGLE BUS APPROACH
`A fourth approach illustrated in Figure 5 combines the multimedia
`bus of Figure 4 with the main c~mputer bus. This gives a system
`bus 32 coupling the videographics subsystem 4, CPU 10, and the
`modular functional units 2r The main requirement of this combined
`system bus is that it should be capable of real time operation.
`Thus it must be able to operate in such a way as to be able to
`allocate sufficient bandwidth to each device and to guarantee a
`worst case latency. Preferably it operates using the same type of
`packetised data/control protocol as that referred to with reference
`to Figure 4. Again the videographics subsystem is capable of video
`scaling and format conversion and thus possesses all the advantages
`described with reference to Figure 1.
`
`In all of the above cases the integration of the video processing
`subsystem and the graphics subsystem into a single videographics
`subsystem capable of performing both graphics and video functions
`(scaling, format, conversion, windowing and masking) is an
`important part of the proprosed invention. The functionality of
`the graphics and the video processing, sharing the same frame
`buffer, can be implemented in any one of many VLSI devices.
`
`- 10 -
`
`Petitioner Apple Inc. - Exhibit 1007, p. 12
`
`

`

`W093/21574
`
`PCf/GB93/00749
`
`CLAIMS
`
`A computer for displaying both video and graphical data
`1.
`comprising a central processing unit (CPU), a memory controller and
`a display system all connected to a bus and means for coupling at
`least one modular functional unit to the memory controller and to
`the display system.
`
`A computer according to claim 1 in which the display system
`2.
`incorporates a video processing means.
`
`A computer according to claim 2 in which the modular
`3.
`functional units access the graphics system via the video
`processing means.
`
`A computer according to claim 1, 2 or 3 in which the coupling
`4.
`means comprise bidirectional connections between the functional
`unit and the display system.
`
`5. A computer according to claim 1, 2, 3 or 4 in which the
`modular functional units make time multiplexed accesses to the
`display system.
`
`A computer according to any preceding claim in which the
`6.
`coupling means comprises a plurality of point to point connections
`for coupling the memory controller to modular functional units.
`
`A computer according to any of claims 1 to 5 in which the
`7.
`coupling means comprises a second bus means for coupling the
`memory controller to modular functional units.
`
`A computer according to any preceding claim in which the
`8.
`coupling means comprises a plurality of point to point connections
`for coupling the display system to modular functional units.
`
`9.
`
`A computer according to any of claims 1 to 7 in which the
`
`- 11 -
`
`Petitioner Apple Inc. - Exhibit 1007, p. 13
`
`

`

`W093/21574
`
`PCf/GB93/00749
`
`coupling means comprises a third bus means for coupling the display
`system to modular functional units.
`
`10. A computer according to any preceding claim in which the
`memory controller is coupled to a fourth bus means for accessing a
`memory means.
`
`11. A computer according to any preceding claim in which the
`memory controller provides memory accesses in response to signals
`from the CPU and from the display system.
`
`12. A computer according to any preceding claim in which the
`memory controller includes routing means whereby modular functional
`units may communicate with each other.
`
`13. A computer according to claim 1 in which the CPU, the memory
`controller, and the display system are. each provided on a separate
`integrated circuit.
`
`14. A computer according to claim 1 in which at least two of: the
`CPU; the memory controller; and the display system, are provided on
`a single chip.
`
`15. A computer according to claims 1, 2 or 3 in which the
`coupling means comprise a multimedia bus linking the functional
`units to the display system and the first bus which links the
`display system to the memory controller.
`
`16. A coputer according to claim 15 in which the multimedia bus
`operates in a time sharing mode for the transmission of data and
`control signals.
`
`17. A computer according to claims 1, 2 or 3 in which the
`coupling means comprises the bus to which the functional units are
`also connected.
`
`- 12 -
`
`f
`
`.-
`
`Petitioner Apple Inc. - Exhibit 1007, p. 14
`
`

`

`WO 93/21574
`
`PCf/GB93/00749
`
`l
`
`18. A computer according to claim 17 in which the bus is a
`multimedia bus.
`
`19. A computer according to claim 18 in which the bus operates in
`a time sharing mode for the transmission of data and control
`signals.
`
`20. A computer according to claim 2 in which the video processing
`means comprise video scaling means.
`
`21. A computer according to claims 2 or 20 in which the video
`processing means comprise video format conversion means.
`
`22. A computer according to claims 2, 20 or 21 in which the video
`processing means comprise masking means to protect areas of a frame
`buffer associated with the display system.
`
`23. A computer according to claim 2, 20, 21 or 22 in which the
`video processing means comprises decompression means for software
`playback of data.
`
`- 13 -
`
`Petitioner Apple Inc. - Exhibit 1007, p. 15
`
`

`

`B
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`VIDEO
`
`1-"2
`
`r--FUNCTIONAL
`
`MODULAR
`
`UNIT '3
`
`UNIT 2
`FUNCTIONAL
`MODULAR ~
`2
`6
`BUS
`VIDEO
`
`\
`
`FUNCTIONAL
`
`UNIT 1
`MODULAR
`
`)
`2
`
`\)
`12
`
`4
`
`Fig 1
`
`•
`
`Petitioner Apple Inc. - Exhibit 1007, p. 16
`
`

`

`c
`R
`B
`M
`G
`A t-----R
`R
`
`M
`GRAPHICS 1---; ~
`V
`
`PROCESSOR CONTROLLER
`
`VIDEO
`
`c:-v9
`
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`
`SUBSYSTEM
`
`'--' 18
`
`MEMORY
`SYSTEM
`
`26-' SUBSYSTEM --
`
`DISK
`
`~~----~--~----
`
`22
`7
`
`24-SUBSYSTEM
`
`AUDIO
`
`t-10
`
`CPU
`
`~----------; ROUTER CONTROLLER f-14
`
`MEMORY
`
`MEM BUS
`
`vi6
`
`FUNCTIONAL .,____.
`MODULAR
`
`~--"2
`
`UNIT "3
`
`8
`}
`
`I
`
`UNIT 2
`FUNCTIONAL 1---.J
`MODULAR ~
`2
`
`-
`
`\
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`
`BUS
`
`UNIT 1
`MODULAR
`
`.---+-'-----1 F U NCTI 0 NAL .,_......,
`
`1~'\
`
`4
`
`Fig.2
`
`Petitioner Apple Inc. - Exhibit 1007, p. 17
`
`

`

`lo"Cj 8 C'l = IC w
`
`....... = = -..!
`
`IC
`oi:lo.
`
`-18
`
`MEMORY
`SYSTEM
`
`SUBSYSTEM -
`
`DISK
`
`26--
`
`I I
`
`22
`}
`
`r--
`
`SUBSYSTEM
`
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`
`24-
`
`._-10
`
`CPU
`
`CONTROLLER f---14
`MEMORY
`
`ROUTER
`
`MEM BUS
`
`UNIT' 3
`FUNCTIONAL 1--------'
`MODULAR ~2
`
`(
`A
`tzz M
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`
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`-..!
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`IC w
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`
`8
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`UNIT
`P~6~~~SING GRAPHICS V /L
`
`CONTROLLER
`
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`
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`
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`
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`
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`
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`
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`
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`
`_----,~ FU NCT I 0 NA L ..______,
`
`UNIT 2
`
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`
`MODULAR
`
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`
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`MODULAR
`
`F(q. 3
`
`Petitioner Apple Inc. - Exhibit 1007, p. 18
`
`

`

`MEMORY
`SYSTEM
`
`10
`
`CPU
`
`14
`
`CO NT ROLLER
`MEMORY
`
`MEM BUS
`
`16
`
`4
`
`2
`
`Fig. 4
`
`•
`
`Petitioner Apple Inc. - Exhibit 1007, p. 19
`
`

`

`_.. 10
`
`CPU
`
`MEMORY
`SYSTEM
`
`18-
`
`32
`I
`\
`MEM BUS
`
`PROCESSING CONTROLLER
`
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`
`UNIT
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`
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`FUNCTIONAL
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`
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`
`UNIT 2
`MODULAR
`
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`
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`
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`
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`
`SUBSYSTEM
`
`4
`
`Fig.5
`
`,,
`
`Petitioner Apple Inc. - Exhibit 1007, p. 20
`
`

`

`INTERNATIONAL SEARCH REPORT
`Int.....Uonal Application No
`
`PCT/GB 93/00749
`
`I. CLASSIFICATION OF SUBJECT MATTER
`(If several dasslfication symbols apply, Indicate all)'
`Ac:a~rdlng to International Patent Classification (IPC) or to both National Qassification and IPC
`Int.Cl. 5 G06F3/14
`
`D. FIEIJ)S SEARCHED
`
`Classification System
`
`Int.Cl. 5
`
`Minimum Documentation Searched'
`
`Classification Symbols
`
`G06F '
`
`G09G
`
`'
`
`H04N
`
`DDCUmentation Searched other than Minimum Documentation
`to the Extent that such DDCUments are Induded In the Fields Searched a
`
`m. DOCUMENTS CONSIDERED TO BE RELEVANT9
`Category 0
`Citation of DDCUJDIIIt, 11 with indication, where appropriate, of the reliMlllt passages 12
`
`ReiiMlllt to Claim No.ll
`
`P,X
`
`P,A
`
`EP,A,O 493 881 (INTERNATIONAL BUSINESS
`MACHINES CO.)
`8 July 1992
`
`see page 2, column 1, line 16 - page 3,
`column 4, line 25
`see page 6, column 10, line 46 - page 7,
`column 11, line 46
`see page 7, column 12, line 37 - page 8,
`column 13, line 43
`see page 9, column 15, line 35 - line 39
`see figures 1,3
`---
`
`-1--
`
`1
`
`2,7,9
`
`0 Special categories of dted documents : 10
`• A • dDCUment defining the general state of the art wblch Is not
`considered to be of partla~lar reliMUlce
`"'E"' earlier dDCUJDent but published on or after the International
`fillna date
`"11' document which may throw doubts on J:riorlty dalm(s) or
`which Is cited to establish the publica on date of another
`citation or other special reason (as specified)
`•o• dDCUJDent referring to an oral disclosure, use, extubition or
`other means
`•pao dDCUJDent published prior to the international filing date but
`later than the priority date dalmed
`
`"T"' later dDCUJDent published after the International filing date
`or priority date and not In conflict with the ap/.Ucation but
`dtltl to understand the prindple or theory un eriylna the
`Invention
`"X"' dDCUJDIIIt of partlaJlar relevance; the dalmed Invention
`cannot be considered nowl or cannot be considered to
`Involve an Inventive step
`-v• dDCUJDent of partia~lar relevance; the dalmed Invention
`cannot be considered to involve an Inventive step when the
`dDCUJDent is combined with one or more other such docu-
`meats, such comblnatlnn being obvious to a person skilled
`In tbe art.
`• &• dDCUJDent member of the same patent family
`
`2 IV. CERTIFICATION
`Date of the Actual Completion of the International Search
`22 JULY 1993
`
`Date of Mailing of this International Search Report
`
`.,. ~~ 07 f'3
`
`c. ...... :
`
`~.:J
`
`International Searching Authority
`
`EUROPEAN PATENT OFFICE
`
`Slgoature of Authorized Officer
`FARRICELLA L.
`
`Fom PCT/ISA/210 (lleCOM llleet) (.J__, 1915)
`
`Petitioner Apple Inc. - Exhibit 1007, p. 21
`
`

`

`ID. DOCUMENTS CONSIDERED TO BE RElEVANT
`
`(CONTINUED FROM THE SECOND SHEET)
`
`Ctation of Doa~~~~e~~t, with indication, where appropriate, of the relevant passages
`
`Relevant to Claim No.
`
`lntS'IIational Application No
`
`PCT/GB 93/00749
`
`1
`
`A
`
`A
`
`A
`
`EP,A,O 454 414 (SONY CORPORATION OF
`AMERICA)
`30 October 1991
`see page 3, column 2, line 46 - page 4,
`column 3, line 11
`see page 4, column 4, line 1 - line 10
`see page 5, column 5, line 10 - page 6,
`column 7, line 1
`see figure 2
`
`FUNKSCHAU
`vol. 62, no. 26, 14 December 1990,
`MUNCHEN DE
`pages 60 - 75
`'Computer mit
`KAMENZKY ET AL.
`Fernseh-Ambitionen'
`
`COMPUTER TECHNOLOGY REVIEW
`vol. 12, no. 4, April 1992, LOS ANGELES US
`page 1
`B. CAHILL
`Triclc 1
`
`'Integrating Video/Graphics Neat
`
`Petitioner Apple Inc. - Exhibit 1007, p. 22
`
`

`

`ANNEX TO THE INTERNATIONAL SEARCH REPORT
`ON INTERNATIONAL PATENT APPLICATION NO.
`
`GB 9300749
`72686
`SA
`
`'Ibis annex lists tbe patent family members relating to tbe patent doc:uments cited in the above-meatiooed international sean:h report.
`The memben; are as contained in tbe European Patent Office EDP file on
`22/07/93
`The European Patent Office is in no way liable for these partic:ular5 whicb are merely given for tbe purpo&e of information.
`
`Publication
`Patent family
`Patent document
`Publication
`cited in llelll'1:b report
`date
`member( II)
`date
`04-12-92
`JP-A-
`08-07-92
`EP-A-0493881
`4351181
`----------------------------------------------------------------------
`EP-A-0454414
`30-10-91
`None
`
`I
`~
`~~----------------------------------------------------------------------~
`l!l For more details about this anoex : &ee Official Journal of tbe European Patent Office, No. 12/82
`
`Petitioner Apple Inc. - Exhibit 1007, p. 23
`
`