United States Patent
`
`[19]
`
`4,212,057
`[1 1]
`[45] Jul. 8, 1980
`Devlin et al.
`
`
`
`..... .. 340/ 172.5
`340/172.5
`340/172.5
`340/172.5
`.... .. 364/200
`340/172.5
`...... 364/2(X)
`... . .. 364/200
`364/200
`
`
`
`..
`6/1975 Alferness et al.
`7/1975
`Brown .............. ..
`ll/1975
`Emm et al.
`l/1976 Gruner et al.
`2/1976
`Fitzgerald
`5/1976 Valassis et al.
`..
`9/1976
`Bernstein et al.
`12/1976
`Barlow et al.
`... . .
`I0/1977
`Jenkins et al.
`
`.
`
`3,889,237
`3,896,418
`3,921,145
`3,931,613
`3,940,743
`3,959,775
`3,932,231
`4,(X)0,485
`4,055,851
`
`FOREIGN PATENT DOCUMENTS
`
`1279955 6/1972 United Kingdom ................... .. 364/200
`
`Primary Examiner-—Melvin B. Chapnick
`Attorney. Agent, or Firm--Geoffrey H. Krauss; James C.
`Davis; Marvin Snyder
`
`[57]
`
`ABSTRACT
`
`A multiprocessor microcomputer system having two or
`more substantially independent processors each of
`.
`.
`.
`.
`which has its own bus-type interconnection structure,
`and a shared memory accessible by any of the proces-
`SOTS Without interferrins with the Proper Operation of
`the other processors. Controlled access to the memory
`by connecting the memory to the processor requesting
`access when only one such request is present and to the
`last processor to have received access when more than
`one request is received simultaneously allows autosyn-
`h
`t.
`t
`t.
`I
`t.
`f
`.
`.t
`d
`°, '°“°“-5 °P°"“ ‘°“' F“ °'““ ‘C 5‘ '3‘ ‘°‘‘ ° P“°“ 3’ 3“
`W31‘ 5P¢°d 07 °P°“‘“°"~
`
`9 Claims, 4 Drawing Figures
`
`[54] SHARED MEMORY
`MULTI-MICROPROCESSOR COMPUTER
`SYSTEM
`
`[75]
`
`Inventors: Charles L. Devlin, Ballston Lake;
`Charles W. Eiehelberger,
`Schenectady, both of N.Y.
`
`[73] Assignee:
`
`General Electric Company,
`Schenectady, N.Y.
`
`[21] Appl. No.: 679,400
`
`[22] Filed:
`
`Apr. 22, 1975
`
`[51]
`
`rm. 0.2 .................... .. coar ism; G06F 13/00;
`soar 9/18
`.................................................. .. 364/zoo
`[52] us. Cl.
`
`[58] Field of Search ...................... 340/172.5, 147 LP;
`445/ l; 364/2(1) MS File, 900 MS File
`
`rencel
`
`Cited
`were
`'35- PATENT DOCUMENTS
`5/I969 Driscoll ................................ 364/200
`9/1969 Richmond et al.
`340/172.5
`4/1970 Barlow et al.
`364/200
`V1971
`“Buck 5! 81-
`----- -- 364/200
`2/1971
`Ernst et al. .
`........ 340/172.5
`“M972 N°'b°'3 """"
`340/1" LP
`....
`12/1972
`Takashi et al.
`...... .. 340/172.5
`s/1973 Anderson et al.
`340/172.5
`9/1973
`Brandsma et al.
`340/172.5
`10/1974
`Lange et al.
`340/172.5
`S/1975
`Brown et al.
`........................ 364/200
`
`
`
`.
`.
`
`56
`
`I
`
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`
`3,44s,s22
`3469.239
`3.505.651
`3555-513
`3,560,934
`3'699‘524
`3,706,077
`3,735,350
`3,751,379
`3,845,474
`3,886,525
`
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`10/1’
`
`Petitioner Apple Inc. - Exhibit 1021, p. 1
`
`Petitioner Apple Inc. - Exhibit 1021, p. 1
`
`

`
`U.S. Patent
`
`Jul. 8, 1980
`
`Sheet 1 of4
`
`4,212,057
`
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`Petitioner Apple Inc. - Exhibit 1021, p. 2
`
`Petitioner Apple Inc. - Exhibit 1021, p. 2
`
`

`
`U.S. Patent
`
`JUL 8,1980
`
`Sheet2 of4
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`4,212,057
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`Petitioner Apple Inc. - Exhibit 1021, p. 3
`
`Petitioner Apple Inc. - Exhibit 1021, p. 3
`
`

`
`U.S. Patent
`
`Jul. 8, 1930
`
`Sheet 3 of4
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`4,212,057
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`
`Petitioner Apple Inc. - Exhibit 1021, p. 4
`
`Petitioner Apple Inc. - Exhibit 1021, p. 4
`
`

`
`U.S. Patent
`
`Jul. 3, 1980
`
`Sheet 4 of4
`
`4,212,057
`
`1—*::$
`66
`70 TRI-STATE
`P‘ —- BUFFERS
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`SHARED
`MEMORY
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`
`Petitioner Apple Inc. - Exhibit 1021, p. 5
`
`Petitioner Apple Inc. - Exhibit 1021, p. 5
`
`

`
`1
`
`4,212,057
`
`SHARED MEMORY MULTI-MICROPROCESSOR
`COMPUTER SYSTEM
`
`BACKGROUND OF THE INVENTION
`
`5
`
`l0
`
`15
`
`20
`
`25
`
`This invention relates, in general, to microcomputer
`systems and, more specifically, to a memory for use in a
`multiprocessor microcomputer system utilizing a bus
`interconnection structure.
`Microcomputers are becoming increasingly impor-
`tant in a wide ranging variety of applications. As econo-
`mics involved in the production of microprocessors and
`microcomputers continue to reduce the cost thereof,
`they will be utilized in more and more applications. It
`may often times be desirable to utilize more than one
`processing unit in conjunction with a single memory or
`a portion thereof. This may be desirable in order to
`divide the functions performed by a microcomputer
`among two or more processors in order to increase the
`capacity of the microcomputer system. Another advan-
`tage of a multiprocessor system is that lower cost may
`be achieved by enabling the implementation of a com-
`plex system with two or more relatively low cost pro-
`cessors as opposed to a single more complicated and
`consequently higher cost processor. A further advan-
`tage which may be obtained is that a system may be
`designed such that, in the event of failure of a single
`processor a second processor will assume the functions
`of the failed processor and thus provide a degree of
`redundancy not found in single processor systems. A 30
`still futher advantage attendant a multiprocessor mi-
`crocomputer system is that communications may be
`established between two or more processors through a
`shared memory directly accessible to any processor. A
`system of this type has the capacity for sharing not only
`data but also programming information and has the
`further advantage of allowing one processor to control
`the programming of another by modifying the instruc-
`tions stored in a single memory. Many microprocessors
`currently in use are organized according to a bus struc-
`ture for communication between the microprocessor
`and the other components of the microcomputer system
`as, for example, memory and input/output devices. A
`bus interconnection structure allows the ready modifi-
`cation of a microcomputer system by the substitution of 45
`components therein without the need for physical modi-
`fication of the basic system hardware. It is desirable,
`therefore, that a shared memory for utilization in con-
`junction with a multiprocessor microcomputer system
`be compatible with a bus-type interconnection struc-
`ture.
`
`35
`
`SUMMARY OF THE INVENTION
`
`These and other advantages and improvements in a
`multiprocessor microcomputer system are achieved in
`accordance with this invention. Briefly stated, and in
`accordance with one aspect of this invention, a multi-
`processor microcomputer system is provided having
`two or more substantially independent processors each
`of which has its own bus-type interconnection struc-
`ture, and a shared memory accessible by any of the
`processors without interferring with the proper opera-
`tion of the other processors. In accordance with an-
`other aspect of this invention, a multiprocessor shared
`memory microcomputer is provided wherein one pro-
`cessor is designated a priority processor and is allowed
`access to the shared memory on a priority basis without
`interferring with the proper operation of the other pro-
`z
`
`55
`
`65
`
`2
`cessors. The types of microprocessors used in conjunc-
`tion with a shared memory of the type with which this
`invention mainly is concerned often times operate in a
`mode which actively utilizes an associated memory for
`only a portion of the time, typically in accordance with
`a clock waveform wherein actual connection to mem-
`ory is required during only a certain phase of the clock.
`A shared memory in accordance with this invention
`enables two microprocessors to utilize a shared memory
`in a fashion providing extremely efficient use of a single
`memory by two or more processors. A feature of cer-
`tain memories in common use is that they are able to
`respond to requests for service from a microprocessor
`faster than the processor is able to utilize the service.
`For example, data can be written into or read out of a
`memory faster than certain microprocessors are able to
`perform the reading or writing operations. Accord-
`ingly, there is provided by this invention means for
`increasing the efficiency of memory utilization by en-
`abling a single shared memory to provide service to two
`or more processors such that the time during which one
`processor does not require service is dedicated to the
`other. In this way a substantial amount of time during
`which memory was previously inactive and, therefore,
`wasted is efficiently utilized.
`In accordance with still another aspect of this inven-
`tion, a shared memory is provided which may. if de-
`sired, appear to each of the two or more processors
`sharing it to be a different section of the total memory
`capability of the processor. For example, assume that
`each of two processors has the capability to address
`64,000 memory addresses. Assume still further that
`shared memory is provided in accordance with this
`invention to the extent of 8,000 addresses. In accor-
`dance with a feature of this invention, the 8,000 shared
`addresses might appear as addresses 0 through 7,999 to
`a first processor and 8,000 to 15,999 to a second proces-
`sor. Where desired, of course, the shared memory may
`be the same addresses for two or more processors.
`
`BRIEF DESCRIPTION OF THE DRAWING
`
`The features of the invention which are believed to be
`novel are pointed out with particularity in the appended
`claims. The invention itself, however, both as to its
`organization and method of operation together with
`further objects and advantages thereof may best be
`understood by reference to the following description
`taken in connection with the accompanying drawings in
`which:
`FIG. I is a block diagram of a multiprocessor mi-
`crocomputer in accordance with this invention wherein
`memory is shared between two or more processors.
`FIG. 2 is a detailed logical schematic diagram of a
`shared memory for utilization with two processors in
`accordance with a presently preferred embodiment of
`this invention.
`FIG. 3 is another detailed logical schematic diagram
`of a shared memory in accordance with this invention.
`FIG. 4 is a detailed logical schematic diagram of a
`shared memory for use with more than two micro-
`processors in accordance with this invention.
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`A two processor microcomputer including a shared
`memory in accordance with this invention is illustrated
`in block diagram form at FIG. 1. The computer, desig-
`
`Petitioner Apple Inc. - Exhibit 1021, p. 6
`
`Petitioner Apple Inc. - Exhibit 1021, p. 6
`
`

`
`4,212,057
`
`10
`
`20
`
`25
`
`30
`
`35
`
`3
`nated generally at 10, includes first processor 12 and
`second processor 14. It is to be understood that while
`this invention will be described in conjunction with
`FIG. 1 with respect to a multiprocessor microcomputer
`having two processors, that those skilled in the art will
`readily appreciate that two, three or more processors
`may readily be employed with a single shared memory
`in accordance with the teachings of this invention. Pro-
`cessor 12 has associated therewith a first bus structure
`generally designated at 16 which includes: an address
`bus 18, a data-out bus 20, a data-in bus 22, a read/write
`control bus 24 and a wait bus 26. It will be appreciated
`by one skilled in the art that while the read/write con-
`trol bus and wait bus are illustrated as single wires and
`the address and data buses are illustrated as three wires
`that the precise configuration of the buses will vary
`depending upon the type and number of signals required
`to be transmitted along the buses. For example,
`it is
`often times convenient to provide parallel address data
`inputs and outputs including as many as 16 bits. It will
`be appreciated that the address bus will contain a sum-
`cient number of distinct electrical connections to supply
`the requisite number of bits. Similarly, the data-out and
`data-in buses may contain, for example, 8 bits of parallel
`format information each and will therefore require 8
`conductor buses for each of the data-in and data-out
`buses. The read/write and wait buses may readily be
`accomplished utilizing only one electrical conductor
`referenced to ground or, alternatively, two or more
`conductors as desired. The specific form taken by the
`sundry buses depends upon the organization of the pro-
`cessor and related ancillary equipment utilized in accor-
`dance with this invention. Although not illustrated, it
`will be appreciated by those skilled in the art that addi-
`tional busses may be provided in accordance with par-
`ticular embodiments of this invention. For example,
`although not illustrated, power supply buses are under-
`stood to be included in the microcomputer system 10 of
`FIG. 1.
`A second set of buses substantially identical to buses
`18 through 26 is associated with second processor 14.
`These buses, 18', 20', 22', 24’ and 26' correspond to
`buses 18 through 26 associated with processor 12. Each
`of processors 12 and 14 and the associated bus struc-
`tures thereof is associated with certain peripheral com-
`ponents. Processor 12 is connected via bus structure 16
`to input/output device 30 and to local memory 32.
`Processor 14 and its associated bus structure 16 are
`connected to input/output device number 34, input-
`/output device 36 and local memory 38. It is to be un-
`derstood that the connection between the processors
`and the associated equipment hereinabove described is _
`conventional and will not, therefore, be described at
`great length herein. Briefly, the address buses 18 and 18’
`are supplied by the processors 12 and 14, respectively,
`with address information which is supplied to each
`device connected to the bus structure. The address
`present at any given time on the address bus will corre-
`spond to a particular address in a particular device and
`access will be gained to that device and to the particular
`location in the device to which the address corresponds.
`For example, a particular 16 bit address may corre-
`spond to a certain location in memory. Whenever the
`particular combination of bits appears on the address
`line that location in memory will be available to the
`processor. Buses 20 and 22 along with corresponding
`buses 20‘ and 22' are the data input and output buses.
`These buses provide paths between the devices for data
`
`45
`
`50
`
`55
`
`65
`
`4
`to be transferred from one device to another. The data
`input and output buses carry the actual data between
`devices. For example, data may be written into or read
`from memory by providing a memory address on the
`address bus and providing data from the processor onto
`the data-out bus from which it is received by the ad-
`dressed device. It will be appreciated that it may be
`required to supply to the memory further signals as
`exemplified by signals of the type carried by the read/-
`write buses 24 and 24' before data can be entered into or
`recovered from memory or other device. Wait buses 26
`and 26‘ provide signals from device requesting service
`when the device from which service is requested is
`unable to comply with a request. For example, if data is
`being supplied to an input/output device from a proces-
`sor, it will often times be the case that the processor is
`able to supply the data at a speed greater than that at
`which the input/output device can utilize it. In order to
`prevent data from being lost, a wait signal is sent to the
`processor to moderate the rate of data flow from the
`processor to the input/output device to an extent that
`the data is supplied at a rate at which the input/output
`device can accept it. This same relationship may exist
`between any two devices when the speeds at which
`they are able to perform various operations are differ-
`ent. In addition to the devices hereinabove described,
`microcomputer 10 includes shared memory 40. Shared
`memory 40 is connected to the bus structures associated
`with both processor 12 and processor 14. In accordance
`with a presently preferred embodiment of this invention
`shared memory 40 includes a single memory accessible
`to both processor 12 and processor 14. It is a feature of
`this invention that shared memory 40 may appear to
`each of the processors to be a different portion of the
`total memory accessible by each processor.
`An exemplary shared memory in accordance with a
`presently preferred embodiment of this invention is
`illustrated at FIG. 2. A memory 50 which may advanta-
`geously be a random access memory is provided having
`an address port 52, a data-in port 54, a data-out port 56,
`a read/write control port 58 and a memory enable port
`60. As was hereinabove described in conjunction with
`the discussion of FIG. 1, each of the aforementioned
`address, data-in, data-out, read/write and memory en-
`able ports may include one or more physical connec-
`tions. Address port 52 of memory 50 is connected to
`tri-state buffers 62 and 64. Buffers 62 and 64 provide
`selective connection between the address port 52 of
`memory 50 and the appropriate address buses associated
`with the two processors accessing the memory. In ac-
`cordance with this invention, the shared memory mod-
`ule of FIG. 2 may readily be employed in conjunction
`with a microcomputer structure of the type illustrated
`at FIG. 1 and the discussion hereinafter appearing will
`assume that the shared memory of FIG. 2 corresponds
`to shared memory 40 of FIG. 1. Accordingly, tri-state
`buffers 62 and 64 are connected to address buses 18 and
`18' of FIG. 1. It will be appreciated that while tri-state
`buffers 62 and 64 are illustrated as single blocks, that
`multiple blocks are employed as required in order to
`accommodate multiple address connections. Tri-state
`buffers 62 and 64 are characterized by input terminals
`66 and 68 respectively and output terminals 70 and 72.
`Tri-state buffer 62 is provided with gate input terminal
`74 which in this particular embodiment of the invention
`is an inverting input terminal, that is to say one which
`activates tri-state buffer 62 when a ground or logical
`zero signal is applied thereto. Corresponding gate input
`
`Petitioner Apple Inc. - Exhibit 1021, p. 7
`
`Petitioner Apple Inc. - Exhibit 1021, p. 7
`
`

`
`4,212,057
`
`5
`terminal 76 is provided at tri-state buffer 64. Tri-state
`buffers 62 and 64 provide selective connection between
`inputs 66 and 68 and outputs 70 and 72. When a logical
`zero level signal is applied to gate input terminal 74, for
`example, a low impedance electrical connection is pro-
`vided between input 66 and output 70. When gate termi-
`nal 74 is provided with a positive voltage, a logical one,
`no connection is provided between input 66 and output
`70 and output 70 is permitted to float, that is is not
`connected to either a zero or a plus signal but rather is
`left in a substantially unterminated state. The operation
`of tri-state buffer 64 is identical. The function of tri-state
`buffers 62 and 64 may be readily visualized by analogy
`to an electrical relay of the single pole, single throw
`type wherein input and output terminals 66 and 70 are
`the contacts of the relay and gate terminal 74 provides
`connection to the coil of the relay. It will be appreciated
`by those skilled in the art that the function of tri-state
`buffers 62 and 64 might be provided in a variety of
`fashions and this invention is not intended to be limited
`
`to any particular method or apparatus for obtaining the
`function hereinabove described. For example, tri-state
`buffers such as the 8216 or 8226 manufactured by Intel
`Corp., Santa Clara, California may be utilized.
`Additional tri-state buffers 78 and 80 provide selec-
`tive connection to read/write input 58 of memory 50
`from read/write inputs 82 and 84 respectively. Tri-state
`buffers 86 and 88 similarly provide connection to data-
`in port 54 from inputs 90 and 92 while buffers 94 and 96
`provide connection from data-out port 56 of memory 50
`to output terminals 98 and 100. It will be understood
`that as was the case with buffers 62 and 64 that buffers
`78, 80, 86, 88, 94 and 96 may provide more than a single
`electrical connection to the appropriate buses. It will be
`appreciated that the nature of the buffers permits direct
`connection to the appropriate buses of the microcom-
`puter systems. For example, buffer 62 is connected to
`bus 18, buffer 64 to bus 18', buffer 78 to bus 24, buffer 80
`to bus 24’, buffer 86 to bus 20, buffer 88 to bus 20‘, buffer
`94 to bus 22 and buffer 96 to bus 22‘. The shared mem-
`ory of FIG. 2 further includes AND gates 102 and 104
`which are adapted in accordance with this invention to
`be connected to that portion of buses 18 and 18' which
`carry the high order address bits. Those skilled in the
`art will appreciate that the address bus will carry a
`plurality of address bits in binary form. Visualizing the
`address data in parallel form, it will be appreciated that
`in the case wherein memory 50 includes a number of
`addresses smaller than the total number of addressable
`addresses by the processor that the higher order address
`bits will not be required in order to uniquely specify an
`address in memory 50 alone. They will, however. be
`necessary to distinguish the block of memory addresses
`represented by memory 50 from the remaining memory
`addresses accessible by the processor. Accordingly, the
`higher order address bits are applied to AND gates 102
`and 104 which provide signals at outputs 106 and 108
`thereof when memory 50 is addressed. Each of AND
`gates 102 and 104 includes a plurality of inputs 110 and
`112, the precise number of which will differ depending
`upon the relative size of memory 50 and the addressing
`capability of the processor. As AND gates 102 and 104
`provide outputs when each of the inputs thereof is at a
`high logic level, it will be appreciated that memory 50
`will be accessed when the respective processor ad-
`dresses the portion of memory having the highest ad-
`dress location. For example, wherein 16 bits are pro-
`vided by the processor to the address bus and further
`
`6
`wherein memory 50 includes, for example, 8000 ad-
`dresses and further wherein the 8000 addresses are the
`highest 8000 addresses addressable by the processor,
`and still further that the 8000 addresses represent one-
`eighth of the total number of addresses addressable by
`the processor, then three binary bits are required to
`uniquely determine which of eight blocks of memory is
`addressed. Accordingly, in the embodiment of this in-
`vention illustrated at FIG. 2, the three highest order
`address bits are applied to inputs 110 of AND gate 102
`and an output is produced at output 106 thereof when
`each of inputs 110 is high. It will be appreciated that any
`of the seven other blocks of memory will produce at
`least one bit at input 110 of AND gate 102 which is zero
`or low and no output will be produced at output 106.
`Where it is desired in accordance with this invention to
`address other than the highest group of memory ad-
`dresses,
`inverters may be utilized between the high
`order portion of the address bus and AND gate 102 in
`order to provide an input at input 110 thereof which
`comprises three logical ones. It will be appreciated,
`therefore, that memory 50 may appear to the processor
`to be any of a number of blocks of memory locations.
`Further, gates 102 and 104 may be configured so that
`memory 50 appears to each of processors 12 and 14 to
`be a different portion of the memory addressable by the
`respective processors. For example, assume that three
`bits of address data are supplied to each of gates 102 and
`104 and assume further that each of the bits applied to
`gate 104 is inverted before being connected to inputs
`112 thereof. It will be appreciated that gate 104 will
`provide an output signal at output terminal 108 thereof
`whenever each of the high order address bits is zero
`rather than one and that memory 50 will appear to
`processor 14 to be the lowest 8000 memory addresses
`and to processor 12 to be the highest 8000 memory
`addresses.
`NAND gates 116 and 118 provide the final connec-
`tion to the bus structure of two processors at outputs
`120 and 122 thereof, respectively. Output 120 is con-
`nected to wait bus 26 and output 122 to wait bus 26’.
`The shared memory of FIG. 2 may be seen to be con-
`nected only to the bus structures of the two portions of
`the multiprocessor microcomputer of FIG. 1. No addi-
`tional control is required and no direct connection is
`made between the two bus structures.
`The operation of the shared memory of FIG. 2 re-
`quires that a number of conditions be satisfied. Memory
`50 may be addressed by either of processors 12 or 14 but
`may not be simultaneously addressed by both. When
`only one processor addresses the memory, the shared
`memory of FIG. 2 gives access to that processor. When
`both processors simultaneously require access to the
`memory that processor which most recently utilized the
`memory is given access. It will be appreciated that a
`request for service by a processor will be evidenced by
`a high output at either of outputs 106 or 108 of gates 102
`and 104. For purposes of discussion, reference will be
`made to “high” and “low” signals. It will be understood
`that these references are to high and low logic level
`signals and do not necessarily refer to specific relative
`magnitudes. Those skilled in the art will recognize that
`high and low respectively refer to logical ones and
`zeros. Assume first that only output 106 of AND gate
`102 is activated to produce a high signal thereat indicat-
`ing that a processor 12 desires access to the memory. A
`high signal appears at output 106 of AND gate 102 and
`simultaneously at input 130 of NOR gate 132, input 138
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`Petitioner Apple Inc. - Exhibit 1021, p. 8
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`Petitioner Apple Inc. - Exhibit 1021, p. 8
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`4,212,057
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`of NAND gate 140 and input 142 of NAND gate 144.
`Since no service is being requested by processor 14
`output 108 of AND gate 104 is low providing a low
`signal to: input 146 of inverter 148, input 150 of NAND
`gate 152 and input 154 of NAND gate 156. Inverter 136
`provides a low signal to input 172 of NAND gate 152,
`output 174 of which will necessarily be high. Output
`174 of NAND gate 152 is connected to input 164 of
`NAND gate 166 and provides a high signal thereto.
`Since input 146 of inverter 148 is low, output 158
`thereof provides a high signal to input 160 of NAND
`gate 140. Since input 138 of NAND gate 140 is also
`high, output 162 thereof is low providing a low signal to
`input 176 of NAND gate 178 which insures that output
`182 thereof is high. Output 182 is connected to input 167
`of NAND gate 166 and since both inputs 164 and 167
`are high, output 168 of NAND gate 166 is low provid-
`ing a low signal to gate inputs 74 and 184 of tri-state
`buffers 62 and 78, respectively. Low logic signals are
`similarly provided to input 190 of tri-state buffer 86 and
`to input 192 of NAND gate 116 which provides a high
`signal at output 120 thereof. It will be recalled that
`NAND gates 116 and 118 are connected to the wait
`buses associated with processors 12 and 14, respec-
`tively. In accordance with this invention, a low signal
`will cause the processor to wait and a high signal will
`allow it to proceed. Accordingly, it will be appreciated
`that tri-state buffer 62 provides connection between
`input 66 thereof and output 70 thereby connecting ad-
`dress bus 18 to input 52 of memory 50. Similarly, input
`82 of tri-state buffer 78 is connected to input 58 of mem-
`ory 50 and input 90 of tri-state buffer 86 is connected to
`input 54 of memory 50. Thus, the appropriate address,
`read/write and data buses are connected to the mem-
`ory. The selective activation of the memory for either
`accepting or providing data therefrom willbe described
`hereinbelow.
`The operation of the shared memory of FIG. 2 when
`service is required by processor 14 alone is similar to
`that hereinabove described and produces a low signal at
`output 182 of NAND gate 178 thereby activating tri-
`state buffers 64, 80 and 88 to provide connection to
`memory 50 of inputs 68, 84 and 92. The operation of the
`shared memory when service is simultaneously required
`by both processors 12 and 14 depends upon which pro-
`cessor has most recently had access to the memory.
`Assume that prior to the simultaneous request for ser-
`vices that a processor 12 has most recently addressed
`the memory. Output 168 of NAND gate 166 will pro-
`vide a low signal while output 182 provides a high
`signal. Assume now that both AND gates 102 and 104
`provide log signals indicating that neither processor
`requires service. A low signal is provided to NAND
`gate 140 while a high signal is provided to input 164 of
`NAND gate 166. Since input 167 of NAND gate 166 is
`connected to output 182 of NAND gate 178 which, it
`will be recalled, is providing a high signal, NAND gate
`166 will remain in its previous state and produce a low
`signal at output 168 thereof. This low signal is con-
`nected to input 180 of NAND gate 178 assuring that a
`high signal continues to be produced at output 182
`thereof. It will be seen that NAND gates 166 and 178
`are connected in a flip-flop circuit relationship and will
`maintain a low and high signal, respectively, at the
`output thereof in the absence of service requests from
`either processor. Assume now that both processors
`require service. Both outputs 106 and 108 will be high
`thus providing high signals to inverters 136 and 148
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`which will, therefore, produce low signals at outputs
`158 and 170, thereof, respectively, which low signals
`will insure that high signals are produced at outputs 162
`and 174 which are coupled to inputs 176 and 164, re-
`spectively. It will be recalled that NAND gate 166 was
`previously in an “on” state producing a low signal at
`output 168 thereof and that NAND gate 178 was pro-
`ducing a high signal at output 182 thereof and it will be
`appreciated that these conditions will continue during
`the simultaneous request for service by both processors.
`The inputs to NAND gate 166 remaining high and
`inputs 180 and 176 of NAND gate 178 being low and
`high, respectively,
`thus producing a high output at
`output 182 of NAND gate 178.
`Assume now that request is made only by processor
`14 and that therefore output 106 is low and output 108
`is high. High signals are applied to inverter 148 and
`input 150 of NAND gate 152. Low signals are applied
`to inverter 136 and input 138 of NAND gate 140.
`NAND gate 140 consequently produces a high signal at
`output 162 thereof while NAND gate 152 produces a
`low signal at output 174 thereof. The low signal appear-
`ing at output 174 of NAND gate 152 is connected to
`input 164 of NAND gate 166 which produces a high
`signal at output 168 thereof which is connected to input
`180 of NAND gate 178. Since output 162 of NAND
`gate 140 is connected to input 176 of NAND gate 178,
`output 182 thereof changes to a low state and processor
`14 is given access to the memory while access is re-
`moved from processor 12.
`It will be appreciated that in accordance with this
`invention as hereinabove described access is given to
`either processor requesting it when requests appear one
`at a time and to the processor most recently having
`access when simultaneous requests are received. In this
`way, neither processor will be interrupted, during a
`transaction with memory, by a request from the other
`processor.
`It is desirable to provide two modes of access to the
`memory, a first mode in which data is read into the
`memory from the processor or another device and the
`second mode wherein data is read out of the memory to
`the processor or the other device. The shared memory
`of FIG. 2 provides the necessary control to provide
`these two modes of access. It will be appreciated by
`those skilled in the art that the nature of electrical con-
`nection to memory 50 in order to accomplish the read
`and write operations is somewhat different. Particu-
`larly, data-out port 56 provides relatively low impe-
`dance signal sources, the logic levels of which deter-
`mine the data supplied by memory 50. It will be appreci-
`ated therefore, that data—out port 56 must be isolated
`from the bus structure of the appropriate processor
`except when it is desired to read data from the memory.
`Data-in port 54 is adapted to receive data from the bus
`structure and is characterized by a relatively high impe-
`dance. It is, therefore, unn