`
`List of Contents and Author Index for Volume 28, 1997, are inserted loose in this issue
`
`Volume 29 Number 6 June 1998
`
`ISSN 0026—2692
`
`Will
`
`
`
`”Ill/Ill!” {
`
`j22753A
`
`MICROELECTRONICS
`
`
`
`JOURNAL
`
`
`
`Pilsl
`
`EDITOR'
`
`
`
`SAMSUNG EX. 1010 -1/10
`
`
`
`y.____.____..___.___________AP..._________
`
`,—
`
`.159
`
`.163
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`.71
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`”81
`
`..C83
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`..291
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`2094
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`

`

`Microelectronics Journal
`
`
`
`Editor-in—Chief: Dr M. Henini, Physics Department, University of Nottingham, Nottingham NG7 2RD, UK.
`Tel/fax: +44 (0) 115 951 5195/5180; e—mail: mohamed.henini@nottingham.ac.uk
`
`I. HERNANDEZ—CALDERON
`
`Centro de Investigacion y de Estudios
`Avanzados, Mexico
`
`M.H. OH
`KIST
`Seoul, Korea
`
`Editorial Board
`
`J. ALDERMAN
`University College
`Cork, Ireland
`
`A. BENSAOULA
`
`University of Houston
`Texas, USA
`
`P.M. CAMPBELL
`
`Naval Research Laboratory
`Washington, DC, USA
`D. GALE
`
`Queen’s University
`Kingston, Ontario, Canada
`T.K. GAYLORD
`
`Georgia Institute of Technology
`Atlanta, GA, USA
`
`_
`,
`M. GREEN
`University of New South Wales
`Sydney, Australia
`
`_H.B. HARIKISON
`Griffith University
`Brisbane, Australia ‘
`
`H. HASEGAWA
`
`Hokkaido University
`Sapporo, Japan
`M.R. HASKARD
`
`S. EJAZ HUQ
`Rutherford Appleton Laboratmy
`Chilton, Didcot, UK
`
`J.—M. KARAM
`TIMA/CMP
`Grenoble, France
`
`JR. LEITE
`Universidade de S510 Paulo
`Sao Paulo, Brazil
`D. LIPPENS
`
`Université des Sciences et Technologies
`de Lille
`
`Villeneuve d’Ascq, France
`C.—Y. LU
`
`Vanguard International
`Semiconductor Corp.
`Hsinchu, Taiwan, ROC
`S. MATSUI
`
`NEC Corp.
`Tsukula, Ibaraki, Japan
`A.D. MILNE
`Wolfson Microelectronics Ltd.
`
`P. PANAYOTATOS
`
`Rutgers University, Piscataway, 1‘ 'J, USA
`and Institute of Electronic Structure and
`Lasers, Heraklion, Greece
`
`A. RUDRA
`
`Ecole Polytechnique Federale de Lausanne
`Lausanne, Switzerland
`
`Y. SHIRAKI
`
`University of Tokyo
`Tokyo, Japan
`
`N.D. STOJADINOVIC
`University of Nis
`Nis, Serbia
`
`C. VAN HOOF
`IMEC
`
`Leuven, Belgium
`
`SF. YOON
`
`Nanyang Technological University
`Singapore
`
`Edinburgh, UK
`H.Z. ZHENG
`P. O’LEARY
`Academia Sinica
`Montanuniversit'at Leoben
`University of South Australia
`Beijing, China
`The Levels, Australia
`Leoben, Austria
`
`
`
`
`
`
`
`
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`please contact the Author Service Department: e—mail: authors@elsevier.co.uk; fax: +44 (0) 1865 843905; tel.: +44 (0) 1865 843900.
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`© 1998 Elsevier Science Ltd. All rights reserved.
`
`SAMSUNG EX. 1010 - 21/10
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`

`

`VOLUME 29 NUMBER 6
`
`CONTENTS
`
`B‘IDEEH67HSB
`
`Hll
`
`
`
`
`
`l
`l
`
`b89065487456a‘m
`
`Refereed Papers
`Differential sheet resistivity of mixed implanted (phosphorus + boron) silicon
`A. Kumar, G.S. Virdi, PJ. George, S.K. Chattopadhyaya and N. Nath ............................................. 299
`The VESA generalized timing formula
`A. Morrish ................................................................................................................................ 307
`
`A quantitative analysis ofwiring lengths in 2D and 3D VLSI
`A. Milenkovic and V. Milutinovic ................................................................................................ 313
`Application of byte error detecting codes to the design of self—checking circuits
`S. Pagey and AJ. Al—Khalili ......................................................................................................... 323
`Kinetics of oxidation of copper alloy leadframes
`S.K. Lahiri, N.K. Waalib Singh, KW. Heng, L. Ang and LC. Goh3‘3
`Chip on glass—interconnect for row/column driver packaging
`R. Joshi .................................................................................................................................... 345
`Book Reviews ................................................................................................................................. 3' l
`Patents/ILERT ................................................................................................................................. 367
`
`llllllll
`
`
`
`
`|||l|
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`0026-2692(1998)29:6;1-I
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`
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`lllllll Illlllllllllll
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`
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`02094
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`
`
`PII:50026-2692(97)00071—2
`
`Microcler'lrnnirzr Journal 29 ([998) 343—349
`Cr 1998 Elsevier Science Limited
`Printed in Great Britain. All rights reserved
`0026—2692/98/$l9.00
`
`Jadedpeeieiea
`
`Chip on
`glass—interconnect
`for row/column
`driver packaging
`
`Rajeev Joshi*
`
`National Semiconductor Corporation, 3707 Tahoe Way, Salim Clara, CA 95051, USA
`
`
`
`New liquid crystal active matrix color flat panel displays
`and super twisted nematic liquid crystal displays and other
`flat
`panel
`displays
`are
`driving
`new interconnect
`technologies
`to make low cost,
`thin, compact, mass
`terminations with high resolution capabilities. Chip on
`glass (COG) and flip chip on glass (FCOG) are being used
`to mount
`the driver IC directly on to the glass LCD.
`FCOG and COG offer the highest density possible in
`packaging. Several
`interconnect
`technologies in FCOG/
`COG have been developed; their strengths and weaknesses
`are discussed in this paper. The challenges for COG
`adoption are also discussed. © 1998 Elsevier Science Ltd.
`All rights reserved.
`
`1. Introduction
`
`he liquid crystal display (LCD) market
`can be considered to be a large applica—
`tion of the flip chip market
`in the form of
`chip on glass
`(COG).
`It
`is estimated that
`about 60% of the displays use tape automated
`bonding (TAB) technology. In Japan, COG is
`typically used for LCDs
`that
`are under
`6inches
`in
`size.
`Figure
`1
`gives
`typical
`adoption rates for COG as a function of the
`panel size.
`
`(408) 721—4326. Fax:
`*Tel:
`trajsc@ptg.nsc.com.
`
`(408) 746—2007. E—mail:
`
`For display driver IC to glass interconnect, a key
`requirement of the process is that it should be
`low cost, manufacturable and reworkable.
`
`Several methods have been used historically to
`interconnect driver
`ICs
`to the glass. For
`example, conventional packages
`like a
`thin
`quad flat package (TQFP) on a printed wiring
`board, which in turn is connected to the glass
`using flex. A fine pitch chip on tape package
`like the tape carrier package (TCP)
`is also
`currently used. The outputs of the driver IC
`on the TCP are connected to the glass using
`anisotropic conductive epoxy.
`In COG,
`the
`bare
`(unpackaged) driver
`ICs are mounted
`directly on the glass panel. Thus, COG has
`the potential of using the most
`simplified
`assembly process
`flow and as
`it does not
`involve the use of a conventional package (like
`TCP),
`it can be a low cost
`interconnection
`method.
`
`One method to connect the mounted die is by
`wire bonding the IC to the metallization on the
`glass.
`In this method,
`the interconnects are
`made to the inetallization one bond pad at a
`time. This method is also not very efficient in
`
`343
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`

`

`R. Joshi/Chip on glass
`
`supporting high density or fine pitch intercon—
`nect,
`though it
`is an inexpensive and mature
`interconnect method in the industry.
`
`An alternative interconnect process is flip chip
`on glass (FCOG). FCOG is a system level inter—
`connect and should be treated as such.
`
`From Table 1
`
`the method that uses modified
`
`stud
`is
`equipment
`assembly
`conventional
`bumping, which eliminates the need for lith—
`ography and associated mask costs. The most
`common method, however, for COG,
`is
`the
`use of adhesives for accomplishing the intercon—
`nect. Figure 2 gives the process flow for these
`two processes.
`
`
`
`2. COG
`
`Several methods exist for attaching bare driver
`ICs on to glass. A review of their technologies
`along with their key attributes is given in Table
`l .
`
`Two types of adhesive processes exist: one
`where the epoxy which facilitates electrical
`contact between the bump and the trace metalli—
`zation without itself being in the conduction
`path, as
`in UV curable resins, or are in the
`
`Stud Ball
`
`Anisotropic
`Conductive
`
`Micro Bump
`Bonding (UV
`
`Conductive
`Particle
`
`Film (ACF)
`
`,
`
`JGW‘Qi Au bump
`T 4
`0,0?
`lGlass:
`
`Conductive
`particle in
`ACF
`
`\Conductive
`paste
`
`Conductive particle
`
`Interconnect
`
`Conductive Paste
`
`ACF
`
`IC Electrode
`. Conductor 0n
`Substrate
`
`Ausauonmad
`ITO
`
`ITO
`
`None
`
`IT
`
`0
`
`Conductive
`Particle
`A1 Pad
`
` 20 50 g/pad
`
`150-200
`(recent work
`shown up to 40
`micron)
`
`160 180 C
`
`Pitch(u1n)
`
`60-130
`
`Bond Temperature
`Bond Pressure
`Cure Method
`
`100-120 c
`1- Cy/pad
`
`Benefits
`
`Drawbacks
`
`underfill
`- Flexible
`
`bumping method
`- low capital
`-one at a time
`
`bumpmg
`
`lO-20 g/pad
`
`150—200 c
`10—20 g/pad
`
`-Low cost
`High thru‘put
`
`-No bumps
`needed
`
`.
`
`—Unreliable
`connection with
`A1
`
`344
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`
`
`Microelectronics Journal, Vol. 29, No. 6
`
`
`
`}
`Application
`‘
`1995
`_1996
`1997
`|
`1998
`
`85%
`l
`100%
`‘Character LCD i . ——
`
`‘
`50(7
`1007
`20%
`D
`D
`
`10%
`30%
`
`
`
`
`
`4-6" Panels
`
`Large panel (7"+)
`
`
`
`
`
`‘
`
`E
`
`
`
`70%
`
`with the bumps on the die and with the traces
`on
`the
`substrate. The
`interconnection is
`
`retained by the compressive force between the
`electrode surfaces due to the shrinkage of the
`epoxy after
`curing. During bonding,
`the
`adhesive
`resins
`are
`squeezed out
`and the
`conducting particles are trapped between the
`conductor
`surfaces. Consequently,
`electrical
`conduction is
`restricted to the Z—direction
`while electrical
`isolation is maintained in the
`
`xy plane. Conduction can be accomplished in
`several ways: using metal particles such as Ni—
`or In—based alloys or gold coated resin particles
`which are more compliant
`than the former.
`Using the latter, one could obtain an ohmic
`contact carrying current up to 2000 111A per
`bump with as low an interconnect resistance
`as
`31119
`[5]. Typically,
`the
`resins
`that
`comprise the ACF are thermoplastic,
`ther—
`moset or a mixture of both. While the advan—
`
`tages of a thermoplastic adhesive are superior
`reworkability and pot life, they do not have as
`good adhesive properties as
`thermosets. The
`technology has been extended to apply to fine
`pitch bonding (<40 um) using a ‘double sided
`ACF’ concept [7], where an unfilled top layer
`
`1116
`
`cal
`lli—
`.on
`
`the
`
`Fig. l. COG adoption roadmap.
`
`(anisotropically)
`conduction path as in Z—axis
`conductive adhesives. Both these systems have
`been well documented by researchers [2~6]. In
`the former, an acrylic resin is used which
`shrinks after cure forming a bond between the
`bumps and the substrate metallization. There
`are some issues with this form of interconnect:
`
`chip to glass coplanarity and the Z—axis adhesive
`growth due to thermal expansion. In the latter
`the adhesive itself is in the conduction path of
`the two electrodes.
`
`The
`
`issues of
`
`the UV cured resins
`
`are
`
`overcome in the anisotropic conductive film
`(ACF)
`technology.
`Conductive
`particles
`(metallized resin balls) are dispersed in ACF
`with the conductive particles making contact
`
`(a)
`
`UV-cured
`insulaling resin
`
`
`
`UV “Edi-“i"
`
`
`Pads
`
`Substrale
`(PCB. glass. elc.)
`
`m wm—
`A'Wm —
`
`Non-transparent substrate
`Transparent substrate
`Pressure tool
`Pressure applicalion
`and UV illuminalion
`
`
`
`
`Curing complete
`(remove heal)
`
`LSI pad
`UV~wred
`insulating
`resin
`
`
`z
`Substrate
`
`(b)
`
`DICING
`|
`Z-AXIS CONDUCTIVE EPOXY FILM
`PANEL PREPARATION
`
`(ACF)
`
`|
`ATTACHMENT TO PANEL
`1
`
`DIE ALIGNMENT TO PANEL
`|
`PREBONDING, TESTING
`|
`CURING
`
`l
`FINAL TEST/ SHIPMENT
`
`I
`
`Fig. 2.
`
`(A) Process flow using UV cured resin. (B) Process flow for COG using ACF.
`
`345
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`

`
`
`*Re
`
`Re(
`bee
`
`For
`leas
`the
`Son
`hov
`tent
`
`dept
`saiy
`size
`
`3. 4.
`Sele
`
`pro<
`
`
`
`i
`
`i
`
`iI
`
`i
`
`/ -— Output Side
`
`/
`//
`
`unuuuuu’bun nuuuuunnuunuu
`
`uuuuq‘iuuuu Duuuuuuuuuuuu DUDDDUDDDD
`
`+UD
`
`DD
`
`[Jig
`DD
`\,
`
`[113 Bi]
`
`DU
`
`InputSide
`
`
`i
`
`DE]
`
`GU
`
`DE
`
`DE]
`
`DD
`
`DI]
`
`DU+
`
`In Line Bump Layout
`
`R. Joshi/Chip on glass
`
`of the adhesive film faces the bumps and adds
`additional
`insulation between bumps due to
`its flow properties during bonding.
`
`One issue about FCOG using ACF is that the
`die does not self—align as in conventional solder—
`based flip chip,
`thus requiring excellent align—
`ment capabilities of the bonding equipment [8]
`
`3. COG die requirements
`
`’
`
`,I”— Output Side
`
`i
`i
`
`i L
`
`The mechanical layout of the die should enable
`easy implementation of COG.
`
`
`
`,/
`nnnnnunnnuu
`"
`_
`n
`'Jnfln LiningI iflian n‘jt ’t"u uLuaulinEugnDnUu u u u u u u u D n n
`
`3.1. bump
`Bump area should be maximized to facilitate
`connection with as large a number of conductive
`particles as possible. However, in doing this one
`should also consider
`that
`a certain spacing
`between adjacent bumps needs to be maintained
`(approximately three times the average conduc—
`tive particle size in the ACF) to ensure good
`insulation resistance between bumps. Two
`approaches are possible: an in—line bump pattern
`and a staggered bump pattern as shown in Fig.
`3. Since one of the objectives of COG is to save
`as much space on the viewing glass as possible,
`an orthogonal
`trace layout with respect
`to
`bumps is preferred, hence active bumps on the
`die width (shorter side) of the driver le are not
`preferred as they can lead to non—optimum fan—
`out patterns of the ITO traces. Bump metalliza—
`tion traditionally has been plated up 100% Au,
`though a less expensive method of metallization
`using electroless nickel has been reported to
`have been used with good results [9]. Good
`bump uniformity is required and typical
`top
`surface uniformity of the order of a third of the
`particle size of the ACF is needed so as mechani—
`cally to entrap conductive particles between the
`bump and the metallization trace.
`
`3.2. Die size
`
`Although the use of an ACF does enable some
`stress relief due to coefficient of thermal expan—
`sion mismatch, it is still a concern. Delamination
`
`346
`
`l+UD
`
`DU
`
`UQ
`[1E1
`\,
`
`CID
`
`UD
`
`inputSide
`
`
`DD‘
`i
`
`[JD
`
`DEI
`
`CID
`
`DU
`
`DU
`
`[JD
`
`DD+
`
`Staggered Bump Layout
`
`Fig. 3. Bump layouts for COG.
`
`and tensile stress cracking have been reported
`under Mil Std 883 Schedule B thermal cycling
`for assemblies made with Z—axis epoxies [10].
`
`In addition, especially at fine pitch, there is an
`even greater danger of cumulative misalignment
`between the bumps and the traces during
`bonding. Most COG bonders place an upper
`limit of 20mm on the die length for these
`reasons.
`
`3.3. COG adhesives
`
`As summarized in Tables 1 and 2, using a UV
`cured adhesive typically results in a difficult to
`rework process flow and also, by the nature of
`the Chemistries of the materials used in the resin
`
`there are concerns of electrical
`manufacture,
`instability in accelerated temperature, humidity
`and bias tests. The UV cured bonding process is
`fast and occurs at a low temperature resulting in
`less stress on the die and fewer issues of misalign—
`ment due to difering coefficients of expansion.
`
`
`
`SAMSUNG EX. 1010 - 7/ 0
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`

`_..,._
`
`Microelectronics Journal, Vol. 29, No. 6
`
`Bonding
`
`Fllp Chip
`
`Wire
`
`Metallization
`
`PbSn bump
`
`LSl
`
`Solder Paste
`
`Cu bump
`
`LSI
`
`Low Melting Point
`Metal
`
`
`in alloy
`LSI
`
`
`
`
`Glass or
`9""
`
`Metallization
`
`Au or In
` Mataliization
`
`no
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`LS! Electrode
`
`Conductor on
`substrate
`
`Bum Pitch
`
`Bonding
`Temperature
`
`Bonding Pressure
`
`
`
`
`
`
`
`
`
`Au or Al wire m In alloy
`Al pad
`Pia/Sn bu =-
`I Au/in bum
`
`Au, Al
`
`min. 150nm
`
`150°C
`
`Au. Cu. Ni, or W
`
`200~300 m
`
`300~350°C
`
`Al, Au, or lTO
`
`50~150um
`ambient-'1 50°C
`
`_ ~209/pad
`
`Cu/Au bump
`
`lTO. Cu. or Au
`
`150~200 m
`80~120°C
`
`1~2glpad
`
`0K
`
`
`- testableic
`- uses current equipment
`-
`low cost
`
`
`
`- reiiowable bumps
`. no bumps
`low pressure bond
` -
`
`- Reliabte at liquid
`
`
`
`nitro en temps.
`
`- high temp. connection
`- peripheral pads oniy
`-
`indium bumps are
`- gross pitch
`
`
`
`
`
`difficult to form
`
`
`-
`low yield iorhign l/Os
`- solder iailgue
`.
`low control of paste
`
`
`spread
`
`
`- low temp. bonding
`
`*Repairability not good after underfill
`
`Recently, a UV curable, reworkable adhesive has
`been reported [11].
`
`For ACF adhesives it is recommended to use at
`least a minimum film thickness of about 80% of
`
`the bump height in order to minimize voiding.
`Some work has been done on fast cure ACF,
`however rework of these films is difficult as they
`tend to be thermoset adhesives.
`In addition,
`depending on the bump spacing it may be neces—
`sary to select an adhesive with a specific particle
`size as well as either a single or a double layer ACF.
`
`3.4. COG equipment
`Selection of COG equipment depends on the
`process used in bonding the die to the substrate.
`
`accuracy,
`bonding
`accuracy,
`Alignment
`handling systems for both the substrate and the
`adhesives, process zones (bonding stages and
`rework stages), throughput and cost are some of
`the key attributes that need to be considered.
`
`4. Other COG technologies
`
`Resin and flexible metal bumps have been
`studied [10,12] as a means of achieving good
`thermal cycle reliability and rework at
`fine
`pitch. In one method, a polymer bump is plated
`with gold to form a compliant polymer bump
`[10] using either a dry etch, wet etch or photo—
`imagible process. This method still would
`require an adhesive for connection to the traces,
`
`347
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`int
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`

`R. Joshi/Chip on glass
`
`but being compliant would absorb the mismatch
`more readily. In the other method, a new photo—
`thermosetting resin was developed which can
`adhere to a substrate and flexible indium bumps
`on the bond pad of the resin. The photoimagible
`thermosetting resin takes
`the place of the
`adhesive in the previous approach.
`
`5. COG adoption
`
`From a driver IC manufacturer’s view point
`COG implementation is positive as it enables a
`faster and lower cost design turn (eliminating
`TCP tape tool—up time and expenses); however,
`there are some barriers to an easy adoption of
`COG for large panel size displays. Some key
`barriers to COG adoption are: the lack of ease
`of rework during assembly as well as during
`field repairs. While this may not be a critical
`issue for small panel size low resolution displays,
`it is a concern for large panel size displays which
`often use several row and column driver ICs. In
`
`addition, there is a need to invest in new equip—
`ment to assemble COG devices with a probably
`lower throughput as compared to the conven—
`tional TCP row and column driver ICs. The
`
`perception ofa larger than TCP ‘dead space’ for
`COG versus the TCP (flex) package has not
`helped in facilitating a quick adoption. The
`interconnect resistance of the COG intercon—
`
`nect has been a concern, especially for large
`high resolution panels, but with new adhesive
`technology available it has approached that of
`the TCP package.
`
`With high resolution driving pixel size, outer
`lead pitch bonding is likely to shrink and with
`IC manufacturers shrinking their die sizes to
`meet
`the cost
`targets
`the inner
`lead pitch
`bonding is likely to shrink as well. For high res—
`olution displays with fine pixel size there is a
`possibility of greater misalignment between the
`TCP outer leads and the substrate metallization
`
`traces. Below 50 ,um inner lead pitch bonding
`there are concerns about TCP lead strength,
`cost, especially for the flex tape, and at which
`
`348
`
`[8
`
`point COG will be a compelling interconnect
`technology for large panels. The emerging tech—
`nology in the area of repair/rework of COG
`both during bonding and in field service is an
`exciting one and should benefit
`the industry
`upon its maturity.
`
`6. Conclusion
`
`Key COG technologies have been reviewed
`with their attributes. Factors that need to be
`
`implementing
`considered when designing or
`COG with respect
`to the driver IC and the
`materials and equipment have been discussed.
`Hindrances to COG adoption for large panel
`size displays have been discussed at length as
`well as when COG could become a compelling
`system interconnect
`technology of choice for
`LCD displays.
`
`References
`
`[‘1] Worldwide Developments in Flip Chip Interconnect,
`A multi
`client
`study, Techsearch International,
`February 1994.
`[2] N.R. Basavanhally, D.D. Chang, B.H. Cranston and
`S.G. Seger, Direct chip interconnect with adhesive
`connector films, Prat. 42nd Elctrrouit Components and
`Tetlmology Calif, San Diego, CA, USA, 1992.
`[3] W. Takakahashi, K. Murakoshi, ]. Kanazawa, M.
`Ikehata, Y. Iguchi and T. Kanamon, Solderless COG
`technology rising anisotropic conductive adhesives,
`IMC 1992 Pi'orcediugs, Yokohama, japan, 1992.
`I. Watanabe, N. Shiozawa, K. Takemura and T.
`Ohta, Flip chip interconnection technology rising
`anisotropic conductive adhesive films, in]. Lau (ed).
`Flip Chip Tet/mology, McGraw—Hill, New York.
`1996.
`
`[4]
`
`I. Tsukagoshi and T. Ohta,
`[5] N. Shizoawa, K. Isaka,
`Role of conductive particles on anisotropic conduc—
`tive films used for high density connection, HimL'Ili
`C/Iemiml Cir, Tat/mini] Report, I994.
`[6] K. Hatada and H. Fujimoto, A new LSI bonding
`technologyimicron bump bonding technology.
`Prat.
`38f]! E/ctfronit Compmlcnrs
`and Ter/Iilology
`Con/i, Houston, TX, USA, 1989.
`[7] H. Hirosawa, I. Tsukagoshi, H. Matsuoaka, I. Wam—
`nabe, K. Takemura, N. Shiozawa and T. Ohta.
`Double—layer anisotropic conductive adhesive films.
`”[995 Display IVIaiIigfiitfur/Hg Tr’c/Iiiolqu Conf, Digest Qf
`
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`

`
`
`Microelectronics Journal, Vol. 29, No. 6
`
`[8]
`
`[9]
`
`Tet/Iniml Papers, Society for lnfonnation Display, Vol.
`2,
`'1995.
`CC. Wong, Flip chip conection technology, in D.A.
`Doane and P.D. Franzon (eds), A/[iiltirln'p lVlodn/e
`Technologies and Alternatives, Van Norstrand Reinhold,
`New York, 1993, pp. 429—449.
`R. Aschenbrenner, A. Ostmann, G. Motulla, K.F.
`Becker, E. Zakel and H. Reichl, Flip chip inter—
`connection to glass
`substrates using anisotropic
`adhesives and electroless nickel bumps, Prot. Adhe—
`sives
`in Elettronits
`’96, Stockholm, Sweden, june
`1996.
`
`[10] K. Keswick, R. German, M. Breen and R. Nolan,
`Compliant bumps for adhesive flip chip assembly,
`Pror. 44th Elertronir Components and Tet/inology Con/j,
`Washington, DC, USA, May '1994.
`T. Angelucci and]. Alpcter, Flip chip on glass (COG)
`assembly using Z—axis (ACA) adhesive technology,
`Elettronirs Prodnrtion Fair, Stockholm, Sweden, May
`1996.
`
`['11]
`
`[Q
`
`K. Matsui, K. Utsumi, H. Ohkubo and C. Sugitani,
`Resin and flexible metal bumps for chip on glass
`technology, Pror. 43rd Elettronit Components and Tet/1—
`no/ogy Confi, Orlando, FL, USA, May 1993.
`
`
`
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`)hta,
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`
`349
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`SAMSUNG EX. 1010 -10/10
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`SAMSUNG EX. 1010 - 10/10
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