IPR2015-00862
`Petition for Inter Partes Review of U.S. Patent 7,202,843 - EXHIBIT 1010_Page 1
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`Petition for Inter Partes Review of U.S. Patent 7,202,843 - EXHIBIT 1010_Page 1
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`Page 2
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`Copyright © 1996 by Iohn Wiley 8: Sons Ltd.
`Baffins Lane, Chichester,
`West Sussex PO19 1UD, England
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`National
`International
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`01243 779777
`(+44) 1243 779777
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`All rights reserved.
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`No part of this book may be reproduced by any means,
`or transmitted, or translated into a machine language
`without the written permission of the publisher.
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`Other Wiley Editorial Ofiices
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`John Wiley & Sons, Inc, 605 Third Avenue,
`New York, NY 10158-0012, USA
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`Iacaranda Wiley Ltd, 33 Park Road, Milton,
`Queensland 4064, Australia
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`John Wiley 8: Sons (Canada) Ltd, 22 Worcester Road,
`Rexdale, Ontario M9W 1L1, Canada
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`John Wiley & Sons (Asia) Pte Ltd, 2 Clementi Loop #02-01,
`]in Xing Distripark, Singapore 0512
`
`Library of Congress Cataloging-in-Publication Data
`Prince, Betty.
`High performance memories / Betty Prince.
`p.
`cm.
`Includes bibliographical references and index.
`ISBN 0 471 95646 5
`1. Semiconductor storage devices.
`circuits.
`1. Title.
`TK7895.M4P68
`621‘ . 39'732—dC20
`
`1996
`
`2. Very high speed integrated
`
`95-25742 CIP
`
`British Library Cataloguing in Publication Data
`
`A catalogue record for this book is available from the British Library
`ISBN 0 471 95646 5
`
`Typeset in 10/ 12pt Palatino by Keyword Typesetting Services Ltd., Wallington, Surrey
`Printed and bound in Great Britain by Bookcraft (Bath) Ltd.
`This book is printed on acid—free paper responsibly manufactured from sustainable forestation,
`for which at least two trees are planted for each one used for paper production.
`
`Page 3
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`Page 3
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`
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`Acknowledgements
`
`About the author
`
`Introduction
`
`1 Overview of High Speed Memories and Memory Systems
`1.1 Overview of Fast Memory Trends
`1.2 New Memory Architectures to Improve Bandwidth
`1.3 Memories in Computer Systems
`1.3.1 Cache SRAMS
`1.3.2 DRAMs in High Performance Main Memory
`1.3.3 DRAMs in Graphics Subsystems
`1.4 Effect of Electrical System Characteristics on Speed
`1.5 Effect of Packaging on Speed
`Bibliography
`
`2 High Performance Memory Applications
`2.1 The Concept of a High Performance Memory
`2.2 System Architecture Determines Performance
`2.3 Systems Applications for High Performance SRAMS
`2.3.1 Overview of Fast SRAM Applications
`2.3.2 Systems with Fast Caches
`2.3.3 Synchronous and Asynchronous SRAMS in Fast Caches
`2.3.4 Cache Size and Speed Requirements of Computer Systems
`2.3.5 SRAM Use Based on Processor Speed
`2.4 Overview of Applications for High Performance DRAMs
`2.5 Main Memory Applications for DRAMs
`2.5.1 Mainframe and Supercomputer Applications
`2.5.2 DRAMs in Main Memory in Workstations
`2.5.3 DRAMs in Mai.n Memory in PCS
`2.5.4 DRAMs in‘Add-On Modules for Main Memory
`2.6 DRAMs in Graphic Subsystems
`2.6.1 Television Displays
`2.6.2 DRAMs in Television Related Applications
`2.6.3 Graphics DRAMs in Computer Graphics Subsystems‘
`2.6.4 Frame Buffer Operations to lrnprove Bandwidth
`2.7 Peripheral Applications for DRAMs
`2.7.1 Printers
`
`2.8 Consumer Applications for Fast DRAMs
`2.8.1 Fast DRAMs in Consumer Games
`2.9 Communications Applications for DRAMs
`
`xi
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`xiii
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`xiv
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`Page 4
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`vi
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`Contents
`
`2.9.1 Digital Switching Systems
`2.10 Emerging Communications Applications
`2.10.1 Video Conferencing and Interactive TV Equipment
`2.10.2 ATM Switches
`2.10.3 Digital Compression
`2.10.4 Mobile Communications
`2.11 Industrial Applications for DRAMS
`2.11.1 Medical Systems
`2.11.2 Embedded Controllers
`Bibliography
`V
`
`~
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`3 Fast SRAMS
`3.1 Overview of Fast SRAMS
`3.2 Fast SRAM Technology
`3.3 Architectural Influence on SRAM Speed
`3.3.1 Separate and Common Inputs and Outputs
`3.3.2 Output Enable
`3.3.3 Wide Bus SRAMS for Bandwidth Improvement
`3.4 Fast Technologies
`3.4.1 BiCMOS Technology for Speed
`3.4.2 GaAs Technology for Speed
`3.5 Effect of Lower Power Supply Voltage on Speed
`3.6 Effect of Temperature on Speed
`3.7 Revolutionary Pinout for Speed
`3.7.1 Revolutionary Interface on ECL SRAMS
`3.8 Latched and Registered SRAMs
`3.8.1 Overview
`3.8.2 Latches
`3.8.3 Registers
`3.8.4 Synchronous (Registered) SRAM with Separate I / O Option
`3.9 FlFOs
`Bibliography
`
`4 Fast Cache Memory
`4.1 Overview
`4.2 Cache Concept and Theory
`4.2.1 The Problem
`4.2.2 Supplying Data from DRAM Main Memory
`4.1.3 Supplying Data from a Cache Hierarchy
`4.3 Effective Speed of the Cache Hierarchy
`4.4 First Level Cache
`4.5 Limitations in Size of an L1 Cache
`4.6
`Increasing the Hit Rate of the Cache: Cache Theory
`4.6.1 Simple Cache Theory
`4.7 Cache Architecture
`4.7.1 Principles of Locality of Time and Space
`4.8 Data and Instruction Caches
`4.9 Cache Associativity
`4.9.1 Direct Mapped Cache
`4.9.2 N-Way Set Associative Cache
`4.9.3 Content Addressable Memory
`4.10 Dual-port Caches
`
`.
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`Page 5
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`4.14.4 Pipelined Burst SSRAMS
`4.15 Use of Parity in Caches
`Bibliography
`
`5 Evolution of Fast Asynchronous DRAMs
`5.1 Overview
`5.2 Basic DRAM Operation
`5.3 Early Speed Improvements
`5.3.1 Nibble Mode
`5.3.2 Wide I/O
`5.4 Special Access Modes
`5.4.1 Page Mode
`5.4.2 Fast (Enhanced) Page Mode
`5.4.3 Static Column Mode
`5.4.4 Fast Page with EDO (Hyperpage)
`5.4.5 Hyperpage Mode with Output Enable Control
`5.4.6 Hyperpage Mode with Write Enable Control
`5.4.7 Burst Mode with EDO
`5.4.8 Pipeline Burst EDO
`5.5 Technology Speed Trends
`5.6 Other Factors in DRAM Speed
`5.6.1 Access Time vs. Power Supply Voltage
`5.6.2 Low Temperature Operation for Speed
`5.6.3 Demultiplexed Addressing
`5.6.4 BiCMOS DRAMs for Speed
`5.7 Early Experiments in High Speed
`Bibliography
`
`6 New Architectures for Fast DRAMs
`6.1 Overview
`‘
`6.2 Synchronous Interface on DRAMs
`6.3 High Speed Modes on Synchronous DRAMs
`6.4 Pipelining on Synchronous DRAMs
`6.5 Prefetch Architectures in Synchronous DRAMs
`6.6 Combinations of Pipelining and Prefetch
`6.7 Multiple Internal Banks
`6.8 Overview of Types of Synchronous DRAMs.
`6.9 The Early 16M JEDEC SDRAMS
`6.9.1 Features
`6.9.2 New Pin Function Descriptions
`6.10 Architecture of IEDEC SDRAMS
`6.10.1 Synchronous and Registered Inputs and Outputs
`
`'
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`Page 6
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`Page 6
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`viii
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`Contents
`
`6.10.2 Multiple Internal Banks
`6.10.3 Output Structure
`6.11 Operational Features of IEDEC SDRAMS
`6.11.1 Mode Register
`6.11.2 Burst Mode Access
`
`6.11.3 CAS Latency
`6.11.4 Chip Select Latency
`6.12 Operational Functions of the SDRAM Truth Table
`6.12.1 SDRAM Truth Table
`
`6.12.2 Auto-Precharge
`6.12.3 External Precharge Timing for Reads
`6.12.4 Write Latency
`6.12.5 DQM Latency for Reads
`6.12.6 DQM Latency for Writes
`6.12.7 The 2—N Rule
`
`6.13 Refresh and Power Down on the IEDEC SDRAM
`6.13.1 Auto-refresh Function
`6.13.2 Self Refresh
`6.14 Power Down and Clock Enable
`6.14.1 Clock Enable
`6.14.2 Power Down
`
`6.14.3 Clock Suspend
`6.15 A State Diagram for the JEDEC SDRAM
`6.16 Power On Sequence for the IEDEC SDRAM
`6.17 Interface Options for the IEDEC SDRAM
`6.18 64M SDRAMS — A New Generation of SDRAMS
`
`6.19 Early 256M SDRAMS
`6.20 Trends in SDRAM Characteristics
`6.21 Cache DRAMS
`6.21.1 Introduction
`6.21.2 The Enhanced DRAM
`
`6.21.3 Synchronous Burst EDRAM
`6.21.4 The CDRAM
`6.22 Protocol Based DRAMS
`
`6.22.1 The Synclink DRAM
`6.22.2 Protocol Based DRAM from Rambus, Inc.
`Bibliography
`
`7 Graphics DRAMS
`7.1 Overview of DRAMS for Graphics Subsystems
`7.2 Frame Memories for Television Applications
`7.2.1 Simple Serial Field Memory for Temporary Frame Storage
`7.2.2 Serial DRAM for High Definition TV Frame Storage
`7.3 Single Port A-synchronous DRAMs for Graphics Applications
`7.3.1 Wide DRAM for Unified Memory in Low End PC
`7.3.2 Wide DRAM for High Speed Printer Graphics
`7.4 Graphics Features on Asynchronous Single Port DRAMS
`7.4.1 Write-Per-Bit
`7.4.2 Persistent Write-Per-_Bit
`
`7.5 Synchronous Single Port DRAMS Used in Graphics Systems
`7.5.1
`4M Synchronous Graphics DRAMs
`7.5.2
`8M SGRAMS
`
`7.6 Special Graphics Features on SGRAMS
`
`Page 7
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`149
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`Page 7
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`
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`7.9.2 Multiple bank DRAM from Mosys
`7.10 Overview of Mu1ti—Port Graphics DRAMs (VRAMS)
`7.11 An Introduction to VRAMs, the 4M VRAMS
`7.12 RAM Operations
`7.12.1 Extended Read and Write Mode
`7.12.2 Random Port Mask Functions
`7.12.3 Flash Write
`
`7.13 Transfer Operations between the RAM and SAM
`7.13.1 256><16 SAM
`7.13.2 512><16 SAM
`
`7.14 SAM Operation
`7.15 Video DRAM Standards and Market
`7.16 8M Video DRAM
`
`7.16.1 Samsung "Window RAM”
`7.17 8M and 16M Synchronous VRAMS
`7.18 Triple Port VRAM
`7.19 VRAMs with z-buffers
`7.19.1 3D-RAM
`
`7.20 Integrated Frame Buffers
`Bibliography
`
`8 Power Supply, Interface, and Test Issues
`8.1 Different Voltages in the System
`8.2 Fast Interfaces
`8.2.1 Established Interfaces
`
`8.2.2 Newer High Speed Interfaces
`8.2.3 True Differential Interfaces
`
`8.3 Difficulties in Specification of High Speed Components
`8.3.1 Testing High Density Memories
`8.3.2 Testing with Boundary Scan
`8.3.3 Testing High Speed RAl\/Is
`8.3.4 Power and Heat Management
`Bibliography
`
`9 Fast Packaging Techniques
`9.1 Fast Memory Component Packaging
`9.2 Packages for Fast DRAMS
`9.2.1 Trends to Smaller Sizes in Commodity DRAM Packages
`9.2.2 Reverse Pinout Packages for Double-sided Modules
`9.2.3 Vertical DRAM Packages
`9.2.4 Speciality DRAM Packages
`9.3 DRAM SIM and DIMM Modules
`
`212
`212
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`Page 8
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`Page 8
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`276
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`X
`
`Contents
`
`8/9-Bit SIMM Module
`><32 SIMM Modules (72-Pin SIIVIM)
`Small Outline 72-Pin DIMMS
`
`9.3.1
`9.3.2
`9.3.3
`9.3.4
`9.3.5
`
`168-Pin 64 / 72-Bit (8-Byte) DRAM DIMM Module
`72-Bit (8-Byte) 200-Pin Synchronous DRAM DIMM Module
`9.4 Fast SRAM Packages
`9.4.1 Packages for Fast Synchronous SRAMS
`9.4.2 Speed Considerations in SRAM Package Selection
`9.4.3 Trends in Systems Using Miniature Packaging
`9.5 SRAM Modules
`
`9.5.1 Multi-Package SRAM Modules
`9.5.2 SRAM Mulfichip Packages and Multichip Modules
`9.5.3 SRAM Multichip Modules
`9.6 Package Considerations in Replacing or upgrading a Cache SRAM
`9.6.1 General Considerations
`
`9.6.2 First Generation Upgrades
`9.6.3 Second Generation Upgrades
`9.6.4 Next Generation System Redesigns
`Bibliography
`
`Index
`
`Page 9
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`Page 9
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`Page 10
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`Page 10
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`7.1 Overview of DRAMS for Graphics Subsystems
`
`Graphics in television systems and graphics subsystems in computers use a sufficient
`amount of memory to require the higher density of DRAMS. These subsystems also
`have special requirements for higher bandwidth than is available on the basic asyn-
`chronous DRAM.
`
`A basic frame buffer in either the video or graphics application is required to
`provide at a minimum a continuous serial stream of data to refresh the display
`screen. A subsystem with some manipulation of bits requires, in addition, a random
`port for fast interface with the processor or graphics controller to provide the
`required data manipulations. Either these specific graphics requirements need to
`be met on the memory chip or a very high bandwidth memory must be available
`to support a graphics controller and a parallel—to-serial device which provide the
`required functions. Various combinations of these two approaches have been tried.
`These approaches are outlined in this chapter.
`The market volumes of the systems involved are historically high enough to have
`generated a number of applications—specific DRAMS to serve the special require-
`ments of the graphics subsystems. These included through the 1980s a variety of
`simple serial frame memories used in television applications and the more standard
`dual ported video DRAMS which have one serial and one random port which have
`been used in computer applications requiring more graphics manipulations.
`In the 1990s the datarate of the single port DRAM has been increased significantly
`with the introduction of the EDO (Hyperpage) mode and synchronous DRAMS,
`with Very wide interfaces. This has led to increased use of fast, wide single port
`DRAMS in graphics subsystems in PCs coupled with the use of standard graphics
`controllers which provide the multi port
`interface to the processor and the
`RAMDAC. Many new single port DRAM variants are also being developed such
`as the synchronous graphics DRAMs and the Multibank DRAM.
`
`Page 11
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`Page 11
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`7.2 Frame Memories for Television Applications
`
`7.2.1 Simple Serial Field Memory for Temporary Frame Storage
`
`In a basic video subsystem such as is used in television sets to reduce visible lines or
`visible flicker on the screen, only a simple serial access storage device with four—bit
`input and output is required to store a frame and recycle it to the screen. A random
`access port is not required since there is no graphics manipulation involved.
`Such devices are called field memories and are frequently made from DRAMs
`configured with serial input and output ports instead of a single parallel port. The
`DRAM core array is not changed. Read and write frequencies range from 33 to 50
`MHZ for a line of serial data.
`An example is a 256K><4 field memory from Texas Instruments. This part has a 5 V
`power supply, two four-bit wide ports for fast FIFO (first—in—first—out) operation, and
`asynchronous read and write at 33 MHZ providing a bandwidth of 16MB/sec. It has
`cascade connection capability so two or more parts can be connected to increase
`storage size.
`Cost is a pressing issue in consumer systems such as televisions and a smaller
`package with fewer leads helps reduce the cost of the part. There are no external
`address pins in a serial access RAM, which eliminates nine pins. The inputs and
`outputs are demultiplexed to improve control, which adds four pins, plus the write
`enable (WE\) becomes a separate Read (R) and Write (W) control. The Output
`Enable (OE\) is replaced by a Reset Read (RSTR) and Reset Write (RSTW) pin,
`resulting in the addition of one control pin, giving a total of 16 pins, so the field
`memory fits in a 16-pin package rather than the 20 or 20/26-pin package used by the
`random access 1M DRAM.
`The 20/26 package is a 26-pin package with the six middle pins removed to
`accommodate the large early generation 1M DRAM chips. A comparison between
`the pinouts of the serial field memory and the standard DRAM is shown in Figure
`7.1.
`Another change is that the RAS\ and CAS\ control signals are replaced with serial
`clocks.
`
`Page 12
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`Page 12
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`late generation 20-pin 1M ><4 DRAM package
`
`The addressing is controlled by write and read address pointers which clock the
`data read out or written in. These must be reset to Zero before a new memory access
`begins. The chip provides self refresh and arbitration logic to prevent conflict
`between memory refresh requests and data input and output cycles.
`A functional block diagram is shown in Figure 7.2 which shows the DATA input
`and output buffers, the data cache (”A” and ”B” line) buffers, the read and write
`counters along with the ring oscillator, the address pointers, the serial read and write
`timing controllers, and the read and write reset controllers.
`The first 120 words of data input are stored in the ”A” line cache buffer for fast access
`without having to access the main memory. The next data starting with word 120 goes
`into the 256—word write line buffer and thence into the main array. While the upper
`write line buffer is transferred to memory, the bottom write line buffer will be filling.
`The simple frame memory storing up to 4M bits running at 33 MHZ is useful for
`storing one frame in conventional television. High definition TV (HDTV) requires a
`sampling frequency of 70-80 MHZ and 16Mbit of serial RAM for field memory. Two
`interleaved 8Mbit serial DRAMS running at 50 MHZ or one 16Mbit serial DRAM
`running at 100 MHZ can serve this application.
`
`7.2.2 Serial DRAM for High Definition TV Frame Storage
`
`The block diagram of an 8Mbit 50 MHZ serial DRAM designed by Matsushita for
`HDTV applications is shown in Figure 7.3. The part has eight serial inputs and eight
`serial outputs. Each of the internal 128K x 8 subarrays has a serial-to—parallel and
`parallel—to—serial converter [10]. The bandwidth is 50MB / sec and for two of these
`parts interleaved is 100MB / sec.
`A higher density DRAM can permit storage of multiple fields of video data. For
`example, a 256Mbit serial access DRAM, also from Matsushita, can store two seconds
`Page 13
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`Page 13
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`
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`Texas Instruments [4])
`
`COLUMN
`ADDRESS COUNTER
`COLUMN
`DECODER
`
`1-Mbit SUBARRAY
`
`OUTPUT BUFFER
`
`REFRESH COUNTER
`
`ADDRESS COUNTER
`
`Page 14
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`
`
`to being almost universally present in PCs. The
`workstations and mainframes,
`requirements range from fairly simple graphics in low end PC to a much higher
`level of complexity in mid—range to high end PCs.
`
`7.3.1 Wide DRAM for Unified Memory in Low End PC
`
`Low end PC systems have used wide asynchronous DRAMS to obtain the bandwidth
`required to implement graphics features in the system. The high bandwidth of wide
`
`+1 l<-1ons(1ooMHz)
`
`/RAS
`
`/CAS
`
`Seloctlan)
`Y0-5
`
`(éfifi
`(Column)
`30””
`
`5
`
`_
`‘
`
`'
`
`E
`
`E
`
`V
`
`3‘.-m""""'ii
`£
`
`£1
`IG9DGGflG6@D@GQG@iIIIII
`Read Data from 'X1Y1'
`
`wme Data to 'X1Y1'
`
`3
`
`Write Data to'X2Y2‘
`
`Figure 7.4 Read/write timing diagram of 256M clocked field memory (source: H. Kotani,
`1994 [11] permission of IEEE)
`
`Page 15
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`Page 15
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`
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`of memory storage along with 25-33 MHZ speed and a wide interface. This means
`that the Wide asynchronous DRAMs have also been used for this application.
`For example, four 512K><8/9 fast page mode DRAMS running at 25 MHZ on a 32-
`bit bus offers 100MB / sec datarate. This combination can be upgraded to a single
`512K><32 25 MHZ fast page mode DRAM, saving the cost of the four packages. This
`in turn can be upgraded in speed to a 512K>< 32 Hyperpage mode DRAM with a 33
`MHZ cycle time which gives 130MB / sec datarate [15]. New printers now in devel-
`opment may require considerably more memory which will still require the wide
`interface.
`
`A pinout of a 28-pin 512K><8 DRAM TSOPII package is shown in Figure 7.5 along
`with that of a 70-pin 512K><32 DRAM TSOPII package. The savings in board space in
`going from four of the former to one of the latter are not as significant as in previous
`generations of upgrades, partially due to the number of power and ground pins
`which need to be added to keep the ratio of power and ground to DQs at 1:4 to
`control ground bounce.
`
`7.4 Graphics Features on Asynchronous Single Port DRAMS
`
`There has also been an attempt to add graphics features to the asynchronous single
`port DRAMS which are intended specifically for the graphics PC buffer applications.
`The write-per—bit function, also known as ”mask write”, is such a feature.
`There is also a function called persistent write—per-bit, which allows a mask to
`persist for more than one cycle. These features are also implemented on the dual port
`graphics DRAMs to be described in a later section.
`
`7.4.1 Write-Per-Bit
`
`The Write-per-Bit (WPB) function [12] provides the ability to alter, or mask, some of
`the bits in a word while leaving other bits in the same word unaffected. If the mask is
`Page 16
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`Page 16
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`UUCJUDUNNMMMMNMNM-4
`
`Figure 7.5 Pinout comparison of (a) 512K><8 and (b) 512K><32 DRAM packages (source:
`Samsung [14])
`
`set as part of the write cycle, it can be used with no increase in cycle time over a
`standard read or write cycle.
`Write-per—bit is implemented using a register on the data-in buffer which is latched
`on the falling edge of RAS\ and enabled by a low signal on the WE\ pin at a RAS
`high—t0-low transition. A block diagram of a 256K>< 16 DRAM with the mask data
`register is shown in Figure 7.6.
`This feature permits any number of bits in a word to be changed during a write
`cycle. In an asynchronous DRAM the mask is applied to the DQ lines and loaded into
`a register at the falling edge of RAS\ if the write enable (WE\) signal is low. When
`the DQ line is high, the corresponding bit will be Written when the write cycle
`executes. If the DQ line is low, the bit remains unchanged.
`An example of a timing diagram comparison for a simplified write-per—bit cycle
`and a normal write cycle is shown in Figure 7.7.
`
`Page 17
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`Page 17
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`
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`9
`
`ADDFIESS
`BUFFERS (9)
`
`V0 GATING
`
`512 x 512 x 16
`MEMORY
`ARRAY
`
`ajc Vcc
`<—-—o Vss
`
`Figure 7.6 Block diagram of 256K><16 DRAM showing mask data register (source: Micron
`Technology [13])
`
`Figure 7.8 illustrates the effect of the mask data on the stored data for different
`inputs along with the timing diagram for the masked and non-masked write for a
`512K><8 DRAM [13].
`During page mode operation, a mask can be loaded at the falling edge of RAS\
`and will remain set and active during a write cycle as long as RAS\ remains low. A
`mask is effective throughout a single page mode cycle and may not be changed
`during this cycle as shown in Figure 7.9 [15].
`
`7.4.2 Persistent Write-Per-Bit
`
`In systems where a single mask will be used for several cycles, some chips permit a
`mask to be set and persist for more than one cycle. This
`referred to as ”persistent
`write—per-bit”. It has not been commonly offered on the asynchronous wide DRAMs
`because of the additional silicon cost involved.
`
`7.5 Synchronous Single Port DRAMs Used in Graphics Systems
`
`The synchronous DRAMs provide additional speed for a single port DRAM up to
`perhaps 200 MHZ. The synchronous graphics DRAMs (SGRAMsfi;%r§1g functional
`
`Page 18
`
`
`
`Figure 7.7 Comparison of write-per-bit cycle vs. standard 8-bit write cycle (source: NEC [12])
`
`superset of the synchronous DRAMS. They have all of the features of the SDRAMS
`plus some additional features useful in graphics subsystems.
`The earliest synchronous graphics DRAM was a 4Mbit part developed by a few
`vendors such as United Memories, Fujitsu, and Hitachi. An 8M SGRAM, which is
`functionally identical to the 4M, is being offered by many Vendors and is expected to
`become the first major SGRAM part.
`
`7.5.1 4M Synchronous Graphics DRAMS
`
`The 4Mbit standard X 16 SDRAM is 3.3 V with an LVTTL interface and / or 5 V with a
`
`TTL interface. It is single ported and runs up to 66 MHZ providing 132MB/ sec of
`bandwidth. Graphics features supported included an eight-bit Block Write and a
`special function pin (DSF pin) to select between a standard SDRAM function and
`the SGRAM functions [17].
`The block diagram of a 4M synchronous graphics RAM is shown in Figure 7.10(a)
`and a pinout is shown in Figure 7.10(b). The SGRAM uses two banks internally
`which can provide a high speed sustained burst.
`Page 19
`
`Page 19
`
`
`
`ADDRESS 0
`
`ADDRESS 1
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`Figure 7.8
`
`Illustration of effect of WPB mask on stored and input data (source: Micron
`Technology [13])
`
`W4/IO4 Doul
`
`Figure 7.9 Write-per-bit during a fast page mode early write cycle (source: Hitachi [15])
`Page 20
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`Figure 7.10 4M synchronous graphics DRAM: (a) functional block diagram; (b) pinout
`(source: United Memories)
`
`The DSF pin is intended to implement the graphics features on this part. If the DSF
`pin is not connected, the part is intended to be a 4M SDRAM Version of the standard
`16M SDRAM. Graphics features include block write, and block write with auto
`precharge which will be described further in the next section.
`
`Page 21
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`Figure 7.11
`
`8M synchronous graphics RAM: (a) pinout; (b) pin definitions (source: NEC
`[9l)
`
`Page 22
`
`Page 22
`
`
`
`VCCQ
`VSSQ
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`
`SUPPLY VOLTAGE FOR DQ
`GROUND FOR DQ
`FLOATING PIN (WITH INTERNAL CONNECT TO VBB)
`
`SOURCE: NBC [9]
`
`(b)
`
`Figure 7.11
`
`(continued)
`
`7.6 Special Graphics Features on SGRAMs
`
`Special graphics features included on the 8M SGRAMS [5, 29] beyond the basic
`SDRAM features include masked block write, and mask write which includes the
`write-per—bit function. These features are standardized.
`To, the command functions present in the normal SDRAM mode register, the
`SGRAM has added Special Mode commands which control Color and Mask
`Registers which have also been added.
`The Color Register is used in block writes and the Mask Register is used in mask
`writes (write—per-bit). The Mode Register with a Special Mode Register section
`blocked out is shown in the block diagram of an 8M SGRAM in Figure 7.12. Also
`shown are the Color Register and Mask Register.
`The Command Truth Table of the SGRAM contains the standard command func-
`tions of the SDRAM and the Special Mode Register command functions for color and
`mask operation of the SGRAM as shown in Figure 7.13.
`The Special Mode Register is controlled by the DSF (designated special function)
`control pin.
`If the DSF pin is low (inactive), the 8M SGRAM operates similarly to a IEDEC
`Standard SDRAM. For standard SDRAM operation, the addresses AO—A8 are row
`addresses when the active command is given.
`When CAS\ is active, addresses AO—A7 are column addresses and address A8
`enables and disables the auto—precharge function. Address A9 is the bank select,
`BA. For BA low, Bank 0 is selected, and for BA high, Bank 1 is selected.
`Page 23
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`Figure 7.13 Command truth table for 8M SGRAM (source: Micron Technology)
`
`If the DSF pin is high (active), the 8M SGRAM graphics operations are active. These
`include the ”Special Mode Register Load” cycle, and the various masked write and
`block write functions.
`
`7.6.1 Load Special Mode Register Cycle
`
`When all control pins are low and the DSF pin is high, the Special Mode Register is
`loaded using inputs A0—A8 and the bank select BA. The ”Load Mode Register”
`command can be issued when both banks of the SGRAM are idle.
`A block diagram of the Special Mode Register definition is shown in Figure 7.14.
`
`7.6.2 Load Mask Register
`
`During a ”Load Special Mode Register” cycle, A5 controls the Mask Register. If A5 is
`”0”, the Mask Register is unchanged. If A5 is "1", the Mask Register is loaded with
`the new data applied to the DQS. The Mask Register then acts like a per DQ bit mask
`during Masked Write and Masked Block Write Cycles. The mask register will retain
`this data until it is loaded again or until the power is turned off.
`
`7.6.3 Load Color Register
`
`Similarly during a ”Special Mode Register Load” cycle, A6 controls the 32 bit color
`register. If A6 is ”O” the Color Register is unchanged and if A6 is "1” and the special
`Page 25
`
`Page 25
`
`
`
`Mask Register
`
`Leave Unchanged
`Load New Data
`
`Color Register
`Leave Unchanged
`Load New Data
`
`Operating Mode
`u Standard operation
`- All other states reserved
`
`Figure 7.14 Special mode register definition (source: Micron Technology [5])
`
`mode register load conditions are in effect, the Color Register is loaded with the data
`applied to the DQS. The Color Register then supplies the data during Block Write
`cycles. It will retain this data until reloaded or power is turned off.
`The Load Special Mode Register command can be given when both banks are idle.
`It can also be given if either or both banks are active but no Read, Write, or Block
`Write access is in progress.
`Other Special Mode Register inputs include AO—A4 which are all set at zero for
`standard operation. Other configurations of A0—A4 are reserved for future definition.
`A7, A8, and BA indicate the operating mode.
`A truth table and timing diagram for a ”Special Mode Register Load” cycle is
`shown in Figure 7.15.
`On the rising edge of the clock, CS\, RAS\, CAS\ and WE\ are low, and DSF is
`high. The register data on AO—A8 and the BS is sampled and the Mask or Color
`Page 26
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`Page 26
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`Figure 7.15 Special mode register load timing diagram (source: Toshiba)
`
`Register data on DQO—31 is sampled. A5 : A6 = 1 is not allowed, that is, the Color
`and Mask Registers can not be set on the same cycle.
`\
`
`7.6.4 Active Graphics Commands
`
`Commands with DSF high are also shown in the Command Truth Table for activate
`Masked Write (Write—per-Bit) and activate Block Write. Otherwise the DSF pm is a
`Page 27
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`Page 27
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`Figure 7.16 Masked write (write-per-bit) (source: Toshiba)
`Page 28
`
`Page 28
`
`
`
`The data from the color register is masked by the data from the mask register
`where "1" in the mask register enables the data from the color register and ”O” in the
`mask register disables it. For example the "O" in the LM+2 location of the mask
`register disables the ”1” applied from the LC+2 location of the color register so
`that the column—byte in DQ2 has a ”0” written as shown in Figure 7.16.
`The data on the DQS when the Block Write command occurs can be used to mask
`specific column-byte combinations within the block. DQM signals are applied to all
`eight COlU_II1I1S for each byte DQM (0-3). This is sometimes referred to as a ”column
`data mask”. For example, in Figure 7.16, the CM+1 bit of the column of data stored in
`DQO is masked by the column data mask so the ”1" written here from the color
`register does not appear.
`Figure 7.18 illustrates the effect of the Mask Register, Color Register and Column
`Data Mask for columns 0-7, the lower byte.
`A timing diagram for a page mode block write for CAS Latency 3 is shown in Figure
`7.19. In cycle 1, Bank 1 in activated. In cycle 3, a Block Write is activated for Bank 1.
`The Bank Select pin (BS) is high indicating bank selected and A8 is low indicating
`Bank 1. DSF is high activating the color and mask registers for the I / O (DQ). Column
`addresses A3—A7 select the first block of eight columns to be written out of 32 blocks
`in the row. The DQM provide the mask for the column byte input on the DQ.
`
`7.7 Clock Enable on SGRAM
`
`The Clock Enable (CKE) truth table is unchanged from the SDRAM. It indicates the
`logic state of CKE at clock edge 11 and the state at the immediately prior state n—1.
`This truth table was shown previously in Figure 6.24.
`
`7.8 Current State Truth Table on SGRAM
`
`While the Current State Truth Table was included in the Command Truth Table, it is
`
`broken out in Figure 7.20 for closer examination. The current state is the state of the
`SGRAM immediately prior to clock edge n.
`
`Page 29
`
`Page 29
`
`
`
`COLUMN DATA MASK
`IF DQM=1, ALL COLUMN MASK BlTS:0
`
`Figure 7.17
`
`Illustration of the effect of a block write command (source: Toshiba)
`
`The current state describes the commands issued to a specific bank. An idle bank is
`one that has been precharged with tRp met. ”Row Active” means the bank has been
`activated and tRcD met, but no accesses are in progress. ”Read” or ”Write” means a
`read or write burst has been initiated but has not yet terminated.
`The time for the underlying DRAM to perform the action initiated must be met in
`all cases. For example, ”Precharge” starts with the clocking in of the precharge
`command and ends after time tRP. So when activating a row, tRCD must be met,
`Page 30
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`Page 30
`
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`Figure 7.18 Lower byte mask / color registers and column mask (source: Toshiba)
`
`and when refreshing tRp must be met. The ”Burst Terminate" command is not bank
`specific but affects any Read or Write burst in progress in either bank.
`
`7.9 Other Single Port Graphics DRAMS
`
`Various other single -port DRAMs which are primarily targeted at graphics subsy
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