IPR2015-00862
`Petition for Inter Partes Review of U.S. Patent 7,202,843 - EXHIBIT 1006_Page 1
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`Patent Application Publication Nov. 20, 2003 Sheet 1 of 9
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`US 2003/0214473 Al
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`Fig. 1
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`Patent Application Publication Nov. 20, 2003 Sheet 2 of 9
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`US 2003/0214473 Al
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`Patent Application Publication Nov. 20, 2003 Sheet 3 of 9
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`US 2003/0214473 Al
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`Patent Application Publication Nov. 20, 2003 Sheet 5 of 9
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`US 2003/0214473 A1
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`Patent Application Publication Nov. 20, 2003 Sheet 7 of 9
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`PatentApplicationPublication
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`Nov. 20, 2003 Sheet 9 of 9
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`US 2003/0214473 A1
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`Page 10
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`US 2003/0214473 A1
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`Nov. 20, 2003
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`LIQUID CRYSTAL DISPLAY AND DRIVING
`METHOD TH ERFJOF
`
`II/\(.'I((iR()UNI) 01-5 'l‘IIl_i INVI_iN'I'I()N
`
`[0001]
`
`1. Field of the Invention
`
`[0002] The present invention relates to a liquid crystal
`display, and more particularly to a dual input mode liquid
`crystal display having high resolution and performing
`dynamic capacitance compensation (“I)C(."’).
`
`[0003]
`
`2. Description of the Related Art
`
`[0004] Lighter and thinner personal computers or televi-
`sion sets require lighter and thinner display devices. Since
`[lat panel displays such as liquid crystal displays (“l.CI)s”)
`satisfy such requirements, the LCDs have been developed
`and put to practical use in a variety of fields instead of
`cathode ray tubes (“CRTs”).
`
`[0005] LCDs display desired images by applying an elec-
`tric field to a liquid crystal layer with dielectric anisotropy
`between two panels and adjusting the strength of the electric
`field to control the transmittance of incident light onto the
`panels.
`
`[0006] LCDs are used in notebook computers as well as
`desktop computers. Computer users desire to see moving
`pictures by using the computers provided with developed
`multimedia environments. Thus, it is necessary to improve
`the response speed ol‘ the I.(.'I)s.
`
`improving the
`for
`[0007] One exemplary technique
`response speed of the I..CI)s is dynamic capacitance com-
`pensation {“I)CC”). Now, DCC will be described in detail.
`
`[0008] The DCC processes RUB data by comparing gray
`value Ior a pixel in a previous frame with gray value for a
`pixel in a current frame and adding a predetermined value
`larger than the diflerence between the gray values to the gray
`value of the previous frame. Atypical duration of one frame
`is 16.7 rnsec. Since it takes a time for a liquid crystal
`material in a pixel to respond to an applied voltage, time
`delay is inevitable until a desired gray is displayed. The
`DCC minimizes the time delay by applying a voltage larger
`than the predetermined voltage for a given gray to the pixel.
`
`[0009] FIG. 1 shows an exemplary DCC processing unit
`of a conventional single input mode LCD. The DCC pro-
`cessing unit is in a timing oontrollerofan LCD and is a part
`of a data processing block.
`
`[0010] A single input mode I..(.'I) transmits one data Ior
`one clock, while a dual input mode LCD transmits two data
`for one clock. The dual input mode LCD has an advantage
`of reducing the clock period by half relative to the single
`input mode I..(.'l). Accordingly, the dual input mode LCD
`simultaneously transmits both even and odd image data Ior
`one clock.
`
`the DCC processing unit
`[0011] Referring to FIG. 1,
`includes a DCC block 11, a memory controller 12 and frame
`memories A and B 13 and 14.
`
`[0012] The DCC block 11 receives current frame data
`from an external graphic source and previous frame data
`from the frame memory B 14 via the memory controller 12.
`The DCC block ll compares the current frame data and the
`previous Irame data and outputs DCC convened data
`
`selected from a built-in look-up table ("I.U'I'”) based on the
`result of the comparison. The optimal DCC data for the
`current frame data and the previous fame data is given in the
`I_U’l‘. The current Irame data is stored in the frame memory
`A 13 under the control 0|‘ the memory controller 12. As
`described above, a conventional single input mode LCD
`performing the DCC requires two frame memories for
`respectively storing the current frame data and the previous
`Irame data. Typically, I..CI)s having low resolutions such as
`VGA or WXG/\ grade resolution are single input mode
`LCDs, while LCDs having high resolutions equal to or more
`than SXGA grade resolution, which has the greater number
`of data lines and thus requires high clock Irequency for data
`processing, are dual input mode l.(TI)s.
`
`[0013] FIG. 2 shows an exemplary DCC processing unit
`of a conventional dual input mode LCD. The DCC process-
`ing unit is in a timing controller of the l.(Il).
`
`[0014] A DCC processing unit shown in FIG. 2 includes
`two sub-DCC processing units each processing even data or
`odd data and having substantially the same configu ration as
`the DCC processing unit shown in FIG. 1. A first sub—DCC
`processing unit includes a DCC block 21, a memory con-
`troller 22, a frame memory (T 23 and a Irame memory I) 24,
`and processes even data of a current frame. A second
`sub—DCC processing unit
`includes a DCC block 31, a
`memory controller 32, a frame memory A33 and a frame B
`34 and processes odd data of the current Irame.
`
`[0015] As shown in FIG. 2, the dual input mode LCD
`employing the DCC requires four frame memories 23, 24,
`33, and 34 and thus has a problem of the increased number
`of frame memories. To solve the problem of the increased
`number of frame memories,
`it
`is sugested that the high
`resolution LCD employs the single input mode while its
`timing controller increases the data processing clock Ire-
`quency. However, the high data processing clock frequency
`causes
`electromagnetic
`interference
`{“EMI”), which
`enforces to introduce a filter between the timing controller
`and the frame memory. This increases the area of a printed
`circuit board for mounting the timing controller thereon as
`well as a product cost.
`
`SUMMARY OF THE INVENTION
`
`[0016] The present invention provides a dual input mode
`LCD having high resolution in which DCC is performed
`with the same number of frame memories as a single input
`mode LCD by applying DCC to a half oll all pixels Ionning
`a liquid crystal screen without increasing clock frequency
`for data processing data.
`
`[0017] An LCD according to an embodiment of the
`present invention comprises a liquid crystal panel including
`a plurality of pixels at intersecting areas Ofa plurality ofgate
`lines and a plurality of data lines; a gate driver for applying
`a signal to sequentially scan the gate lines of the liquid
`crystal panel; a source driver for selecting and outputting a
`gray voltage to be applied to each of the pixels based on
`image data; and a timing controller including a DCC pro-
`cessing unit applying dynamic capacitance compensation
`{referred to as "DCC” hereinafter) to a part of the pixels, a
`timing redistribution block converting a format of the DCC-
`applied data to a predetermined format for the source driver,
`and a control signal generating block for generating a
`control signal Ior displaying an image.
`
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`US 2003/0214473 A1
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`Nov. 20, 2003
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`[0018] According to an exemplary embodiment of the
`invention, the DCC processing unit using only two memo-
`ries may be easily implemented in a dual input mode LCD,
`by applying the DCC processing to only some of a liquid
`crystal screen, for example, only half of the pixels.
`
`In addition, since a clock frequency for data pro-
`[0019]
`cessing in the frame memory of the timing controller is
`preferably the same as that provided for the timing controller
`of the dual input mode LCD, there is no increase of EM].
`
`[0020] According to aspects of the present invention, a
`variety of pixel arrangements for applying DCC to a half of
`pixels of the liquid crystal screen are provided.
`
`[0021] Amore complete appreciation of the invention, and
`many of the attendant advantages thereof, will be readily
`apparent as the same becomes better understood by refer-
`ence to the following detailed description.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`[0022] FIG. 1 shows an exemplary conventional single
`input mode LCD including a DCC processing unit;
`
`[0023] FIG. 2 shows an exemplary conventional single
`input mode LCD including a DCC processing unit;
`
`[0024] FIG. 3 shows a block diagram of an LCD accord-
`ing to an embodiment of the present invention;
`
`[0025] FIG. 4 shows a pixel arrangement according to a
`first embodiment of the present invention;
`
`[0026] FIG. 5 shows a graph of brightness curves for
`explaining a principle of the present invention;
`
`[0027] FIG. 6 shows a block diagram of a DCC process-
`ing unit of an LCD according to the first embodiment of the
`present invention;
`
`[0028] FIGS. 7A and 7B show pixel arrangements
`according to a second embodiment of the present invention,
`respectively;
`
`[0029] FIG. 8 shows a block diagram of a DCC process-
`ing unit of an LCD according to the second embodiment of
`the present invention;
`
`[0030] FIGS. 9A and 9]} show pixel arrangements
`according to a third embodiment of the present invention,
`respectively;
`
`[0031] FIGS. 10 and 11 each show DCC processing of
`data in an LCD according to the third embodiment of the
`present invention;
`
`[0032] FIG. 12 shows a block diagram of a DCC process-
`ing unit of an LCD according to the third embodiment of the
`present invention; and
`
`[0033] FIGS. 13A and 13B show pixel arrangements
`according to a fourth embodiment of the present invention.
`
`DETAILED DESCRIPTION OF PREFERRED
`EMB()DIMl'_"N’t'S
`
`invention
`[0034] Preferred embodiments of the present
`will be described more in detail hereinafter with reference to
`
`the accompanying drawings
`
`[0035] FIG. 3 shows a block diagram of an LCD accord-
`ing to an embodiment of the present invention.
`
`[0036] As shown in FIG. 3, an LCD according to an
`embodiment of the present
`invention includes a liquid
`crystal panel assembly 1, a gate driver 2, a source driver 3,
`a voltage generator 4 and a timing controller 5.
`
`[0037] Although not shown in detail in FIG. 3, the liquid
`crystal panel assembly 1 includes a plurality of gate lines
`and a plurality of data lines intersecting each other, and a
`plu ratity of pixels provided in intersecting areas of the gate
`lines and the data lines. The pixels receive analog voltages
`for displaying images via the data lines upon the sequential
`scanning of the gate lines.
`
`[0038] The timing controller 5 includes a DCC processing
`unit 51, a timing redistribution block 52 and a control signal
`generating block 53. The timing controller 5 receives RGB
`data, a data enable signal DE, a synchronization signal
`SYNC and a clock signal CLK from an external graphic
`sou rce. The RGB data is inputted to the DCC processing unit
`51 of the timing Controller 5 and DCC-transformed therein.
`The timing redistribution block 52 transforms the DCC-
`transformed data into a format suitable for the source driver
`
`3 and provides the format—transformed data to the source
`driver 3. The control signal generating block 53 generates
`several control signals for controlling display operation of
`the LCD in response to the data enable signal D13,
`the
`synchronization signal SYNC and the clock signal CLK.
`
`[0039] The voltage generator 4 generates gate onfolf volt-
`ages for scanning the gate lines, provides the gate onfoif
`voltages (Vontoff) to the gate driver 2, and outputs analog
`voltages to a gray voltage generator (not shown). The source
`driver3 selects gray voltages corresponding to the RGB data
`from the timing controller 5 and applies the gray voltages to
`the liquid crystal assembly 1.
`
`[0040] According to an embodiment of the present inven-
`tion, the DCC is not performed on all the pixels of the LCD
`but on a predetermined number of the pixels, eg., a half of
`the pixels. The LCD according to the present invention may
`have many different arrangemenLs of DCC—applied pixels.
`
`[0041] FIG. 4- shows an arrangement of pixels according
`to a first embodiment of the present invention, FIG. 5 shows
`a graph of average brightness of DCC—applied pixels and
`DCC—u napptied pixels according to an exemplary embodi-
`ment of the present invention, and FIG. 6 shows a block
`diagram of an exemplary DCC processing unit of an LCD
`according to the first embodiment of the present invention.
`
`[0042] Referring to FIG. 4-, the LCD according to the first
`embodiment oftbe present invention applies DCC to a pixel
`one by one. In detail, the DCC is applied to only the odd data
`in odd rows and only the even data in even rows of a pixel
`arrangement. Accordingly, when the LCD is a dual input
`mode where odd data and even data among RGB data are
`simultaneously inputted to a timing controller, the LCD may
`apply the DCC to one of the odd data and the even data.
`
`'l‘l1us, in this embodiment ot‘tl1e present invention,
`[0043]
`only two frame memories are required even for a dual input
`mode LCD as well as for a single input mode LCD since the
`timing controller applies the DCC to one of the odd data and
`the even data.
`
`[0044] Further, the clock frequency for transmitting the
`RGB data of the frame memories of the timing controller
`may be equal to the main clock frequency of the LCD.
`
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`Nov. 20, 2003
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`[0045] Further more, the sire of the frame memories is
`reduced by half since the DCC is applied to only half of all
`the RGB data, which in turn reduces the data to be stored in
`the frame memories by half.
`
`[0046] As shown in FIG. 5, an embodiment of the present
`invention applies the DCC not to all the pixels (image data)
`but to only a half of the pixels, and thus displays the image
`with an average response speed (average curve) of a
`response speed (DCC applied curve) of DCC—transformed
`data and a response speed {DCC unapplied curve) of DCC—
`untransformed data.
`
`[0047] A desired level of the average brightness may be
`adjusted by appropriately selecting values of the DCC-
`transfonned data larger than those in a look-up table for a
`single input mode l..(T|) employing the DCC. That is, a
`single input mode LCD obtains substantially the same
`average curve as that shown in FIG. 5 by applying the DCC
`to all
`the pixels, while an embodiment of the present
`invention can obtain the average curve by properly selecting
`the values in a look—up table for the application of the DCC
`although the DCC is applied to only a half of the pixels.
`
`[0048] Next, a DCC processing unit of an LCD according
`to the first embodiment of the present
`invention will be
`described with reference to FIG. 6. As described above with
`reference to FIG. 4,
`the llrst embodiment of the present
`invention applies the DCC to only the odd data in the odd
`rows and to only the even data in the even rows.
`
`[0049] As shown in FIG. 6, a DCC processing unit
`according to the first embodiment of the present invention
`includes: a first multiplexer 611 for receiving the odd data or
`even data of a current frame and outputting the even data or
`the odd data to a bypass block 621; a second multiplexer 612
`for receiving the odd data or even data of the cunent frame
`and outputting the even data or odd data to a DCC block 631;
`third and fourth multiplexers 651 and 652 each receiving the
`outputs ofthe bypass block 621 and the DCC block 631 and
`synthesizing the received data into transformed odd data and
`transformed even data; a memory controller 661 receiving
`the output of the second multiplexer 612 and supplying
`previous frame data to the DCC block 631; frame memories
`A and I1 671 and 672 each connected to the memory
`controller 661 and storing the DCC-applied current frame
`data and the DCC-applied previous frame data; and a line
`counter 641 for controlling the first to fourth multiplexers
`611, 612, 651 and 652.
`
`[0050] RGB data is inputted to the DCC processing unit.
`The RGB data includes even data and odd data of a current
`frame. llereinafter, the even data refers to the data for even
`pixels in each pixel row and the odd data refers to the data
`for odd pixels in each pixel row.
`
`[0051] The even data and odd data of the current frame are
`inputted to each of the first and second multiplexer 611 and
`612. The first and second multiplexers 611 and 612 respec-
`tively select the even data or the odd data based on an output
`signal of the line counter 641. The line counter 641 outputs
`the signal having information about row parity of the RG13
`data, ie., providing parity information as to whether the
`RGB data is associated with an even row or an odd row. As
`
`described above, the DCC is applied to only the odd data in
`the odd row and only the even data in the even row.
`Therefore, when the RGB data is associated with an odd
`
`row, the odd data is inputted to the DCC block 631 and the
`even data is inputted to the bypass block 621. On the
`contrary, when the RGB data is associated with an even row,
`the even data is inputted to the DCC block 631 and the odd
`data is inputted to the bypass block 621. Among the current
`frame data, the first multiplexer 611 selects the odd or even
`data to be inputted to the bypass block 621, while the second
`multiplexer 612 selects the odd or even data to be inputted
`to the DCC block 631.
`
`[0052] The bypass block 621 temporarily holds the output
`data of the first multiplexer 611 during the DCC processing
`ofthe output data ofthe second multiplexer 612 in the DCC
`block 631. The data from the second multiplexer 612 is not
`only inputted to the DCC block 631 but also stored in the
`frame memory A 671 via the memory controller 661. At the
`same time,
`the l)(T(.'-applied data of the previous frame
`stored in the frame memory B 672 is sent to the DCC block
`631 under the control of the memory controller 661. The
`data stored in the frame memory A 671 is moved to the frame
`memory B 672 by the memory-controller 661 for every
`frame. The DCC block 631 receives the culTent frame data
`and the previous frame data to perform the DCC processing
`of the current
`frame data and the previous frame data.
`I)C(_‘-transformed values are predetermined values
`for
`maximizing the response speed ofthe liquid crystal based on
`the current frame data and the previous frame data.
`
`[0053] The third multiplexer 651 connected to the bypass
`block 621 and the DCC block 631 rearranges the DCC—
`apptied data and the bypassed data into even data and odd
`data. For example, when the RGB data is associated with the
`first row of the pixel arrangement of FIG. 4, the odd data of
`the current frame is l)(.'(T-transformed by the I)(.f(.' block
`631 and the even data of the current frame is held in the
`
`bypass block 621 during a predetermined time. After receiv—
`ing the outputs of the DCC block 631 and the bypass block
`621,
`the third multiplexer 651 selects the output of the
`bypass block 621 to output it as the transformed even data.
`On the contrary,
`the fourth multiplexer 652 receives the
`outputs of the DCC block 631 and the bypass block 621 and
`selects the output of the DCC block 631 to output it as the
`transfonned odd data. Which multiplexer 651 or 652 is
`selected depends on the row parity information of the output
`signal of the line counter 641. In the second row of the pixel
`arrangement shown in FIG. 4, even data is DCC—trans—
`formed by the DCC block 631 and odd data is held in the
`bypass block 621 during a predetermined time. The third
`multiplexer 651 selects and outputs the output of the DCC
`block 631 as the transformed even data, and the fourth
`multiplexer 652 selects and outputs the output of the bypass
`block 621 as the transfonrled odd data.
`
`[0054] As a result, the DCC processing unit according to
`the first embodiment applies the DCC to only a halfofall the
`image data. Thus, the DCC using two frame memories may
`be applied to the dual input mode LCD with resolution equal
`to or more than SXGA. Since the DCC processing unit
`according to the first embodiment uses clock frequency
`equal to that of the single input mode, the increase of EMI
`is prevented. The above technical feature may be imple-
`mented by simple configuration of multiplexers,
`a
`line
`counter and a bypass block.
`
`[0055] Next, a DCC processing unit according to a second
`embodiment of the present invention will be described with
`reference to FIGS. 7 and 8.
`
`Page 13
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`US 2003/0214473 A1
`
`Nov. 20, 2003
`
`[0056] FIGS. 7A and 7B show arrangements of pixels
`according to a second embodiment of the present invention,
`and FIG. 8 shows a block diagram of an exemplary DCC
`processing unit of an LCD according to the second embodi-
`ment ot‘ the present invention.
`
`[0057] Referring to FIC'. 7/\, the second embodiment of
`the present invention applies the DCC two by one group of
`pixels. For example, the DCC is applied to only the even
`data in a pair of pixels (e.g., two adjacent pixels) for a first
`row while it is applied to only the odd data in a pair of pixels
`for a second row. It is apparent that it can be also applied
`vice versa. In the second embodiment of the present inven-
`tion, even data and odd data are alternately selected in pairs
`of pixels, and, when the row is altered, the order of selection
`is also altered. It can be seen that the DCC is applied to a half
`of all the pixels.
`
`[0053] FIG. 7B shows the application of the DCC two by
`two group of pixels. It is apparent to those skilled in the art
`to alter the number of the rows having the same selection
`rule by the simple design alteration.
`
`[0059] A DCC processing unit according to the second
`embodiment of the present invention is shown in FIG. 8.
`
`[0060] Referring to FIG. 8, a DCC processing unit
`according to the second embodiment of the present inven-
`tion is different from that of the first embodiment in that it
`has a rowfcolumn counter 841 instead of the line counter
`641. The rowfcolumn counter 841 detects the ordinals of the
`corresponding row and the corresponding column of the
`current frame data, and one of first to fourth multiplexers
`811, 812, 851 and 852 is selected based on an output signal
`of the rowfcolumn counter 841. The output signal of the
`rowfcolu mn counter 841 has count information.
`
`[0061] For example, in the pixel arrangement shown in
`FIG. 7A, the rowfcolumn counter 841 counts every row and
`every pair of pixels (e.g., two consecutive pixels) in every
`row. The first and second multiplexers 811 and 812 alter-
`nately select odd data or even data for every pair in response
`to the output signal of the rowfcolumn counter 84]
`to
`alternately distribute the even and odd data for two con-
`secutive pixels lo a bypass block 821 and a DCC block 831.
`
`[0062] For instance, based on the output signal (that has
`count information for the first two pixels shown in FIG. 7A)
`of the row,4'colun1n counter 841, the odd data is selected by
`the first multiplexer 811 and transmitted to the bypass block
`821, while the even data is selected by the second multi-
`plexer 8l2 and transmitted to the DCC block 831. For the
`next
`two pixels,
`the odd data is selected by the second
`multiplexer 812 and sent to the DCC block 831, while the
`even data is selected by the first multiplexer 811 and sent to
`the bypass block 821. The third and fourth multiplexers 851
`and 852 each select one of the outputs of the bypass block
`821 and the DCC block 831 in response to the output signal
`of the rowlcolurnn counter 84] to reconfigure the frame data.
`As for the abovc—described pixel arrangement shown in
`FIG. 7A, the odd datum for the first two pixels is processed
`by the bypass block 821 and the even data for the first two
`pixels is processed by the DCC block 831. Therefore, based
`on the count information of the rowfcolumn counter,
`the
`third multiplexer 851 selects and outputs the output of the
`DCC block 831 as transformed even data, and the fourth
`multiplexer 852 selects and outputs the Output of the bypass
`block 821 as transformed odd data.
`
`[0063] The pixel arrangement shown in FIG. 7B may be
`implemented by applying the DCC to every two rows for the
`pixel arrangement shown in FIG. 7A. Therefore, the row}
`column counter 841 of the DCC processing unit shown in
`FIG. 8 counts every two rows, and One Of the first to fourth
`multiplexers 811, 812, 851 and 852 is selected based on the
`information of the rowfcolu mn counter 841.
`
`[0064] The other components of the DCC processing unit
`shown in FIG. 8 have substantially the same functions and
`interconnecting relations as those of the DCC processing
`unit according to the first embodiment.
`
`[0065] The above—described second embodiment provides
`another example of applying the DCC to a half of all pixels.
`
`[0066] Next, a DCC processing unit according to a third
`embodiment of the present invention will be described with
`reference to FIGS. 9 to 12.
`
`[0067] FIGS. 9A and 9B show pixel arrangements
`according to a third embodiment of the present invention,
`FIGS. 10 and 11 show DCC processing of data according
`to the third embodiment, and FIG. 12 shows a block
`diagram of an exemplary DCC processing unit according to
`the third embodiment of the present invention.
`
`invention
`[0068] The third embodiment of the present
`applies the DCC to alternative pair of pixels (e.g.,
`two
`consecutive pixels). As described above, the present inven-
`tion relates to a dual input mode LCD with a high resolution
`equal to or higher than SXGA degree, and applies the DCC
`to even and odd data simultaneously. Since the DCC is
`repeatedly applied to alternate pixel pairs, once first pair of
`pixels {e.g., first two adjacent pixels) is I)(fC-transformed, a
`second pair of pixels (e.g., next two adjacent pixels) is not
`DCC—transformed. Therefore, the third embodiment of the
`present invention delays the DCC processing of one of the
`two pixel data, and perfonris the DCC processing of the
`delayed pixel data during the input of the pixel data for the
`next two pixels (which are not subject to the DCC).
`
`[0069] A pixel arrangement shown in FIG. 9/\ represents
`that the DCC is applied to alternate pairs of pixels and to
`alternate pixel rows. For example, the DCC is applied to the
`first two pixels in the first row, while not applied to the first
`two pixels in the next row. A pixel arrangement shown in
`FIG. 93 represents that the DCC is applied to alternate pairs
`of rows ('e.g., two consecutive rows).
`
`[0070] FIG. 10 shows the relation between input data and
`output data for the first
`row shown in FIG. 9A. The
`numerals shown in FIG. 10 refer to the ordinals of the
`
`pixels. Refe1Ting to FIG. 10, the DCC is applied to the first,
`the second, the fifth, and the sixth input data. FIG. 11 shows
`a data processing procedure for obtaining the output data
`shown in FIG. 10. In FIG. 11, it is assumed that the DCC
`processing is performed for two clocks.
`
`[0071] Referring to FIG. 11, the DCC is applied to the
`data for the first and the second pixels inputted simulta-
`neously in the DCC processing unit. The DCC is applied to
`the data for the first pixel, and the data for the second pixel
`is DCC—transformed after delay of one clock. This is pos-
`sible since the DCC is not applied to the data for the third
`and the fourth pixels. The processing procedure of the data
`for the first and the second pixels is equally applied to the
`data for the fifth and the sixth pixels.
`
`Page 14
`
`Page 14
`
`

`
`US 2003/0214473 A1
`
`Nov. 20, 2003
`
`[0072] FIG. 12 shows a block diagram of a DCC process-
`ing unit according to the third embodiment of the present
`invention.
`
`the DCC processing unit
`[0073] As shown in FIG. 12,
`according to the third embodiment of the present invention
`basically includes a bypass block 931, a DCC block 934, a
`memory controller 961 and two frame memories A and B
`971 and 972.
`
`[0074] A first multiplexer 911 is provided at input side of
`the DCC processing unit, and distributes a pair of pixel
`(even and odd data) to one of the bypass block 931 and the
`DCC block 934. A first rowfcolumn counter 912 provides
`rowfcolu mn count information of a pair ofpixcls for the first
`multiplexer 911 to select one of the even and odd data. A
`second multiplexer 951 is provided at output side of the
`DCC processing unit, and reconligures the outputs of the
`bypass block 931 and the DCC block 934 as transformed
`even data and odd data. Asecond rowfcolumn counter 952
`provides rowfcolumn count information of a pair of pixels to
`control the pixel pair selection of the second multiplexer
`951. The DCC according to the third embodiment is alter-
`natively performed on rows in a pixel arrangement like that
`in the pixel arrangement shown in FIG. 9A, and the DCC is
`alternatively performed on pairs on adjacent two rows in the
`pixel arrangement like that in the pixel arrangement shown
`in FIG. 9B. The change oi-the altemalion unit ofone row or
`two rows can be easily implemented by altering internal
`settings of the first and second rowfcolumn counters 912 and
`952.
`
`the even and odd data of the first
`[0075] Meanwhile,
`multiplexer 911 is inputted to the DCC block 934 via the
`third multiplexer 933. The even or odd data of the first
`multiplexer 911 is inputted to the third multiplexer 933 after
`delayed for one clock by a first delaying unit 921 or without
`delay. The third multiplexer 933 outputs the even or odd data
`of the first multiplexer 911 that is not delayed to the DCC
`block 934 based on the rowfcolumn count inforrnation from
`the third rowfcolumn counter 932, and outputs one—clock—
`delayed even or odd data of the first multiplexer 911 to the
`DCC block 934. The third rowfcolumn counter 932 provides
`the rowfcolumn count information for determining which
`pixel data is first DCC—transformed. First DC‘C—applied pixel
`data is outputted from the DCC block 934 and delayed for
`one clock by a second delaying unit 941. A fourth multi-
`plexer 935 selects the first DCC-applied pixel data to
`provide it for the delaying unit 941. The other components
`other than described above have substantially the same
`configurations and operations as those according to the first
`embodiment.
`
`[0076] Next, a fourth embodiment of the present invention
`will be described with reference to FIG. 13.
`
`[0077] FIGS. 13A and BB show pixel arrangements
`according to a fourth embodiment of the present invention.
`The pixel arrangements of the fourth embodiment are
`hybrids of the pixel arrangements according the second and
`the third embodiments. A DCC processing unit for applying
`the DCC to the pixel arrangements according to the fourth
`embodiment shown in FIG. 13 can be easily obtained by
`slightly altering the internal hardware of the DCC process-
`ing unit according to the third embodiment shown in FIG.
`12.
`
`[0078] Refening to FIG. 13A, a certain number of pixels
`of the three or more consecutive pixels in a column are not
`
`If the number of the DCC.‘-unapplied
`I)(T(T-transformed.
`pixels in a group of consecutive pixels increases, the groups
`of consecutive pixels are seen as a stripe. Therefore, it is
`advantageous to visibility to limit the number of the pixels
`in the group to equal to or less than tour.
`
`[0079] As described above, by applying the