QLogic Corporation
`
`FAS216/216U/236/236U
`Fast Architecture SCSI Processor
`
`Data Sheet
`
`Features
`n Host application and 16-bit peripheral application
`support
`n Compliance with ANSI SCSI standard
`X3.131-1994
`n Compliance with ANSI SCSI configured
`automatically (SCAM) protocol levels 1 and 2
`n Compliance with ANSI X3T10/855D SCSI-3
`parallel interface (SPI) standard
`n Compliance with ANSI X3T10/1071D Fast-20
`standard
`n Asynchronous data transfers up to 7 Mbytes/sec
`n Synchronous data transfers up to 5 Mbytes/sec
`(normal SCSI), 10 Mbytes/sec (fast SCSI), and 20
`Mbytes/sec (Ultra SCSI)
`Programmable synchronous transfer period
`Programmable synchronous transfer offsets up
`to 15 bytes
`
`n 24-bit transfer counter
`n Initiator and target modes
`n Differential driver protection (DIFFSENS)
`n Direct memory access (DMA) burst transfer rate up
`to 20 Mbytes/sec
`n Pipelined command structure
`n 16-byte data FIFO between DMA and SCSI
`channels
`n Parity pass-through on FIFO data
`n Part-unique ID code
`n On-chip, single-ended SCSI transceivers
`(48-mA drivers)
`n Clock rates up to 40 MHz
`
`SCSI
`DATA
`
`SCSI
`CONTROL
`
`DB BUS
`
`FIFO
`
`REGISTER BUS (OUT)
`
`TRANSFER
`COUNTER
`
`INTERRUPT
`
`STATUS
`
`SEQUENCE
`STEP
`
`SEQUENCERS
`
` COMMAND
`
`TRANSFER
`COUNT
`
`SEL/RESEL
`BUS ID
`
`SEL/RESEL
`TIMEOUT
`
`SYNC PERIOD
`
`SYNC OFFSET/
`SYNC ASSERT/
`SYNC DEASSERT
`
`CLOCK
`CONVERSION
`
`CONFIGURATION
`
`TEST (SCAM)
`
`REGISTER BUS (IN)
`
`PAD BUS
`
`NOTE:
`
`SCAM APPLIES TO THE FAS216U AND FAS236U ONLY.
`
`Figure 1. FAS2x6 Block Diagram
`
`53236-580-00 C
`
`FAS216/216U/236/236U
`
`1
`
`Oracle/Dot Hill Ex. 1007, pg. 1
`
`r
`r
`

`
`QLogic Corporation
`
`SCAM Implementation
`The FAS216U and FAS236U support levels 1 and 2 of
`the SCAM protocol. SCAM protocol requires direct access
`and control over the SCSI data bus and several of the SCSI
`phase and control signals. The majority of the SCAM
`protocol can be implemented in firmware at
`microprocessor speeds. The following SCAM features are
`supported in the chip hardware:
`n Arbitration without an ID
`n Slow response to selection with an unconfirmed ID
`n Detection of and response to SCAM selection
`System Organization
`The FAS2x6 controller systems support three main
`buses: the 8- or 16-bit data bus (DB), the 8-bit
`microprocessor address and data bus (PAD), and the 8-bit
`SCSI bus. The DB provides a path for DMA transfers
`through the FIFO. The PAD bus provides access to all
`internal registers. The FAS2x6 supports parity
`pass-through from the SCSI bus through the FIFO to the
`DB. This versatile split-bus architecture separates the two
`high-traffic information flows, the SCSI bus and DB bus,
`to provide maximum efficiency and throughput. Single- or
`split-bus configurations with 8- or 16-bit DMA are pin
`selectable. Table 1 shows chip operating conditions.
`Interfaces
`The FAS2x6 acts as an interface between the
`microprocessor and the SCSI bus in target or initiator mode.
`The other interfaces are described below:
`n Microprocessor Interface. The DB or PAD bus is
`the microprocessor interface to the FAS2x6. Both
`buses allow the microprocessor 8-bit read and write
`access to all chip registers, including the FIFO. The
`PAD bus allows microprocessor interface to the chip
`registers independent of DMA activity on the DB.
`n DMA Interface. The FAS2x6 logic transfers data
`to and from a buffer over the DB configured as 8 or
`16 bits. (Each byte on the bus has its own parity.) If
`byte control mode (Configuration 2 register bit 5)
`is set, an external DMA controller can dictate how
`the bytes are placed on the bus.
`Packaging
`The pin diagrams for the FAS216/216U and
`FAS236/236U are shown in figures 2 and 3. Pins that
`support the FAS216/216U and FAS236/236U operations
`are shown in figures 4 and 5. Dimensions for the
`FAS216/216U 84-pin plastic leaderless chip carrier
`(PLCC) and the FAS236/236U 100-pin plastic quad flat
`pack (PQFP) are shown in figures 6 and 7.
`
`NOTE: Throughout this data sheet, the term FAS2x6
`refers to the FAS216, FAS216U, FAS236, and FAS236U
`unless otherwise noted.
`Product Description
`The FAS2x6 chips are part of the QLogic SCSI
`processor family with features designed to facilitate
`SCSI-2 support (FAS216 and FAS236) and SCSI-3 support
`(FAS216U and FAS236U). The FAS216 and FAS236 can
`transfer synchronous data at 10 Mbytes/sec. The FAS216U
`and FAS236U can transfer data at 20 Mbytes/sec with
`SCAM support. The normal 5-Mbytes/sec transfer rate and
`the fast 10-Mbytes/sec transfer rate (FAS216U and
`FAS236U) are supported on-chip by setting the FASTSCSI
`bit (Configuration 3 register bit 4). Asynchronous transfers
`up to 7 Mbytes/sec are also supported. The FAS216U and
`FAS236U chips are firmware and pin compatible with the
`FAS216 and FAS236 chips, respectively. Figure 1 shows
`the FAS2x6 block diagram.
`The FAS2x6 replaces existing SCSI interface circuitry,
`which typically consists of discrete devices, an external
`driver, and a low-performance SCSI interface chip. The
`FAS2x6 contains a fast DMA interface; a 16-byte FIFO;
`and fast asynchronous and synchronous data interfaces to
`the SCSI bus, including drivers in single-ended mode.
`Differential mode requires external drivers.
`The FAS216 and FAS216U support single-ended
`mode; the FAS236 and FAS236U support single-ended and
`differential modes. Since the FAS2x6 operates in both
`initiator and target modes, it can be used in both host and
`peripheral applications. The chip performs such functions
`as bus arbitration, selection of a target, and reselection of
`an initiator. The FAS2x6 also handles message, command,
`status, and data transfers between the SCSI bus and its
`internal FIFO or between the SCSI bus and buffer memory.
`The chip maximizes protocol efficiency by utilizing a FIFO
`command pipeline and combination commands to
`minimize host intervention.
`Differential Driver Protection
`(FAS236/236U Only)
`The FAS236/236U pins 5 (DIFFSENS) and 7
`(EDIFFS) support the SCSI DIFFSENS differential driver
`protection function.
`The DIFFSENS function is enabled in differential
`mode when pins 5 and 7 are pulled up by an external device.
`The FAS236/236U is configured for differential mode
`operations when pin 87 (DIFFM) is low. If a single-ended
`device or terminator is connected while the chip is
`configured for differential operations, DIFFSENS becomes
`grounded, disabling the differential drivers. The Gross
`Error bit (Status register bit 6) is set and a disconnect
`interrupt is generated. The Gross Error bit and the
`disconnect interrupt are asserted as long as the DIFFSENS
`condition exists. The DIFFSENS function has no effect in
`single-ended mode.
`
`2
`
`FAS216/216U/236/236U
`
`53236-580-00 C
`
`Oracle/Dot Hill Ex. 1007, pg. 2
`
`

`
`VSS
`
`VSS
`
`DB0
`
`DB1
`
`DB2
`
`DB3
`
`DB4
`
`DB5
`
`DB6
`
`DB7
`
`DBP0
`
`VSS
`
`DB8
`
`DB9
`
`DB10
`
`DB11
`
`DB12
`
`DB13
`
`DB14
`
`DB15
`
`DBP1
`
`75
`
`76
`
`77
`
`78
`
`79
`
`80
`
`81
`
`82
`
`83
`
`84
`
`9 8 7 6 5 4 3 2 1
`
`10
`
`11
`
`74
`
`73
`
`72
`
`71
`
`70
`
`69
`
`68
`
`67
`
`66
`
`65
`
`64
`
`63
`
`DBWR
`
`DACK
`
`DREQ
`
`PAD7
`
`PAD6
`
`PAD5
`
`PAD4
`
`VSS
`
`PAD3
`
`PAD2
`
`PAD1
`
`PAD0
`
`FAS216/216U
`84-PIN PLCC
`
`QLogic Corporation
`
`SDI0
`
`SDI1
`
`SDI2
`
`SDI3
`
`SDI4
`
`SDI5
`
`SDI6
`
`SDI7
`
`SDIP
`
`VDD
`
`VSS
`
`12
`
`13
`
`14
`
`15
`
`16
`
`17
`
`18
`
`19
`
`20
`
`21
`
`22
`
`23
`
`SDO0
`
`SDO1
`
`SDO2
`
`SDO3
`
`VSS
`
`SDO4
`
`SDO5
`
`SDO6
`
`SDO7
`
`SDOP
`
`24
`
`25
`
`26
`
`27
`
`28
`
`29
`
`30
`
`31
`
`32
`
`62
`
`61
`
`60
`
`59
`
`58
`
`57
`
`56
`
`55
`
`54
`
`VDD
`
`CK
`
`A3, ALE
`
`A2, DBRD
`
`A1, BHE
`
`A0, SA0
`
`CS
`
`RD
`
`WR
`
`53
`
`52
`
`51
`
`50
`
`49
`
`48
`
`47
`
`46
`
`45
`
`44
`
`43
`
`42
`
`41
`
`40
`
`39
`
`38
`
`37
`
`36
`
`35
`
`34
`
`33
`
`RESET
`
`INT
`
`MODE0
`
`MODE1
`
`RSTI
`
`ACKI
`
`REQI
`
`BSYI
`
`SELI
`
`VSS
`
`RSTO
`
`ATN
`
`IO
`
`CD
`
`MSG
`
`VSS
`
`ACKO
`
`REQO
`
`BSYO
`
`SELO
`
`VSS
`
`Figure 2. FAS216/216U 84-Pin PLCC Pin Diagram
`
`53236-580-00 C
`
`FAS216/216U/236/236U
`
`3
`
`Oracle/Dot Hill Ex. 1007, pg. 3
`
`

`
`QLogic Corporation
`
`SDO7
`
`SDOP
`
`NC
`VSS
`VSS
`SELO
`
`BSYO
`REQO
`
`ACKO
`
`VSS
`VSS
`MSG
`
`CD
`
`IO
`
`ATN
`
`RSTO
`VSS
`VSS
`
`SELI
`
`BSYI
`
`REQI
`
`ACKI
`RSTI
`
`MODE1
`
`MODE0
`
`INT
`RESET
`NC
`
`WR
`RD
`
`51
`52
`
`53
`
`54
`55
`56
`
`57
`
`58
`
`59
`
`60
`61
`
`62
`
`63
`
`64
`65
`
`66
`
`67
`68
`69
`
`70
`
`71
`
`72
`
`73
`
`74
`
`75
`
`76
`77
`
`78
`
`79
`
`80
`
`CS
`
`A0, SA0
`
`A1, BHE
`
`A2, DBRD
`A3, ALE
`
`CK
`
`DIFFM
`
`VDD
`
`81
`82
`
`83
`84
`
`85
`
`86
`87
`
`88
`
`89
`
`50
`49
`
`48
`
`47
`
`46
`45
`
`44
`
`SDO6
`SDO5
`
`SDO4
`VSS
`VSS
`
`SDO3
`
`SDO2
`
`FAS236/236U
`100-PIN PQFP
`
`NC
`PAD0
`
`PAD1
`
`PAD2
`
`PAD3
`VSS
`
`VSS
`
`PAD4
`PAD5
`
`PAD6
`PAD7
`DREQ
`
`90
`91
`
`92
`93
`
`94
`95
`
`96
`
`97
`
`98
`
`99
`
`100
`
`43
`42
`41
`40
`
`39
`
`38
`
`37
`36
`35
`
`34
`
`33
`
`32
`31
`
`SDO1
`SDO0
`
`VSS
`
`VSS
`NC
`VDD
`
`SDIP
`SDI7
`
`SDI6
`
`SDI5
`SDI4
`
`SDI3
`SDI2
`
`30
`29
`
`28
`27
`
`26
`25
`24
`
`23
`22
`
`21
`20
`
`19
`18
`
`17
`16
`
`15
`14
`
`13
`12
`
`11
`10
`
`1
`
`2 3 4 5 6 7 8 9
`
`SDI1
`
`SDI0
`
`NC
`
`DBP1
`DB15
`
`DB14
`DB13
`DB12
`
`DB11
`DB10
`
`DB9
`DB8
`
`VSS
`
`VSS
`DBP0
`
`DB7
`
`DB6
`DB5
`DB4
`
`DB3
`DB2
`
`DB1
`DB0
`
`EDIFFS
`
`TGS
`
`DIFFSENS
`IGS
`
`NC
`DBWR
`DACK
`
`Figure 3. FAS236/236U Pin Diagram
`
`4
`
`FAS216/216U/236/236U
`
`53236-580-00 C
`
`Oracle/Dot Hill Ex. 1007, pg. 4
`
`

`
`FAS216/216U
`
`QLogic Corporation
`
`MICROPROCESSOR
`INTERFACE
`
`DMA AND
`MICROPROCESSOR
`INTERFACE
`
`RESET
`
`CLOCK
`
`POWER
`AND GROUND
`
`A0, SA0
`A1, BHE
`A2, DBRD
`A3, ALE
`CS
`INT
`PAD7-0
`RD
`WR
`
`DACK
`DB15-0
`
`DBP1-0
`DBWR
`
`DREQ
`
`RESET
`
`CK
`
`VDD
`VSS
`
`57
`58
`59
`60
`56
`52
`71-68, 66-63
`
`55
`54
`
`73
`
`10-3, 84-77
`11, 1
`74
`72
`
`53
`
`61
`
`21, 62
`
`SEE NOTE
`
`48
`
`37
`42
`46
`
`35
`40
`41
`39
`47
`
`36
`49
`43
`20, 19-12
`
`32, 31-28, 26-23
`
`SCSI
`INTERFACE
`
`ACKI
`ACKO
`ATN
`BSYI
`
`BSYO
`CD
`IO
`
`MSG
`REQI
`REQO
`
`RSTI
`RSTO
`SDIP, SDI7-0
`
`SDOP, SDO7-0
`
`SELI
`SELO
`
`45
`
`34
`
`50, 51
`
`MODE1-0
`
`MISC
`
`NOTE:
`
`VSS = 2, 22, 27, 33, 38, 44, 67, 75, 76
`
`Figure 4. FAS216/216U Functional Signal Grouping
`
`53236-580-00 C
`
`FAS216/216U/236/236U
`
`5
`
`Oracle/Dot Hill Ex. 1007, pg. 5
`
`

`
`QLogic Corporation
`
`SCSI
`INTERFACE
`
`MISC
`
`FAS236/236U
`
`72
`59
`65
`70
`57
`63
`64
`62
`71
`58
`73
`66
`37, 36-29
`52, 51-48, 45-42
`69
`56
`
`ACKI
`ACKO
`ATN
`BSYI
`BSYO
`CD
`IO
`MSG
`REQI
`REQO
`RSTI
`RSTO
`SDIP, SDI7-0
`SDOP, SDO7-0
`SELI
`SELO
`
`87
`5
`7
`74, 75
`
`DIFFM
`DIFFSENS
`EDIFFS
`MODE1-0
`
`82
`83
`84
`85
`81
`76
`99-96, 93-90
`
`80
`79
`
`1
`
`26-19, 15-8
`7, 16
`
`22
`
`100
`
`77
`
`86
`
`38, 88
`
`SEE NOTE
`
`IGS
`
`TGS
`
`4
`6
`
`EXTERNAL
`TRANSCEIVER
`CONTROL
`
`3, 28, 39, 53, 78,89
`
`MICROPROCESSOR
`INTERFACE
`
`DMA AND
`MICROPROCESSOR
`INTERFACE
`
`RESET
`
`CLOCK
`
`POWER
`AND GROUND
`
`NO CONNECT
`
`A0, SA0
`A1, BHE
`A2, DBRD
`A3, ALE
`CS
`INT
`PAD7-0
`RD
`WR
`
`DACK
`DB15-0
`DBP1-0
`DBWR
`DREQ
`
`RESET
`
`CK
`
`VDD
`VSS
`
`NOTE:
`
`VSS = 17, 18, 40, 41, 46, 47, 54, 55, 60, 61, 67, 68, 94, 95
`
`Figure 5. FAS236/236U Functional Signal Grouping
`
`6
`
`FAS216/216U/236/236U
`
`53236-580-00 C
`
`Oracle/Dot Hill Ex. 1007, pg. 6
`
`

`
`QLogic Corporation
`
`0.045 X 45(cid:176) CHFR
`
`0.576
`
`0.05 (NOM)
`
`1.19 SQ
`(NOM)
`
`0.576
`
`0.45
`
`PIN 1
`INDICATOR
`
`1.153 SQ
`(NOM)
`
`0.010 X 45(cid:176)
`CHFR (3)
`
`0.028 (NOM)
`
`0.018 (NOM)
`
`0.072 (NOM)
`
`0.093 (NOM)
`
`NOTE:
`
`ALL DIMENSIONS ARE IN INCHES.
`ALL DIMENSIONS ARE NOMINAL UNLESS SPECIFIED OTHERWISE.
`
`Figure 6. FAS216/216U 84-Pin PLCC Mechanical Drawings
`
`0.175 (NOM)
`
`0.15 (NOM)
`0.045 X 45(cid:176)
`CHFR
`
`1.12 SQ
`(NOM)
`
`0.025 (NOM)
`
`0.107 (NOM)
`
`PIN 80
`PIN 81
`
`17.9 – 0.25
`
`14.00
`
`23.9 – 0.25
`
`20.00
`
`INDEX MARK
`
`PIN 100
`
`PIN 1
`
`PIN 30
`
`PIN 51
`
`A
`
`PIN 50
`
`PIN 31
`
`4(cid:176) TYPICAL
`
` 0.8 + 0.15
`
`0.13 MIN
`0.23 MAX
`
` 1.95 REF
`
`3.4 MAX
`
`0.13 MIN
`
`0.22 MIN
`0.38 MAX
`
`0.65 BSC
`
`DETAIL A
`
`NOTE:
`
`ALL DIMENSIONS ARE IN MILLIMETERS.
`ALL DIMENSIONS ARE NOMINAL UNLESS SPECIFIED OTHERWISE.
`
`Figure 7. FAS236/236U 100-Pin PQFP Mechanical Drawings
`
`53236-580-00 C
`
`FAS216/216U/236/236U
`
`7
`
`Oracle/Dot Hill Ex. 1007, pg. 7
`
`

`
`QLogic Corporation
`
`Electrical Characteristics
`
`Table 1. Operating Conditions
`
`Symbol
`
`VDD
`IDDa
`IDDb
`TA
`
`Description
`
`Supply voltage
`
`Supply current (static IDD)
`
`Supply current (dynamic IDD)
`
`Minimum
`
`4.75
`
`Ambient temperature
`
`0
`
`Maximum
`
`5.25
`
`4
`
`40-60
`
`70
`
`Unit
`
`V
`
`mA
`
`mA
`
`oC
`
`Table Notes
`Conditions not within operating conditions but within the absolute maximum stress ratings may cause the chip to malfunction.
`aStatic IDD is measured with no clocks running and all inputs forced to VDD, all outputs unloaded, and all bidirectional pins configured
`as inputs.
`bDynamic IDD is dependent on the application.
`
`Specifications are subject to change without notice.
`QLogic is a trademark of QLogic Corporation.
`
`©October 4, 1996 QLogic Corporation, 3545 Harbor Blvd., Costa Mesa, CA 92626, (800) ON-CHIP-1 or (714) 438-2200
`
`8
`
`FAS216/216U/236/236U
`
`53236-580-00 C
`
`Oracle/Dot Hill Ex. 1007, pg. 8