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`
` CROSSROADS EXHIBIT 2319
`Oracle Corp., et al v. Crossroads Systems, Inc.
` IPR2014-01207 and IPR2014-1209
`
`CROSSROADS EXHIBIT 2319
`NetApp Inc. v. Crossroads Systems, Inc.
`IPR2015-00776
`
`

`

`Verrazano Software Architecture
`
`Crossroads Confidean Material
`
`Updated: 08/27/97 3:24 PM
`
`1.
`
`INTRODUCTION .................................................................................................................................4
`
`2. OVERVIEW .......................................................................................................................................... 4
`
`2.1
`2.2
`2.3
`
`PRODUCT HARDWARE DESCRIPTION................................................................................................ 4
`PROTOTYPE DESCRIPTION ................................................................................................................ 4
`DESIGN PHILOSOPHY........................................................................................................................ 4
`
`3. CORE SOFTWARE MODULES....................................................................................................5
`
`
`BOOT CODE...................................................................................................................................... 5
`3.1
`DIAGNOSTICS ................................................................................................................................... 5
`3.2
`KERNEL............................................................................................................................................ 5
`3.3
`PC DRIVER ...................................................................................................................................... 6
`3.4
`SCSI DRIVER ................................................................................................................................... 6
`3.5
`BRIDGE CODE .................................................................................................................................. 7
`3 .6
`Architectural Overview ........................................................................................................... 7
`3.6.1
`Buffer Management ............................................................................................................. 11
`3. 6.2
`Protocol Translation............................................................................................................. 12
`3.6.3
`Address Translation.............................................................................................................. 13
`3. 6.4
`Program Structure................................................................................................................ 14
`3. 6.5
`3 .7
`ETHERNET DRIVER......................................................................................................................... 15
`3.8
`CONFIGURATION ............................................................................................................................ 15
`3. 8.1
`Configurable Options ........................................................................................................... I5
`3. 8.2
`Serial Console ....................................................................................................................... 1 6
`3. 8.3
`Telnet .................................................................................................................................... 16
`3. 8.4
`FTP ....................................................................................................................................... I6
`3. 8.5
`SNMP.................................................................................................................................... l 6
`3. 8. 6
`HTTP .................................................................................................................................... 16
`3.9
`MANAGEMENT ............................................................................................................................... 16
`3. 9.]
`SNMP.................................................................................................................................... 1 6
`3.9.2
`HTTP .................................................................................................................................... 16
`
`4. DIAGNOSTIC TEST SOFTWARE ................................................................................
`
`
`DIAGNOSTIC TESTS ........................................................................................................................ 17
`Initial boot............................................................................................................................. 1 7
`LED visual test...................................................................................................................... 17
`Flash Memory - Read test .................................................................................................... 1 7
`Instruction Memory - Read/write test................................................................................... 1 7
`Serial Controller - read/write test......................................................................................... I8
`Ethernet Controller - read/write test ................................................................................... 18
`PCI Memory Read/Write Test .............................................................................................. 18
`Tachyon ................................................................................................................................ 18
`Symbios 875 SCSI Controller............................................................................................... 18
`
`4.1
`4.1.]
`4.1.2
`4.1.3
`4.1.4
`4.1.5
`4.1. 6
`4.1. 7
`4.1.8
`4.1.9
`
`Figure 3.1- Core processes and flow ............................................................................................................... 8
`Figure 3.2 - Management Commands Control Flow....................................................................................... 9
`Figure 3.3 - FCP Write with pre-fetch .......................................................................................................... 10
`
`Table 3.1 - FCP_CNMD Information Unit ................................................................................................... 12
`Table 3.2 - SCSI Command Descriptor Block .............................................................................................. 12
`Table 3.3- Default Direct Address Map, FCP->SCSI (Narrow) .................................................................. 13
`Table 3.4 - Default Direct Address Map - SCSI->FCP (Narrow) ................................................................. 13
`Table 3.5 - Ordered Address Map, FC->SCSI .............................................................................................. 14
`Table 6.1 960RP Interrupt Map .....................................................................Error! Bookmark not defined.
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`Crossroads Confidential Material
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`Updated: 08/27/97 3:24 PM
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`Table 7.1 System Memory Map .....................................................................Error! Bookmark not defined.
`Table 7.2 PCI Memory Map ..........................................................................Error! Bookmark not defined.
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`Verrazano Software Architecture
`
`Crossroads Confidential Material
`
`Updated: 08/27/97 3:24 PM
`
`1. Introduction
`
`This document provides the architectural details for the Verrazano Bridge and gives an overview of the
`methods, processes, and requirements involved in the software development effort. It is meant to provide
`the basic guidelines for development, and as such is subject to change as the implementation evolves.
`
`2. Overview
`
`2.1 Product Hardware Description
`
`The target hardware is an embedded system centered around the Intel i960RP processor. Incorporated on
`the i960 bus are program memory, flash memory, and a serial UART. The secondary PCI bus from the
`i960RP will have an HP Tachyon Fibre Channel controller, using the Interphase TPI PCI interface, and
`4MB DRAM for data buffering. This DRAM will interface to this PCI bus via a custom interface designed
`in house. The secondary PCI bus will also have the Symbios 53C875 PCI SCSI controller. The 960RP
`primary PCI bus will have an AMD lOBaseT Ethernet controller.
`Specific details of the hardware architecture and design can be found in the Verrazano Requirements
`Document, and in the Verrazano Strategic Specification.
`
`2.2 Prototype Description
`To accelerate software development and to allow for software development to be overlapped with
`hardware development, a PC based prototype platform will be used. Functionally, the PC will be used for
`the PCI bus and system memory. The host processor will not be used except for limited debugging
`purposes. The processor used will be the Intel Cyclone board with the i96OJX processor module. This will
`have 4MB of DRAM for program memory. The PLX 9060 PCI bridge on the Cyclone will allow for
`interfacing the 960 processor to the FC and SCSI devices over the PCI bus. The Fibre Channel interface
`will be the Interphase Tachyon based PCI adapter. The SCSI interface will be the Symbios SYM53C875
`PCI adapter. Serial communication, flash memory, and other basic functionality is provided by the
`Cyclone board.
`This provides an architecturally similar platform using essentially identical core components for
`development. Porting to the Verrazano hardware platform will require changes limited to the PCI bridge,
`memory and device mapping, and serial and other peripheral interfaces. The core driver and bridge code
`will remain unchanged.
`
`2.3 Design Philosophy
`0
`‘C’ Code base
`
`0 Modular design
`0
`Pass-through, event driven architecture
`0
`Use Existing OS, Drivers, Protocol Stacks as possible
`0 Design for performance, future portability, maintainability
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`3. Core Software Modules
`
`3. 1 Boot Code
`
`At system boot, code will be required to initialize the hardware, perform basic system testing, and load the
`runtime code. The expectation is that this will consist in large part of modules available from Intel
`(mon960) and the runtime OS (VxWorks). Portions of this code will be modified and extended to support
`hardware specific characteristics which are TBD.
`
`Requirements:
`0
`Initialize hardware
`Run Power On Self Test
`
`Set Processor, PCI address mapping
`Initialize and start VxWorks, core software
`
`0 0
`
`0
`
`3.2 Diagnostics
`
`In addition to the power on self test code executed at boot time, further diagnostics will be required for
`manufacturing test, field diagnosis, and returned unit test. These tests should be more extensive than the
`POST, and should include tests for all major subsystems of the Verrazano board. Diagnostics should be
`accessible from the serial console, TELNET via Ethernet, and SNMP via Ethernet. Future extensions
`should include accessibility via SCSI and Fibre Channel via FC—IP.
`
`Requirements:
`
`0
`
`One base test suite is desired. covering:
`0 Manufacturing Test
`0
`Field Test
`.
`0
`Return Unit Test
`Processor test
`
`Memory test
`PCI test
`
`Buffer memory test
`Tachyon test - internal loop back, electrical (GLM) wrap, external loop back
`Symbios test - internal loop back, external loop back
`Ethernet adapter test - internal loop back, external loop back
`
`3.3 Kernel
`
`Currently VxWorks from Wind River Systems is the targeted mntime OS. Future ports may be targeted for
`IxWorks.
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`Updated: 08/27/97 3:24 PM
`
`3.4 FC Driver
`
`The Fibre Channel driver will be based on the current ICS FC-2 SDK. Modifications may be made to the
`initialization and FC-4 layers. The interfaces to this code will be defined in section Error! Reference
`source not found. of this document.
`
`The FC driver provides the following functionality:
`0 Manage logins and logouts
`0 Manage FC-4 exchanges
`0 Activation of new exchange for each FCP command
`0 Manage FCP command(exchange) through all phases for that command
`0
`Provide means for FC-4 to do process login for an FCP attached device
`0
`Receive all FC-4 data commands
`0 Manage exchanges
`0 Activation and Deactivation of exchanges
`o
`assignment of X_ID
`0 Manage sequences
`0
`Initiation and termination of sequences
`0
`SEQID assignment
`0 Managing sequence initiative
`0 Manage EE credit
`
`Initial support will be arbitrated loops only. Later versions will support fabrics including F and FL ports.
`
`3.5 SCSI Driver
`
`The SCSI driver will consist of two parts. The SCSI state machines will be implemented in the Symbios
`SCRIPTS language, which runs on the 875 internal processor. This code will interface with a higher layer
`interface running on the i960 processor. The interfaces to this code and other architectural characteristics
`will be defined in section Error! Reference source not found. of this document.
`
`0
`
`The SCSI driver provides the following functionality:
`0
`Provide SCSI initiator support with a single SCSI ID
`0 Manage Commands and Messages to targets
`0 Manage DMA to/from buffer memory
`Provide SCSI target support
`0
`Respond to multiple target IDs
`0
`Process Commands and Messages
`0 Manage DMA to/from buffer memory
`0 Manage all SCSI bus phases and transitions
`0 Manage Synchronous, wide, and fast negotiation
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`3.6 Bridge Code
`
`The Bridge code provides for the conversion and transport of data and commands between FCP and SCSI
`devices. This code should be event driven, of a pass-through design and use a store and forward method of
`data transport. Major functionality is defined below. Additional operational characteristics are outlined in
`the Verrazano Requirements Document.
`
`Requirements:
`
`0
`
`Process incoming CDBs from FC4 and SCSI layers
`Manage command and data transfer between FCP and SCSI drivers
`Manage data buffers and internal command structures
`Manage FC4 interface
`Translate protocols from FCP to SCSI-2
`Translate address information between FC and SCSI devices
`
`3.6.1 Architectural Overview
`
`Figure 3.1diagrams the core processes and program flow within the bridge. Three areas of fimctionality
`are diagrammed, for FCP and SCSI processes. These are:
`
`0
`0
`0
`
`Event handling
`Bridge processing
`Request handling
`
`Event handlers process incoming requests from the FCP or SCSI interfaces and route these requests to the
`appropriate bridge module. The bridge modules handle the creation and management of buffer queues,
`address translation, and protocol translation. The request handlers initiate transfers on the FCP or SCSI
`interface as required by the other modules. Further description of these modules and their components is
`provided in the following sections.
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` FCP RECEIVE EVENT
`
`SCSI RECEIVE EVENT
`
`
`
`
`
`
`
`FCP MD,
`FCP_D TA Out
`
`
`
`FCP_RSP,
`scsu Status.
`FCP_DATA In
`Data In
`
`SCSI Command.
`Dali Out
`
`
`SCSI Command.
`SCSI Status.
`Data Out
`Dam In
`
`
` FCP SEND REQUEST SCSI SEND REQUEST
`
`
`
`
`
`Figure 3.1- Core processes and flow
`
`(Describe FCP Command bridge, scsi command bridge as those processing for SCSI initiators and FC
`initiators.)
`
`(Add examples, with steps l-N defined where each arrow in flow above is step described.)
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`Figure 3.1 illustrates control flow for management commands. Management commands are those
`commands that are processed by the bridge directly, and not passed through to the alternate interface. This
`capability is to be provided to support in-band diagnostics, configuration, and management through the
`FCP and SCSI interfaces in future releases. Similar interfaces to the Management Command Service will
`be provided for out of band management, via the Ethernet and serial interfaces.
`
`SCSI RECEIVE EVENT
`
`
`
`Management
`Command
`Request
`
`FCP
`Command
`Bridge
`
`Management Command
`Service
`
`SCSI
`Command
`
` FCP RECEIVE EVENT
`Bridge
`
`Management
`Command
`Response
`
`FCP SEND REQUEST
`
`
`
`
`
`SCSI SEND REQUEST
`
`Figure 3.2 - Management Commands Control Flow
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`Certain other cases exist to the normal flow of execution. Chief among these is the case where an
`FCP_CMND Write is received. In order to reduce inactive time on the SCSI bus, data is pre-fetched. This
`is exhibited in Figure 3.3. The bridge module snoops the command, and, if necessary, allocates buffers and
`requests data from the FCP device before generating the SCSI command. Subsequent data transfers and
`status phases for this command proceed normally.
`
`Incom'ng
`FCP_CMD Writ-
`
`SCSI m UM
`
`Du In Bu"-
`
`(FCP_XI-iILRDY)
`FCP_DATA
`
` Pralmn om
` FCP SEND REQUEST
`SCSI SEND REQUEST
`
`Figure 3.3 - FCP Write with pre-fetch
`
`(Optimize io vs throughput? Discuss - can submit cmd before or after xfer__rdy, may be important for tapes
`and like devices)
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`3.6.2 Buffer Management
`
`System memory is available both in the 960 local memory space or in PCI memory space. Hardware
`performance dictates that highest performance is available when a device requiring memory ‘reads from
`nearest RAM’. Accordingly, DMA read lists for the Tachyon will be located in PCI buffer memory, and
`Tachyon write lists in program memory. Interrupt structures and Bridge command structures will reside in
`program memory. Although these lists will be read by the Tachyon and Symbios part, it is likely that more
`read operations will be performed by the 960 on the CDB elements. Data buffering will be in the PCI
`buffer memory.
`
`Primary Data elements:
`
`Data buffers
`
`o Allocated sequentially
`- 2K each
`
`a In 4MB PCI Buffer memory
`0 Memory may be shared with Tachyon DMA lists, so less than 2048 buffers available
`0 Empirical testing to determine benefits of DMA lists in PCI vs. CPU memory
`
`Bridge command elements
`
`0 Allocated in program memory
`0 Number allocated limits the number of outstanding IO requests
`0 512 Allocated
`
`0 Max 480 targets (Wide SCSI targets times LUNS)
`0 Average queue depth per target greater than 1, TBD
`0 About 96 bytes per, total allocation 49,152 Bytes
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`Updated: 08/27/97 3:24 PM
`
`3.6.3 Protocol Translation
`
`Protocol translation is performed by the core bridge code. This involves the translation of a CDB
`(Command Descriptor Block) being converted between SCSI and FCP. Generally, the structure of the
`CDB is the same in both cases. Changes to the CDB may have to be made to the LUN field when LUN
`addressing is required. The structure of the FCP_CMND and CDB is shown in Table 3.1and Table 3.2.
`
`Table 3.1 - FCP_CNMD Information Unit
`
`
`
`—M'-II_
`
`
`
`
`
`
`
`FCP DL
`
`
`
`scsr Command Descritor Block
`
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`Updated: 08/27/97 3:24 PM
`
`3.6.4 Address Translation
`
`By default, the bridge will address in ‘Direct Addressing Mode’ with the mapping shown in Table 3.3 and
`Table 3.4. Configuration will allow for FC AL_PA to be changed, however, the LUN value will map
`directly to the SCSI LUN. Configuration will also allow for specific SCSI target addresses to be disabled.
`This reduces the range of available addresses, but allows for attaching other devices to the SCSI bus.
`
`Table 33- Default Direct Address Map, FCP->SCSI 0‘1arrow)
`
`FC Address Verrazano AL PA
`SCSI Address
`SCSI Taret 0, LUN 0
`
`
`SCSI Tar_et l, LUN 0
`
`
`SCSI Taret 2, LUN 0
`
`
`
`SCSI Tar_et 0, LUN 1
`
`
`
`SCSI Tar_et 7 Unavailable Brid_e Initiator ID
`
`Table 3.4 - Default Direct Address Map - SCSI->FCP (Narrow)
`
`SCSI Address
`SCSI Tar_et 0, LUN 0
`SCSI Tar_et 1,LUNO
`SCSI Tar-et 2, LUN 0
`
`SCSI Tar_et 7 Unavailable Bride Initiator ID
`
`FC Address
`L PA 0, LUN 0
`L PA 1, LUNO
`L PA 2,LUN 0
`
`L PA7,LUNO
`L PA8,LUNO
`AL PA9,LUN 0
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`Optionally, Ordered Addressing mode can be enabled. This mode will perform discovery on the SCSI side
`of the bridge, and use the resulting data to build an address map between the busses. This results in an
`ordered list of addresses with no apparent gaps between devices. Although this provides automatic
`configuration, no allowance is given for hot plugging devices or any dynamic change of addressing.
`Example tables are shown in Table 3.5 and Error! Reference source not found..
`
`Table 3.5 - Ordered Address Map, FC->SCSI
`
`N‘h discovered BUS:SCSI TARGETzLUN
`
`SCSI Address
`1“ discovered SCSI BUS:TARGET:LUN
`2nd discovered SCSI BUS:TARGET:LUN
`3rd discovered SCSI BUS:TARGET:LUN
`
`A maximum of 128 translation elements are required for each direction. This is the maximum number of
`logical units that can be addressed. This is determined by using the maximum number of usable SCSI
`targets times the number of LUNS. Wide SCSI allows 16 SCSI IDs, one of which must be used as the
`bridge initiator ID. Each target can address 8 LUNS.
`
`Each FC->SCSI entry is 7 words. Each SCSI->FC element is 8 words. Thus, the total required memory
`for address tables is 7200 bytes. These tables will reside in local 960 memory.
`
`3.6.5 Program Structure
`
`Three primary elements are defined for core bridge functionality. These are the SCSI driver, the FC driver,
`and the bridge code.
`
`BRIDGE
`
`(VBRIDGED)
`/
`\
`\
`
`/
`
`/
`SCSI Driver
`
`(SCSILIB.O)
`|
`l
`Interphase
`TPI/Tachyon
`
`\
`
`FC2 Driver
`
`(FC2LIB.O)
`|
`I
`Symbios
`875 SCSI Controller
`
`Bridge internals
`----------------
`
`.
`
`Future Support of FC2 to Other Architectures
`
`C RD S 1 6 1+ 39
`
`In the future, FC2 may be bridged to other Arch. like ATM, ESCON, LAN, etc. In order to facilitate the
`porting of the Verrazano to other platforms the bridge is made up to 2 components:
`
`0
`o
`
`FC2 interface handler
`FC2 to SCSI conversion
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`For performance reasons, these 2 components are in the same source file BRIDGEC.
`
`Code that does the SCSI conversion is #IFDEFed with #IFDEF SCSI.
`
`3.7 Ethernet Driver
`
`WindRiver currently has plans to supply the Epilogue driver for the AMD LANCE Ethernet chip.
`This can be modified to support the PC-NET chip in LANCE compatibility mode, or more likely,
`to
`support DMA master operations.
`
`3.8 Configuration
`
`Verrazano will require configuration for various reasons. The prototype device will allow
`configuration though the serial interface and SNMP. Ethernet via TELNET will be implemented in a
`subsequent release. Subsequent releases will further support SNMP and potentially HTTP, FC and SCSI
`interfaces.
`
`3.8.1 Configurable Options
`
`A number of configurable parameters are required. They are listed below, and grouped into major
`categories.
`
`3.8.1.1 FCP Options
`
`0 Use/Set Hard Address (AL_PA)
`o
`Participate if Hard Address unavailable
`0
`Override World Wide Address (IEEE)
`
`3.8.1.2 SCSI Options
`Set [D for SCSI Initiator
`
`Use multiple SCSI response IDs
`Set IDs for SCSI Target response
`Set general SCSI parameters (fast/disconnect/sync negotiation/etc.)
`Set SCSI Narrow/Wide
`Use CDB LUN field
`
`3.8. 1.3 Bridge Options
`0
`Use Direct Address Method
`
`Specify/Enter Address Map
`0
`Use default Address Map
`0
`Use Ordered Address Method
`
`0
`
`Perform FCP Discovery
`0
`Perform SCSI Discovery
`0
`0 Use Target Addressing (LUN 0 Only)
`0
`FCP Target Addressing
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`0
`0
`
`0
`
`SCSI Target Addressing
`0
`Set Management Command method (LUN 0, LUN FF, Group Code, Disable)
`Select FCP LUN format
`
`Set Buffer Memory parameters
`0 Data Buffer Size
`
`0
`0
`
`Set Tachyon list parameters
`Set Symbios list parameters
`
`3.8.1 .4 Miscellaneous
`
`0 Override Ethernet IEEE address
`
`Set default serial parameters
`0
`0 Disable diagnostics
`
`3.8.2 Serial Console
`
`The Serial Console will provide for:
`0 Menu based configuration
`0 Statistics reports
`0 EEPROM Download
`
`0 Debugging VxWorks Interface
`
`3.8.3 Telnet
`
`Access to the same options and control given through the serial interface will be provided through
`Ethernet based TELNET in future release.
`
`3.8.4 FTP
`
`Firmware download will be provided through Ethernet FTP.
`
`3.8.5 SNMP
`
`MIB based configuration and statistics via SNMP (Ethernet, future FC—IP)
`
`3.8.6 HTTP
`
`Configuration, management available via H ['1 P in future release.
`
`3.9 Management
`
`3.9.1 SNMP
`
`MIB-II compliant private MIB defined in Crossroads CP4100 SNIVIP document.
`
`3.9.2 HTI’P
`
`TBD, in future release
`
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`4. Diagnostic Test Software
`
`Diagnostics will be nm on power up, as well as started through the serial and TELNET interface. Future
`updates may allow diagnostics through SNMP, SCSI, or FCP interfaces. Diagnostics will halt all bridge
`activity, and will leave the bridge in a power on condition. A configuration option will be provided to
`enable or disable diagnostics other than at power reset,
`to help to prevent inadvertent data corruption.
`One base test suite is desired. covering:
`0 Manufacturing Test
`0
`Field Test
`0
`Return Test
`
`4. 1 Diagnostic Tests
`
`Processor/Program memory
`Data paths
`Tachyon
`875
`
`Buffer memory
`Peripheral components
`
`Data path test - The data path (usually a bus) is tested for single (and most multiple) stuck-at faults,
`bridging faults, and stuck-open faults.
`RAM pattern test - In addition to data path tests, pattern sensitive faults are tested. Patterns include
`alternating 0’s and Fs, 55. .. and aa. . .. These patterns involving switching the most bits in a word and tend
`to expose noise problems caused by switching. A random pattern is also used. This will expose any other
`faults that may not be covered by other patterns.
`
`’
`
`4.1.1 Initial boot
`
`0 Verify Mode 3 reset bus confidence self-test
`0
`Processor reads initial memory image (see RP User’s Manual, Ch. 11). The IBR, PRCB,
`NMI vector, and Control Table loads.
`
`4.1.2 LED visual test
`
`I
`
`A sweeping pattern is generated on the LEDs to be visually inspected. The LEDs are used in
`later stages of the bringup test to indicate the current stage of the test. Should a failure occur
`any time during the bringup test, the LEDs will indicate the last test being performed in which
`a failure is detected.
`
`4.1.3 Flash Memory - Read test
`
`0 Word read of preprogrammed data and verify against pre-computed checksum.
`
`4.1.4 Instruction Memory - Read/write test
`
`Walking 1 word write/verify on address bits
`Walking 0 word write/verify on address bits
`Walking 1 word write/verify on data bits
`Walking 0 word write/verify on data bits
`Incrementing word count (address) write/verify on data bus
`B
`'t /
`'f
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`QTTDRNEYS'
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`0 Quad-word write/verify
`o
`l-byte alignment Quad-word write/verify
`o
`2-byte alignment Quad-word write/verify
`o
`3-byte alignment Quad-word write/verify
`
`4.1.5 Serial Controller - read/write test
`
`All read/write bits of the controller’s registers are tested
`The controller is put into internal loopback mode and characters are wrapped through the
`contoller and verified
`
`A PC or dumb terminal is connected to the serial port. A terminal session is started and a test
`message is sent to the terminal emulator to verify transmission by the controller
`The 960 is programmed to echo input characters and echo test is performed from a terminal
`emulator
`
`0
`
`-
`
`I
`
`1. Verify operation of MON960 through serial port
`
`4.1.6 Ethernet Controller - read/write test
`
`4.1.7 PCI Memory ReadMIrite Test
`
`Walking 1 word write/verify on address bits
`Walking 0 word write/verify on address bits
`Walking 1 word write/verify on data bits
`Walking 0 word write/verify on data bits
`Incrementing word count (address) write/verify for entire memory (4 M)
`Incrementing word count (address) writes with 100 ms delay before verify (verifies refresh
`circuitry)
`Incrementing byte count (address) write/verify (verifies byte accessing)
`Incrementing word count (address) for every multiple lK-l word location (verify end of dram
`row accesses work). This should also verify that surrounding words remain unchanged.
`Incrementing word count (address) for every multiple lK-Z word location (verify end of dram
`row accesses work). This should also verify that surrounding words remain unchanged.
`Incrementing word count (address) for every multiple lK-3 word location (verify end of dram
`row accesses work). This should also verify that surrounding words remain unchanged.
`Incrementing byte count (address) for every multiple 4K-1 byte location (verify end of dram
`row accesses work). This should also verify that surrounding bytes remain unchanged.
`Incrementing byte count (address) for every multiple 4K-2 byte location (verify end of dram
`row accesses work). This should also verify that surrounding bytes remain unchanged.
`Incrementing byte count (address) for every multiple 4K-3 byte location (verify end of dram
`row accesses work). This should also verify that surrounding bytes remain unchanged.
`
`o
`
`0
`
`0
`
`0
`
`0
`
`-
`
`4.1.8 Tachyon
`
`-
`
`Register Test
`
`4.1.9 Symbios 875 SCSI Controller
`0
`Register tests
`self test
`
`0
`
`data path test
`
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