1 of 32
`
` CROSSROADS EXHIBIT 2317
`Oracle Corp., et al v. Crossroads Systems, Inc.
` IPR2014-01207 and IPR2014-1209
`
`CROSSROADS EXHIBIT 2317
`NetApp Inc. v. Crossroads Systems, Inc.
`IPR2015-00773
`
`

`

`_Verrazano Hardware Architecture
`
`Revision 2.1
`
`The infomntion contained in this document has been carefully checked and is believed to be entirely
`reliable. However. no responsflaility is assumed for inaccuracies. Furthermore, Crossroads Systems. Inc",
`reserves the right to change this document and product without notice and to make improvemcus in
`reliability, fiinction and design without notice. Crossroads Systems, Inc... neither assumes any liability
`arising out of the application or use of any product, software or circuit described herein, nor does it convey
`any license under its right or the rights of others. Companies, names, and data used in examples herein are
`fictitious unless otherwise noted. No part of this document may be reproduced or transmitted in any form
`or by any means, electronic, mechanical, for any purpose, without the express written permission of
`Crossroads Systems, Inc..
`
`© 1997 Crossroads Systems, Inc.. All rights reserved.
`
`Crossroads Systems is a trademark of Crossroads Systems, inc... in the USA and other countries.
`
`Copyright © 1997
`Crossroads Systems, Inc..
`Building 1, MS 225
`6101 West Courtyard Drive
`Austin, Texas 78730
`
`Fax:
`
`(512) 349-0300
`(512) 349—0304
`
`info@crossroads.eom
`support@crossroads.com
`http://www.crossroads.com
`
`Printed in the United States of America.
`
`ATTORNEYS '
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`Verrazano Hardware Architecture
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`Revision 2.1
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`Revision Histo
`Revision
`
`
`Descrition
`
`9/21/97
`
`-
`
`.
`
`John Middleton
`
`
`
`
`The information contained herein is confidential in nature and is to be used only with written permission
`from Crossroads Systems, Inc.
`
`
`
`This document is only valid on the date printed. Please see the document author for information about the
`latest revision.
`
`ATTORNEYS‘
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`Verrazano Hardware Architecture
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`Revision 1.0
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`Crossroads Systems Confidential Material
`
`1.
`
`1.1
`
`2.
`
`INTRODUCTION ................................................................................................................... 6
`
`Related Documents ........................................................................................................... 6
`
`HARDWARE ......................................................................................................................... 6
`
`2.1
`2.2
`2. 2. 1
`2.2.2
`2.2.3
`2.2.4
`2.2.5
`2.2.6
`2.2. 7
`2.2.8
`2.3
`2.3.1
`2.3.2
`2. 3. 3
`2.3.4
`2.3. 5
`2.3.6
`2.4
`2.4.1
`2. 4.2
`2.5
`2.5. 1
`2. 5.2
`2.5.3
`2.5.4
`2.6
`2.6.1
`2. 6.2
`2.6.3
`2.7
`3.
`
`Architecture .........................................................................'............................................... 6
`Component Comparison Notes.......................................................................................... 7
`Processor.................................................................................................................... 8
`Serial Port ................................................................................................................... 8
`Ethernet Port............................................................................................................... 8
`Fibre Channel Port...................................................................................................... 9
`Memory..................................................................................................................... 10
`SCSI Port.................................................................................................................. 13
`
`General Components...................................................................................... 14
`
`Peripheral I/O............................................................................................................ 16
`.
`Enclosure ...........
`............................................................................. 17
`Features.................................................................................................................... 1 7
`Implementation Standards........................................................................................ 1 7
`Color Scheme ........................................................................................................... 1 7
`. Finish ........................................................................................................................ 17
`Interim Front Bezel ................................................................................................... 18
`Molded Front Bezel................................................................................................... 18
`System l/O Panel ............................................................................................................. 18
`Panel Cut-outs .......................................................................................................... 19
`Labels ....................................................................................................................... 19
`Mechanical Features ......................................................................... ............................... 19
`
`Air flow assumptions ........................................................................................ 19
`
`Electromagnetic Shielding ............................................................................... 19
`
`Desk Top.......................................................................................................... 19
`
`Rack Mounting ................................................................................................. 19
`Enclosure Components .................................................................................................... 19
`
`' Fan .................................................................................................................. 20
`Power Supply.................................................................................................. 20
`Printed Circuit Board....................................................................................... 20
`Assembly Considerations ................................................................................................ 20
`ENGINEERING DATA ........................................................................................................ 20
`
`3.1
`3.2—
`3. 2. 1
`3.2.2
`3.2.3
`3.2.4
`3.3
`4.
`
`Standards ......................................................................................................................... 20
`Hardware System.......................................................................................................... 21
`
`Nonvolatile storage ......................................................................................... 21
`
`Interrupts......................................................................................................... 21
`
`Local bus................................................ 22
`
`Ethernet PCI Bus ........................................................................................... 22
`
`Memory Map .......................................................................................................... 22
`PROGRAMMING CONSTRAINTS ..................................................................................... 25
`
`4.1
`4.2
`4.3
`4.3.1
`4.3.2
`4.4
`4.5
`
`960RP .............................................................................................................................. 25
`
`PCI Dram Access .................................................................................................... 25
`
`Supervisory Space Registers.............................................................................. 26
`
`Initial Memory Image (IMI) .............................................................................. 26
`
`
`Other Supervisory Space Registers ............................................................... 27
`Timers .............................................................................................................................. 27
`Integrated Peripheral Registers
`QTTDRNEYS .
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`ATU Registers ...................................................................................................... 28
`4. 5.1
`
`Memory Controller ...................
`4.5.2
`Inten'upt Controller.................................................................................................... 30
`4.5.3
`DIAGNOSTICS .................................................................................................................... 30
`
`5.
`
`5.1
`5.2
`5.3
`5.3.1
`5.3.2
`
`5.3.3
`5.3.4
`
`Diagnostics Monitor ......................................................................................................... 31
`VxWorks Diagnostics Task .............................................................................................. 31
`Common Diagnostics Utilities .......................................................................................... 31
`Pattem Generator..................................................................................................... 31
`Pattem Verifier.......................................................................................................... 31
`
`Register Walking bit tester........................................................................................ 32
`Code Downloader and Flash programmer... ............................................................ 32
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`Verrazano Hardware Architecture
`
`Revision 1.0
`
`Crossroads Systems Confidential Material
`
`'
`
`1. Introduction
`
`This document details the hardware architecture of the CrossPoint 4100 (code named Verrazano).
`
`1. 1 Related Documents
`
`Information neceSSary to use the product is presented in the CrossPoint 4100 Reference Manual, the
`softcopy of which is stored in “\UnfmitySouree\Verrazano\doc\ref_manual.doc".
`Reasoning behind design decisions and certain design details deemed proprietary are described in the
`Strategic Specification, the softcopy of which is available in
`“\\Infinity\Souree\Venazano\doc\suat_spec.doc".
`The Statement of Requirements is available at “\\lnfinity\Source\Vetrazano\doc\reqhequirernentsdoc“. and
`describes the functionality goals of the product.
`
`2. Hardware
`
`Verrazano is an embedded system that provides connectivity between Fibre Channel devices and SCSI
`devices. The hardware subsystem is comprised of an embedded 80960 RISC controller, a programmable
`SCSI controller, 3 Fibre Channel controller, an Ethernet (802.3) controller, and a serial port. Various other
`components are present to support operation ofthe system sofiware. The design of Vertazano is optimized
`to support data flow between the Fibre Channel and SCSI controllers, and support out of band connections
`via the Ethernet or serial ports. The 80960 controller has its own pregram execution memory space to
`achieve parallelism with the data flow between the Fibre Channel and SCSI controllers.
`
`2. 1 Architecture
`
`The main controller of the system is an i960RP processor running VxWorlcs and handles the necessary
`protocol conversions to transfer data between the Fibre Channel and SCSI connections.
`
`The Verrazano architecture is Summarized in Figure l. Verrazano hardware platform architecture.
`
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`Fibre Channel
`
`SCSI Bus
`
`40 MHZ
`
`Tachyon
`
`Dtfiefemial
`Transceivers
`
`SYM530875
`
`®
`80MHz
`
`®
`
`20 MHz
`
`-TP
`PClBus-
`
`80960RP
`
`960 Local Bus
`
`Memory
`
`Controller
`
`33%
`
`FLASH
`
`Serial
`controller
`
`
`
`Ethernet
`Controller
`
`_ _
`
`CL)
`
`18. 32
`MHz
`
`Filters
`
`RS-232E
`
`1OBaseT
`
`Figure 1. Verrazano hardware platform architecture.
`
`2. 2 Component Comparison Notes
`This section describes in more detail the components used in the system.
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`2.2.1 Processor
`
`The central controller in the system is an 80960RP processor. It contains an integrated JF core, a PCI-PCI
`bridge, and a local 960 bus. It is packaged in a 352-pin Ball Grid Array which requires a special process to
`properly attach it to the board.
`
`The 80960RP controls all the functions (modules) in the Verrazano product. The 80960RP controls the
`operation of the Fibre Channel port and SCSI port through its secondary PCI bus. The 80960RP controls
`the operation of the Ethernet port through its primary PCI bus. The 80960RP coutrols the operation of the
`serial port through its local bus.
`'
`
`2.2.2 Serial Port
`
`The industry standard 16550 UART is used. This component converts serial to parallel conversion on
`characters.
`
`
`
`
`
`
`———IE-
`
`___li-
`
`
`
`
`2.2.2.1 Transmitter/Receiver
`
`A general RS-232 serial port needs 3 drivers and 5 receivers, a typical PC configuration. For Verrazano
`implementation with the RJ-l 1, only 2 drivers and 2 receivers are needed.
`
`2.2.2.2 Serial Controllers
`
`The serial controller resides on the 960 local bus. Support components: EIA drivers for RS-232 line,
`7.3728 MHz crystal, 245 iii-directional transceiver, address decode logic. address latch (shared with
`FLASH).
`
`2.2.2.3 Serial Connector (RJ-11)
`The serial connector used is a shielded filtered RJ-ll connector.
`
`‘
`
`2.2.3 Ethernet Port
`An Ethernet controller is used that connects to the 960RP primary PCI bus.
`
`2.2.3.1 Controller
`
`The Ethernet controller provides a bus master interface and supervises the Ethernet port.
`The part used for this function is the AM79C970A.
`
`2.2.3.1.1 Ethernet Controller Interface Design
`
`2.2.3.1. 1. 1 Software Requirements
`Operating assumptions and restrictions on the software are listed.
`1. The sofiware relocation strategy for the AM79C970A is used to setup the base address. This means
`the address on the bus following the first access to address 0x378 sets up the base address. The base
`address must be set to 0xC000_0000 based on the mask OXEOOO_OOOO.
`2. Only word accesses are allowed.
`ATTORN
`'
`3. All DMA transfers must start on a word boundary.
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`2. 2. 3. 1. 1.2 Hardware Structure
`
`The Ethernet controller chip uses the 960R? Primary PCI bus to communicate to the processor.
`
`2.2.3.2 Transceiver/Filter
`
`A Valor FL1043 Ethernet filter module is used.
`
`2.2.3.3 Connector (RJ~45)
`The Ethernet connector is a pin through hole RJ-45 shielded connector.
`
`2.2.4 Fibre Channel Port
`
`The functionality of this port is based on Tachyon/TF1 capabilites.
`
`2.2.4.1 Tachyon Controller
`The Tachyon controller chip provides all Fibre channel protocol support. Tachyon interrupts are mapped
`through the TH chip (see that section for details). Tachyon must be configured for a maximum write
`stream size of 16.
`
`See the lip TACHYON specification for details on this component.
`
`2.2.4.2 in chip
`This is an ASIC manufactured by Interphase that is designed to interface Tachyon to a PCI bus. it consists
`of several FIFOs to buffer operations between the bosses. The Tachyon bus can run at 4OMHz.
`it provides
`write post buffering.
`0
`0 wait state as PCI master
`0
`5 volt part
`0
`programmable PCI burst
`0
`IEEE address from serial EEPROM. It is optional. A central non-volatile element in Verrazano will
`store all appropriate unique information.
`Provides byte swap
`
`0
`
`TPI optionally requires 93C46 serial EEPROM to store contents of serial EEPROM. 64 bytes of extra
`information can be stored. External PCI master can modify EEPROM contents. PCI protoc01 and TPI
`registers should be examined to determine if EEPROM can be omitted. See data list on p. 38 of Rev. B TPl
`spec.
`The following PCl configuration registers are read only. Their values can only be loaded with a serial
`EEPROM. Based on this list, there is no need for a serial EEPROM to support TPI.
`Vendor ID
`Device lD
`
`Revision (each 'I'Pl rev should increment this)
`Class code
`
`Header type
`8181"
`
`cans 151.00
`
`CIOOOOOOOI
`
`
`
`
`Subsystem vendor 1D
`Subsystem 1D
`Interrupt register (default value indicates interrupt A)
`Min_Gnt (not used)
`Max_Lat (not used)
`TP r—u
`does not re ~ nd to interrut acknowled - e command Interrupts shall be mapped as:
`Iflflflllflflflflllllllllllliflflflfifll
`
`S INTA
`PINTA
`
`
`
`
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`
`- TSI bus timeout, parity error.
`
`PCI bus errors
`
`Design Requirements
`Pull RAMI'EB' high as perTPl errata fix 0.
`Programing: configure both DMA channels to use byte swapping, as per errata 2 for 'I'PI.
`
`2.2.4.3 Fibre Channel Media
`
`The connector is GLM based. See the GLM specification for details. This allows flexibility on choosing
`which media is needed. The supooned GLM types are:
`0
`Copper
`0
`Short Wave Optical
`-
`Long Wave Optical
`
`2.2.5 Memory
`
`2.2.5.1 RP Memory controller
`The RP memory desigt consists of 4Mbyte of DRAM. Parity is not implemented.
`
`'lhe RP does support up to 256MB 32-bit/36—bit DRAM that is Extended Data Out (EDO)/fast page.
`Drives row-address Strobes (320), column access Strobes (7:0). and write enables (1:0). DRAM refresh
`provided as CAS before RAS. Only 4 Mbyte is used on the design.
`
`2.2.5.2 PCl memory controller
`
`The PC! memory design (Gamer) consists of 4M'byte of DRAM plus parity.
`
`It is implemented as custom logic with a PLD. It supports 3-O—0~0—... read access (not including one cycle
`on the PCI bus for address turnaround). It also supports l-O-O—O-... write accesses (unless doing non-word
`write access).
`. The DRAM is EDO/fast page mode, lMxlé. . The extended data out implementation
`requires one bank of memory to achieve the zero wait state performance. There are 3 DRAM chips used
`for the bank of memory which includes two chips {or neural data and One chip for parity.
`.
`
`The design is implemented in an Altera FLEX 10K part (lOKlO—3). All buffers and logic are contained in
`a single package, for ease of design. The Alters tools allow for better control over timing than discrete
`parts.
`
`A smaller PAL device is also used (16v8-5) which runs from a 66Mhz clock. This device is used to give
`better control over the CAS signals to the dram. Faster CAS signals basically give faster data access times.
`
`2.2.5.2.1 System Description
`
`A representative diagram of the PCI memory controller is shown below.
`
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`
` g
`
`owmtmrm
`
`PCI
`
`1.W m =fl I
`PC!may" - l
`EJ"
`
`per AOIJI. m
`
`S
`
`J"
`
`pcmmm
`
`J—
`
`U
`
`PC1 AD“! .2]
`
`g
`
`'L
`
`?
`
`DRAM Dummy
`
`ow won 9 to
`
`PCl wane]
`ch Benn]
`PC! PAR
`
`PCI PERR
`
`
`
`Figure 2 PC! Memory Controller Architecture
`
`21.5.2.2 Functionalrtleonstramts
`
`CRDS 15403
`
`2. 2. 5. 2. 2. 1 Gamer DOES support
`Gamer implements a subset of the PCI functions that are allowed These are the fimctions that Gamer
`DOES support (not an exhaustive list):
`- memory read and write cycles including read multiple, cache write and invalidate, and read line
`(although their function is equivalent to the read and write cycles)
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`
`partial address decode (dram responds to pci data bit 31=0)
`non word access (including zero byte access)
`linear address sequencing (pci add: bits 0 and l are assumed to be 00)
`generates parity during data read cycles
`checks parity during data write cycles and generates valid PERR
`address bursting (along a 1K word row address)3-0oO-O-... burst access
`support for up to 4 M of dram ([0 address lines and 4 CAS lines)
`Decades bit 32 of address to determine if being addressed
`
`00......
`
`2. 2. 5. 2. 2.2 Garner does NOTsupport
`
`Garner implements a subset of the PCI functions that are allowed These are the fimctions that garner does
`NOT support:
`.
`configuration cycles (a target abort will be generated)
`interrupt acknowledge cycles (a target abort will be generated)
`dual address cycles (a target abort will be generated)
`I/O cycles (a target abort will be generated)
`lock function
`
`parity checking on address cycles
`initiator mode functions (gamer is strictly a target)
`full address decode (only PCI data bit 31 is used)
`nonlinear address sequencing (ie. PCI add: bits 0 and 1 not being equal to 00)
`does not respond to SERR. LOCK, IDSEL signals (no connections to these signals)
`
`0
`
`2.2.5.2.3 Dram latency
`Reads are 3-0-0—0...
`Writes are 1-0-0—0...
`
`Non-word writes require an extra 5 wait states. This is due to having a single parity dram. The parity bits
`must be read back from the dram, modified and written back.
`
`2.2.5.2.4 Device package
`
`_
`Device package is PQFP-208
`Note: This device type and package is available in the FLEXlOKIO, 10K20, 10x30 devices..
`
`2.2.5.2.5 Clock distribution to garner
`Garner uses an inverted 33 Mhz clock signal from the clock distribution network.
`Thedesign makes use of the fact that both the inverted and non-inverted clk signals are available to internal
`registers on the chip. The chip inverts whatever clock is supplied to it and makes that signal (as well as the
`original clock signal) available to internal registers. This allows some signals to be generated lSns earlier
`than normal. Running registers off both edges of the clock emulates 66Mhz operation for some signals.
`
`'
`
`We chose to use the inverted clock (rather that the true form) because I/O registers on the chip have only
`the clock supplied available to them (ie. not both the inverted and true). Since most of the critical signals
`are generated with the neg edge of the clock, the inverted signal goes to the U0 registers. The internal
`registers still have the option of using either version of the clock.
`
`2.2.5.2.6 CAS pal
`A faster PAL is used to implement the CAS signals to the DRAM. The pal uses a 66 Mhz clock to
`implement the CAS pulses. The enable signals for the pal come from the PCT Memory Controller chip.
`
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`
`2.2.5.2.7 Device lnitlalization
`
`The FLEX 10K devices are SRAM based, so they must be configured (loaded with a program) at power-on.
`The “ConfiguratiOn EPROM" scheme is used to load the configuration. The lOKlO part needs 1 15,000 hits
`of configuration information Future enhancements could implement Garner configuration with the
`microprocessor.
`
`'Ihe serial EEPROM is the Altera EPICl in a DIP-8 package. It contains an oscillator which makes it easy
`to work with.
`
`2.2.5.3 SRAM
`
`No SRAM will be used on this design.
`
`2.2.5.4 FLASH
`
`The AMD 29F016. It is a 2Mbyte part (1 byte wide). The AMI) programing algorithm must be used
`when programming this part.
`
`2.2.6 SCSI Port
`
`Note: The Fast-20, P connector imply SCSI-3 Parallel Interface standard is being used. The SPl, Annex
`II, defines a SCSI graphic symbol that denotes if the port is single ended or differential. P-cable is the 16—
`bit wide data/control cable/port defined in SCSI-3. The optional Q cable adds another 32 bits of data. This
`is not implemented because the 53C875 does not support this mode. A shielded connector is used:based on
`the external connection and EMC/ESD considerations. The SCSI-3 connector (jack) is defined in Figure 6.-
`p. 11 of SPI, rev 153. Cable retention is with two 2-56 screws. Shield is DC connected to enclosure. The
`standard (SPI, rev 153., p. 8) recommends having two shielded connectors. with internal connections.
`
`The physical interface and differential drivers will be contained on a daughter card. This card is the SCSI
`Interface Board (SIB). The differential version is the primary SCSI bus interface. A single ended SIB will
`consist of pass through wiring, as the Symbios 53C875 contains the single ended drivers. Since port is
`differential, twisted pair cable should be used for a maximum length of 25m. Also, it should be shielded
`since used external. Terminator pOWer source needs protection circuits, as per SP1, p. 23. The PCB will
`contain an header connector, and a jumper cable will connect the panel mounted external connectors to the
`PCB. Note that power requirements of SCSI-3 for TERMPWR is greater than SCSI-2. Therefore, at least
`'one SCSI-3 device must supply power. Verrazano will supply the power as it may be the only SCSI—3
`device on the bus. See notes in Annex C of SP1. To convert from P cable to A cable (SCSI-2 8-bit cable).
`additional termination requirements are needed. Consider if Verrazano terminators can be wired to support
`termination requirements of cable conversion as per Annex C. p. 66, SP1 rev 153.
`
`Skew and propagation delays for SCSI wiring is defined in Annex E of SPI. Ven-azano wiring must follow
`these guidelines. SCAM protocol support is to be determined.
`-
`
`2.2.6.1 Controller
`
`The design is constrained to use Symbios Logic 53C875 SCSI controllers.
`
`2.2.6.2 SYM53C875
`
`Refer to the Symbios SYM53C875 for details.
`
`2.2.6.3 SCSI Interface Board
`
`QTTORNEYS '
`EYES ONLY
`
`CRDS 16404'
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`The 53C87S has integral single ended drivers. To implement the differential interface on Verrazano,
`external drivers are needed. The driver circuitry is contained on the SCSI Interface Board (SIB). which
`allows the Verrazano product to be configured with a differential or single-ended interface by populating
`the appropriate SCSI Interface Board. A drawing sib_card.dwg) defines the dimensions of the SB card.
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`The differential version contains terminating resistors and drivers, plus the connectors. The Single-ended
`version contains only connectors.
`
`2.2.6.4 Termination
`
`An Active termination required on all 16 data lines for SCSI-3.
`
`2.2.6.5 Connector
`
`A vertical orientation header is used on the SIB card. Fooqm'nt defined in AMP document 114—40029,
`“Amplimite .050 Series Connectors...”, p. l4. Pay special attention to “ACTION PIN" contact5, dimension
`of plated hole important. For board thiclmess of 0.062", use contact tail lengths on ACTION PINS of
`4.39m (0.093).
`
`2.2.7 General Components
`
`2.2.7.1 Clock Distribution
`
`Clock oscillators are used: higher cost, lower design effort. A standard size footprint is used for all clocks.
`The system clock (33MHz) is driven through a PLL clock buffer.
`Use an SOME: clock to derive 40MHz. The ZOMHZ needed by Ethernet is derived from a 20 MHz crystal.
`There are three choices for clock distribution: standard buffers wired in parallel (below 20 MHz), single
`input-multiple output buffers with skew matched gates, and PLL based buffers. The PLL buffers offer
`lower skew 'and can be used to build multiple part buffer trees with vinually zero propagation delay. The
`single chip bufferis suitable for fanout up to 10 devices.
`For Verrazano, a PLL bufferis used for the 33/66 MHz signals. It can be generated from a single 33Mllz
`source, and the phase alignment of the outpus is very good. Primary need15 for the 66 MHz clock to be
`skew controlled with the 33 MHz clock.
`The clock distribution trees are shown in . Skew is limited to 1 n8.
`
`
`
`Gamer-FLA
`
`Garner
`
`Ethernet
`
`960RP
`
`
`
`scsr Chip
`
`
`TH E
`Tachyon
`
`GLM
`
`E
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`Figure 3. Clock distribution trees.
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`ATTORNEYS'
`EYES ONLY
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`CRDS 16
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`2.2.7.2 Crystal/Clock Specifications
`
`2.2.7.2.1 Crystals
`Note that “970 Ethernet controller requires a CMOS level input for a clock, so it cannot be driven from a
`PLL bufferfl'hercfore a
`stal is used
`
`lam—M
`73728 MHz
`20.0mm
`
`
`
`
`
`mC
`
`alibration Tolerance:
`
`islun at 25°C W
`10m0-70 °C
`wum 0-70°C
`
`
`
`7 .FMax
`A i
`n—W-T—
`O-ImW
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`
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`
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`2.2.7.2.2 Clocks
`
`A PLL (phase lock loop) is used to generate the 2X frequencies. This saves the cost of the high frequency
`oscillators, and facilitates the move to custom oscillators in the future. All clock oscillators use a common
`O.200x0.300 foo mm.
`
`
`s stcmzs
`33.000er
`
`SCSI 40
`40.000MHz
`
`_:xo--me70°c
`.
`
`FO uU) E
`
`
`
`
`E
`
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`C (I)
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`M 5-75%
`
`nSMIN
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`-EE
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`
`
`
`
`U0 U)
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`
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`2.2.7.3 Reset Circuit
`
`The reset subsystem is shown in . The reset signal generation is accomplished by the 1232 supervisory
`circuit. This is an industry standard product that generates a 250 m5 reset pulse on power-on, when
`detecting a low power condition, when a manual switch is pressed, or when a watch dog timer expires. The
`watch dog timer monitors the systems for inactivity.
`.
`
`For production, the push button switch will not be populated.
`
`ATTORNEYS '
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`’
`
`Reset Pulse
`timer Serial port
`
`960RP——<:
`
`Ememet
`
`TPl -——~———— Tachyon
`
`‘
`
`SCSI Chip
`
`10% below Vcc
`detect
`
`SOOmS watchdog
`
`250 m5
`
`Figure 4. Reset subsystem.
`
`2.2.8 Peripheral IIO
`The peripheral [/0 provides a real time clock and debug interfaces (LEDs and LCD).
`Only word accesses are supported. Each device is an 8-bit device, mapped to the least significant byte of
`the word.
`
`2.2.8.1 Real time clock/calendar
`
`.
`
`A PC industry standard real time clock is included. It is referred to as the “calendar" throughout the
`documentation to distinguish it from the clock oscillators.
`
`This clock module contains an integral oscillator and battery with a lifetime of 10 years. It contains 1 14
`bytes of RAM and 14 bytes of clock data mapped as registers. Each byte is mapped to a word boundary.
`and only 8 address bits are available. Thus, only the first 64 bytes of the calendar are accesstble.
`
`2.2.8.2 LCD Interface
`
`A standard 16 character by 1 line LCD display is included. Two word addresses are used to write character
`and command data to the display. The interface is a standard 14-pin interface, which could support
`multiple line displays if desired. This interface is included for debugging, and is not intended to be
`installed in the final product. However, a mechanical modification to the enclosure is needed to include the
`LCD interface.
`
`2.2.8.3 LED Interface
`
`An'S‘bit register is used to control the output of the LEDs. These are debugging aids, and are mounted on
`the board. The upper 4 bits are green, the lower 4 are orange. (This is subject to change based on
`availability of LEDs). The LEDs are active low. i.e. write a 0 to a bit turns on the LED.
`
`W
`2.2.8.4 Address Mapping
`The peripheral 1/0 is connected to the 960 bus Ming extra logic in Gamer, the DRAM controller. The byte
`re - isters are um 31' d to word boundaries. Use normal word accesses to these registers.
`
`
`—m§§§_ c axes to access
`.
`.
`
`
`.-
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`Oxcooo 0300
`
`
`
`
`
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`ATTORNEYS ’
`EYES ONLY
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`The production version will not support all these interfaces, but write cycles will be accepted.
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`.Venazano Hardware Architecture
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`Revision 1 .0
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`Crossroads Systems Confidential Material
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`2.3 Enclosure
`
`A rough drawing ofVcnazano is show in Figure 1. This is the desk top configuration. Rubber “feet" are
`placed on the bottom. The back face contains connectors and the power entry.
`In order to rack mount the
`
`
`
`Mlm—O
`+1”.
`
`Figure 5. Approximate size of enclosure. The depth is 9'. The height and
`width are determined by the p