UNITED STATES PATENT AND TRADEMARK OFFICE
`__________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`___________
`
`ATopTech, Inc.
`Petitioner
`
`v.
`
`Synopsys, Inc.
`Patent Owner
`___________
`
`Case IPR2015-00760
`Patent 6,237,127
`___________
`
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 6,237,127
`
`
`__________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`___________
`
`ATopTech, Inc.
`Petitioner
`
`v.
`
`Synopsys, Inc.
`Patent Owner
`___________
`
`Case IPR2015-00760
`Patent 6,237,127
`___________
`
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NO. 6,237,127
`
`
`
`Petition for Inter Partes Review of U.S. Patent No. 6,237,127
`
`TABLE OF CONTENTS
`
`I.
`
`COMPLIANCE WITH PETITION REQUIREMENTS ..........................1
`
`Certification the `127 Patent May Be Contested By Petitioner ......1
`A.
`Fee For Inter Partes Review (37 C.F.R. § 42.15(a) and § 42.103) ..1
`B.
`C. Mandatory Notices (37 C.F.R. § 42.8) ...............................................1
`
`1.
`
`2.
`
`3.
`
`Real Party-In-Interest (§ 42.8(b)(1))...........................................1
`
`Related Matters and Joinder Motion (§ 42.8 (b)(2))...................1
`
`Lead And Backup Counsel (§ 42.8 (b)(3)) .................................2
`
`4.
`Service Information (§ 42.8 (b)(4)) ............................................2
`Proof Of Service (§ 42.6(e) and § 42.105(a)).....................................2
`D.
`IDENTIFICATION OF CLAIMS BEING CHALLENGED (§
`42.104(B))........................................................................................................3
`III. RELEVANT INFORMATION CONCERNING THE `127 PATENT ....3
`
`II.
`
`A.
`
`Subject Matter of the `127 Patent......................................................3
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`Calculating Delay Values with Timing Table Propagation........4
`
`Tracking “Exceptions” with Timing Table Propagation ............5
`
`“Exceptions” – Non-Default Timing Constraints.......................7
`
`“Pin-Labelling” – Associating the “Exceptions” with the Circuit
`.....................................................................................................9
`
`Comparing the Delay Values in the Timing Tables to the
`Circuit Constraints and Applying the Relevant Exceptions. ....10
`
`B.
`
`Effective Filing Date and Prosecution History of The `127 Patent
`.............................................................................................................11
`
`1.
`
`Belkhale’s Significance was not Recognized During
`Prosecution................................................................................12
`
`i
`
`
`
`Petition for Inter Partes Review of U.S. Patent No. 6,237,127
`
`C.
`
`How the Challenged Claims Are To Be Construed .......................13
`
`IV. PRECISE REASONS FOR RELIEF REQUESTED...............................14
`A.
`Belkhale Renders Claims 5 and 6 and Obvious .............................14
`
`1.
`
`Overview Of Belkhale ..............................................................14
`
`B.
`
`Belkhale Renders Claims 5 and 6 of the `127 Patent Obvious......20
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`6.
`
`Belkhale Teaches the Preamble Of Claim 1 .............................20
`
`Belkhale Teaches the First Element of Claim 1 .......................21
`
`a.
`
`b.
`
`Correct Construction of the First Element of Claim 1 ...21
`
`Belkhale Teaches Marking the Circuit Description with
`Exceptions.......................................................................22
`
`Belkhale Teaches the Second Element Of Claim 1 ..................24
`
`a.
`
`Correct Construction “Timing Tables” ..........................25
`
`Belkhale Teaches the Final Element of Claim 1 ......................27
`
`a.
`
`The Correct Construction of “Tag” ................................29
`
`Belkhale Renders Claim 4 Obvious..........................................31
`
`Belkhale Renders Claim 5 Obvious..........................................31
`
`7.
`Belkhale Renders Claim 6 Obvious..........................................35
`Claims 5 and 6 are Rendered Obvious over Belkhale in view of
`Tom. ....................................................................................................38
`
`C.
`
`1.
`
`2.
`
`Overview Of Tom.....................................................................38
`
`Motivation to combine Tom with Belkhale..............................40
`
`3.
`Belkhale in View of Tom Renders Claims 5 and 6 Obvious....43
`CONCLUSION ............................................................................................54
`
`V.
`
`ii
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`
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`Petition for Inter Partes Review of U.S. Patent No. 6,237,127
`
`TABLE OF AUTHORITIES
`
`Cases
`
`KSR Intern. Co. v. Teleflex Inc., 550 U.S. 398 (2007) ............................................47
`Merrill v. Yeomans, 94 U.S. 568 (1876)..................................................................28
`Statutes
`
`35 U.S.C. § 102............................................................................................. 2, 13, 40
`
`35 U.S.C. § 103....................................................................................................2, 10
`
`35 U.S.C. § 315(b) .....................................................................................................1
`
`Rules
`
`37 C.F.R. § 42.8 (b)(2)...............................................................................................1
`
`37 C.F.R. § 42.8 (b)(3)...............................................................................................1
`
`37 C.F.R. § 42.8 (b)(4)...............................................................................................2
`
`37 CFR § 42.100(b) .................................................................................................12
`
`Attachment A: Proof of Service of the Petition
`
`Attachment B: List of Evidence and Exhibits Relied Upon in Petition
`
`iii
`
`
`
`Petition for Inter Partes Review of U.S. Patent No. 6,237,127
`
`I.
`
`COMPLIANCE WITH PETITION REQUIREMENTS
`A.
`Certification the `127 Patent May Be Contested By Petitioner
`Petitioner certifies pursuant to 37 C.F.R. § 42.104(a) that Patent No.
`
`6,237,127 (“the `127 patent”) Ex. 1001 is available for inter partes review and that
`Petitioner is not barred or estopped from requesting inter partes review of the
`
`claims of the `127 patent on the grounds identified herein. This petition is
`
`accompanied by a motion for joinder with Case No. IPR2014-001145 hereinafter
`
`(the “Prior `127 Petition”), and, as such, the time period set forth in 37 C.F.R. §
`
`42.101(b) does not apply to this petition.
`
`Fee For Inter Partes Review (37 C.F.R. § 42.15(a) and § 42.103)
`B.
`Petitioner paid the required fees upon filing. Should any further fees be
`
`required, the PTAB is hereby authorized to charge Deposit Account No. 04-1073.
`
`C. Mandatory Notices (37 C.F.R. § 42.8)
`1. Real Party-In-Interest (§ 42.8(b)(1))
`The real party-in-interest is ATopTech, Inc. (“Petitioner”).
`
`2. Related Matters and Joinder Motion (§ 42.8 (b)(2))
`U.S. Patent No. 6,237,127 (“the `127 patent”) (Ex. 1001) is allegedly owned
`
`by Synopsys, Inc. (“Patent Owner”), and is currently being asserted by Patent
`Owner in Synopsys, Inc. v. ATopTech, Inc., No. 3:13-cv-02965-MMC (N.D. Cal.
`
`2013) hereinafter (the “Pending Litigation). Ex. 1003. The complaint was filed
`
`against petitioners on June 26, 2013 (Ex. 1003), and subsequently served on July
`
`12, 2013 (Ex. 1004). Petitioner timely filed a petition challenging all the claims of
`the `127 patent. On January 21, 2015, a decision instituting inter partes review of
`
`1
`
`
`
`Petition for Inter Partes Review of U.S. Patent No. 6,237,127
`
`claims 1-4 and 7-11 was entered in Case. No. IPR2014-01145 (the “`127 Inst.
`
`Dec.”). Trial was not instituted on claims 5 and 6 in the `127 Inst. Dec. because
`
`the Board adopted a claim construction that differed from Petitioner’s proposed
`
`construction. `127 Inst. Dec., p. 17. Petitioner submits the present petition to
`
`demonstrate the invalidity of claims 5 and 6 under the Board’s proposed claim
`
`construction in the `127 Inst. Dec. Allowing this petition to be joined will provide
`
`significant judicial economies at least because it will join all the claims of the `127
`
`patent asserted against Petitioner in the Pending Litigation into a single IPR. By
`
`separate motion filed herewith, Petitioner requests that this proceeding be joined
`
`with Case No. IPR2014-001145.
`
`3. Lead And Backup Counsel (§ 42.8 (b)(3))
`
`Lead Counsel
`Jeffrey A. Miller, Reg. No. 35, 287
`jeffrey.miller@kayescholer.com
`Tel 650.319.4500; Fax 650.319.4900
`
`Backup Counsel
`Nisha Agarwal, Reg. No. 67, 039
`nisha.agarwal@kayescholer.com
`Tel 650.319.4500; Fax 650.319.4900
`
`4. Service Information (§ 42.8 (b)(4))
`Service may be made to Jeffrey Miller, Kaye Scholer LLP, Two Palo Alto
`
`Square, Suite 400, 3000 El Camino Real, Palo Alto, CA 94306. Please also email
`
`correspondence to jeffrey.miller@kayescholer.com and
`
`nisha.agarwal@kayescholer.com.
`
`Proof Of Service (§ 42.6(e) and § 42.105(a))
`D.
`Proof of service of this petition is provided in Attachment A.
`
`2
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`
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`Petition for Inter Partes Review of U.S. Patent No. 6,237,127
`
`II.
`
`IDENTIFICATION OF CLAIMS BEING CHALLENGED (§
`42.104(B))
`Petitioner requests inter partes review of claims 5 and 6 because: (1) claims
`
`5 and 6 are rendered obvious under 35 U.S.C. § 103 by “Timing Analysis with
`
`known False Sub Graphs” by Belkhale et al. (“Belkhale”), Ex. 1005; and (2)
`
`claims 5 and 6 are rendered obvious under 35 U.S.C. § 103 by Belkhale in view of
`
`US Patent 5,210,700 (“Tom”) Ex. 1006. These claims were previously challenged
`
`in the Prior `127 Petition, but the Board chose not to institute trial on them because
`
`the Board adopted a different claim construction than Petitioner. `127 Inst. Dec. p.
`
`8, 17. The invalidity of the claims under the Board’s claim construction is
`
`addressed in this Petition.
`
`III. RELEVANT INFORMATION CONCERNING THE `127 PATENT
`A.
`Subject Matter of the `127 Patent
`The `127 Patent teaches methods for performing a static timing analysis on a
`
`circuit design. Ex. 1001, Title. When an electronic circuit is designed, it often
`
`begins with a designer expressing the design of the circuit in a high-level hardware
`description language (HDL)1. Ex. 1001, 1:17-20. Once the circuit description is
`expressed or coded by the designer using a HDL, the description for the circuit is
`
`converted/compiled into a circuit that is expressed as a netlist description of gates
`
`and transistors. Ex. 1001, 1:23-27. The process of converting/compiling the HDL
`
`1 The two most widely used HDL’s are Verilog, introduced by Gateway Design
`Automation in 1985, and VHDL, which resulted from a request from the
`
`Department of Defense in 1987. Ghiasi Declaration (Ex. 1007), ¶32.
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`Petition for Inter Partes Review of U.S. Patent No. 6,237,127
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`description of a circuit into a netlist description is well known to those of ordinary
`skill in the art as “synthesis.” Id. Synthesizing the HDL description of the circuit is
`
`more productive compared to a traditional schematic layout because the
`
`functionality of the circuit is abstracted. Ex. 1001, 1:21-23.
`
`The process of synthesizing a circuit design may be analogized to writing
`
`software in C or some other programming language, and compiling the source code
`
`into an executable. However, unlike compiling software, a circuit design that is
`
`output from the “synthesis” process must be compatible with hardware clocks and
`
`the delays associated with signal propagation. Thus, a timing analysis should be
`
`done to verify that the actual circuit design produced will perform correctly at the
`target clock speeds. Ex. 1001, 1:36-40; See also Ex. 1007, ¶34. This timing
`
`analysis of the circuit design is the subject of the `127 Patent. Ex. 1001, Title.
`
`In particular, the `127 Patent deals with the use of non-default timing
`constraints, which the `127 Patent calls “exceptions.” Id; Ex. 1007, ¶37. An
`
`exception, which may be identified by a user, instructs the timing analyzer that
`
`specific paths through the circuit design are not subject to the default timing
`
`constraints that the rest of the circuit must adhere to. Ex. 1001, 1:61-64. In the
`
`context of the `127 Patent, the timing analysis is performed within the “Design
`
`Compiler” shown as block 103 in Fig. 1. Ex. 1001, Fig. 1. As can be seen in Fig. 1,
`the “exceptions” 108 are input into the “Design Compiler.” Id; Ex. 1007, ¶39.
`
`1. Calculating Delay Values with Timing Table Propagation
`The timing analysis of the `127 Patent is performed in two steps: (1)
`
`calculating the delays through the circuit by propagating timing tables; and (2)
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`Petition for Inter Partes Review of U.S. Patent No. 6,237,127
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`comparing the calculated delays to the required timing constraints of the circuit. Ex.
`
`1001, 8:37-41. The first step of the timing analysis in the `127 Patent involves
`
`propagating the signal availability times through the various paths of the circuit
`
`and summing the delays along the way to calculate the minimum and maximum
`
`signal availability times at each point in the circuit. Ex. 1001, 8:41-13:2. These
`
`minimum and maximum delays are stored in “timing tables.” Ex. 1001, 9:53-58.
`
`As the timing tables are propagated through the circuit, the delays at each node are
`
`added to the minimum and maximum values of the timing table from the previous
`
`node. Ex. 1001, 10:61-11:15, Fig. 5. Delays associated with wire objects between
`
`nodes are taken into account by adding a fixed delay to each of the delay values of
`
`the timing tables propagated across the wire. Ex. 1001, 12:50-55. To this end, the
`
`worst case delays at each point within the circuit are calculated. Ex. 1007, ¶¶40-41.
`
`The `127 Patent teaches the use of a particular kind of “timing table,”
`
`referred to as an “RF timing table.” Ex. 1001, 3:7-11. The “RF timing table”
`
`includes the minimum and maximum delays associated with the rise and fall (RF)
`times of the signal. Id. Accordingly, the `127 Patent discloses that an “RF timing
`
`table” includes values for the minimum rise time (minRT), maximum rise time
`
`(maxRT), maximum fall time (maxFT), and minimum fall time (minFT). Id.
`
`2. Tracking “Exceptions” with Timing Table Propagation
`In addition to the delay values stored in each timing table, the `127 Patent
`
`teaches that the timing table includes a “tag.” Ex. 1001, 3:11-14. The specification
`
`of the `127 Patent teaches that a “tag” is a data structure that comprises “labels.”
`
`Ex. 1001, 10:21-25, See also 3:11-15. The `127 Patent teaches that the “labels”
`
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`Petition for Inter Partes Review of U.S. Patent No. 6,237,127
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`within a “tag” may identify a clock. Ex. 1001, 10:21-25. (“In general, a ‘tag’ is a
`
`data structure, pointed to by an RF timing table, which contains an identifier
`(which we shall refer to as a ‘label’)2 that uniquely determines the clock…”). The
``127 Patent also teaches that the labels of a “tag” may identify points in the circuit
`
`referenced by an exception. Ex. 1001, 3:29-32. (“For each output pin with an
`
`exception flag, a label, representing that pin…is added to the second part of the
`tag….”) See also 3:11-16, 3:35-39. Thus, the specification of the `127 Patent
`
`teaches that tags may comprise any number of labels and labels may identify
`
`clocks or points in the circuit referenced by an exception. Ex. 1007, ¶¶43-45.
`
`A “tag” is described by the `127 Patent as being comprised of different types
`
`of labels in different locations within the `127 Patent:
`
`RF timing tables each have their own “tag” which, in accordance with
`the present invention, has two parts: i) a first part which is loaded
`with a unique identifier for the clock of a launch flip flop; and ii) a
`second part which can contain a variety of “labels.”
`Ex. 1001, 3:11-16. In yet another portion of the `127 Patent, a “tag” is described
`
`as:
`
`In general, a “tag” is a data structure, pointed to by an RF timing table,
`which contains an identifier (which we shall also refer to as a “label”)
`that uniquely determines the clock driving the flip flop for which the
`RF timing table was created.
`Ex. 1001, 10:21-25.
`
`2 Unless indicated, any bolding, underlining, etc. of text is added by Petitioner.
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`Petition for Inter Partes Review of U.S. Patent No. 6,237,127
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`Fig. 12, shown to the left,
`
`illustrates one example of a circuit
`
`which has been processed using
`
`timing tables and tags. As seen in
`
`Fig. 12, at each point along the
`
`circuit, a timing table is produced –
`
`for example timing tables 1203,
`
`1207, 1211, 1217, 1218, etc. Each timing table points to a tag – 1204, 1208, 1212,
`
`1219 and 1220, respectively. Those tags include labels to either identify a clock or
`
`to identify points within the circuit. Ex. 1007, ¶¶48-49.
`
`To incorporate the use of exceptions within the timing table propagation,
`
`each time a timing table is created at a new location in the circuit, a check is made
`
`to determine whether the pin at that location is associated with an exception. Ex.
`
`1001, 18:31-35. If the pin is part of an exception statement, a label, which
`
`represents how the pin is referred to by the exception statement, may be added to
`the tag. Ex. 1001, 18:42-50. See also Ex. 1007, ¶50.
`
`“Exceptions” – Non-Default Timing Constraints
`3.
`The `127 Patent teaches that exceptions are specified by the circuit designer
`
`as individual syntactic units called “exceptions statements.” Ex. 1001, 1:57-61. An
`
`“exception statement” is a user-specified command, which for a particular path or
`
`set of paths through a circuit section, alters the default timing constraints. Ex. 1001,
`
`14:30-54. An exception statement comprises two main components: (i) a “path
`
`specification” which specifies the path or paths for which the exception statement
`
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`Petition for Inter Partes Review of U.S. Patent No. 6,237,127
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`applies; and (ii) a “timing alteration” which alters the default timing constraints of
`the specified paths. Id. The `127 Patent, at Ex. 1001, 14:43-46, gives an example
`
`of the syntax for an exception statement:
`
`<timing alteration>[value]<path_specification><delimiter>
`The `127 Patent explicitly states that what it calls a “false path” is an
`
`example of an exception statement. Ex. 1001, 14:44-54. When using the
`
`“set_false_path” exception statement, no additional timing information is needed
`
`because a false path always sets the Maximum Allowable Path Delay MAPD to
`
`infinity and sets the Shortest Allowable Path Delay SAPD to zero. Id.
`
`Accordingly, only a <path_specification> is required when defining a false path
`
`exception. Ex. 1001, 16:37-42. The `127 Patent provides the following
`
`“exemplary exception” statement: set_false_path –from input1 –to output1;
`
`explaining, “[t]his exception alters the default timing constraints, according to the
`
`“set_false_path” timing alteration discussed above, for the path beginning at a pin
`
`“input1” and ending at a pin “output1.” Id. See also Ex. 1007, ¶¶51-53.
`
`In the numerous examples throughout the `127 Patent, the “set_false_path”
`command is used as the example illustrating an exception statement. See e.g. Ex.
`
`1001, 16:33-17:39, 22:40-24:28, 24:29-25:61. One example is in Fig. 12,
`
`illustrated above, where the circuit is subject to the command: set_false_path –
`through {X1 X2}. See Ex. 1001, 24:47-54. This exception statement indicates that
`
`all paths through pin X1 or pin X2 should be subject to the “set_false_path” timing
`
`constraint. Ex. 1001, 22:49-55. Accordingly, pins X1 and X2 show up as
`
`arguments in the labels within the tags of the timing tables that have passed
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`Petition for Inter Partes Review of U.S. Patent No. 6,237,127
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`through pin X1 or pin X2. Ex. 1007, ¶54.
`
`“Pin-Labelling” – Associating the “Exceptions” with the Circuit
`4.
`Referred to as “pin-labelling” in the `127 Patent, the path specified by the
`
`exception statements are referenced to the circuit description in two different ways.
`
`Ex. 1001, 2:44-46; See also 18:10-22; 21:3-35. The `127 Patent teaches a first way
`
`of “pin labelling” where pins in the circuit design that are part of any exception are
`associated with an “exception flag.” Ex. 1001, 18:10-22; See also 2:44-46. This is
`
`illustrated as the “E.F.” (exception flag) elements 1110 and 1111 in Fig. 11. Ex.
`
`1007, ¶56.
`
`The second way the `127 patent teaches for “pin-labelling” is that an
`
`“argument container” is associated with the pin and the argument container may
`
`contain a collection of “labels” which may be matched to one or more exception
`
`statements. Ex. 1001, 2:48-63; 21:3-35. The `127 Patent explains: “Any form of
`
`label, which allows this matching to be accomplished, is suitable.” Ex. 1001, 2:56-
`
`57. If the exception deals with a single pin, the label may refer to a single pin. Ex.
`
`1001, 2:57-60. If the exception refers to several pins, a label which can represent
`
`the entire expression may be used. Ex. 1001, 2:60-62. Figure 12 illustrates the
`
`second-way of “pin-labelling” showing the two argument containers 1200 and
`
`1201 associated with pins x1 and x2 respectively both containing the label {x1 x2}.
`
`The label {x1 x2} is a single label establishing that the exception statement applies
`
`to pin x1 OR x2. Ex. 1001, 24:67-25:3. Ex. 1007, ¶57.
`
`As the timing tables propagate through the circuit description and pass
`
`through points that have been identified during pin labeling, the timing tables may
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`Petition for Inter Partes Review of U.S. Patent No. 6,237,127
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`be amended with a label representing the circuit point. Id. The second way of pin
`
`labeling may reduce the number of timing tables that need to be propagated. Ex.
`
`1001, 25:37-40. A good way to understand the different effects of the two
`
`methods of pin labeling is by comparing the difference between Figs. 11 and 12.
`
`In Fig. 11, at point X3 and X6, the first-way process results in four separate timing
`
`tables each with a different tag. In contrast, in Fig. 12, the second-way process
`
`results in only two separate timing tables at points X3 and X6. Ex. 1007, ¶¶58-59.
`
`5. Comparing the Delay Values in the Timing Tables to the Circuit
`Constraints and Applying the Relevant Exceptions.
`Once all the timing tables have been propagated through the circuit
`
`description and tagged with the relevant information, the delay values contained in
`
`the timing tables are compared to the relevant constraint values. Ex. 1001, 13:66-
`
`14:27. In the context of the `127 Patent, the constraint value is the required arrival
`
`time at the circuit point. The `127 Patent discloses: “[the] [Maximum Allowable
`Path Delay] MAPDxy and [Shortest Allowable Path Delay] SAPDxy are the default
`timing constraints…alterable by exceptions.” Ex. 1001, 13:60-63. Thus, the `127
`
`Patent applies any exceptions identified as being relevant by the tag in the timing
`
`table to the MAPD and/or SAPD, and then compares the MAPD and SAPD against
`
`the delay values stored in the timing table. Ex. 1001, 13:56-14:26. As already
`
`explained above in the section on exceptions, for set_false_path exceptions, the
`
`relevant MAPD’s are set to infinity and the relevant SAPD’s are set to zero. Ex.
`
`1001, 14:51-53. If the MAPD and SAPD timing constrains are satisfied, the circuit
`section has successfully passed the static timing analysis. Id. If they are not, some
`
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`Petition for Inter Partes Review of U.S. Patent No. 6,237,127
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`modification may be required. Ex. 1007, ¶¶60-62.
`
`Effective Filing Date and Prosecution History of The `127 Patent
`B.
`The `127 patent issued from Appl. 09/093,817 filed 6/8/1998. No priority or
`
`benefit claims were made, making the effective filing date 6/8/1998.
`
`The `127 Patent was filed with 13 original claims. Claim 1 was the only
`
`independent claim and claims 2-13 depended directly or indirectly from claim 1.
`
`On 4/12/2000, an Office Action was mailed in which claims 1-11 were rejected
`
`under 35 U.S.C. § 103(a) as being unpatentable over Osler and Tom (Ex. 1006).
`
`Ex. 1002, pgs. 131-136. The Examiner stated that Tom taught all the limitations of
`claim 1 but “exceptions.” Id. Specifically, the Examiner stated that the Tom
`
`taught: 1) “marking certain points (clock tags) in a circuit description”; 2)
`
`“propagating a plurality of timing tables (clock description & path delay tables…)
`through the circuit”; and 3) “a first timing table referring to a tag.” Id. The
`
`Examiner then stated that Osler taught (i) exceptions, and (ii) referencing
`
`exceptions to a circuit description, and thus finding that it would have been
`obvious for one skilled in the art to combine Tom and Osler. Id. Dependent claims
`
`2-11 were also rejected under the combination of Tom and Osler et al. Id.
`
`On 8/14/2000, Patent Owner submitted a response to the Office Action. Ex.
`
`1002, pgs. 143-147. Patent Owner did not amend the claims, arguing instead that
`
`they were patentable over the cited combination, specifically arguing that Osler did
`not teach the concept of exceptions. Id. Patent Owner argued that the “timing
`
`rules” of Osler were not the same as the “exceptions“ of the `127 Patent and
`
`therefore, claim 1 and all its dependent claims were patentable. Id. Importantly,
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`11
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`Petition for Inter Partes Review of U.S. Patent No. 6,237,127
`
`Patent Owner did not argue that any of the Examiner’s assertions relating to the
`
`teachings of Tom and its application to the claims were incorrect.
`
`On 11/20/2000, the Examiner mailed a notice of allowability, accepting the
`
`Patent Owner’s arguments that independent claim 1, and thus its dependent claims
`
`2-13, was patentable over Tom in view of Osler. Ex. 1002, pgs. 148-153.
`
`The Examiner’s stated reasons for allowability were as follows:
`
`From the prior arts of record, Tom does not teach the use of
`exceptions or some equivalent. Furthermore, Osler taught timing rules
`that are descriptions of circuit characteristics. These used timing rules
`are described as characterizing either a low level or a synthesized
`design by containing propagation paths and setup and hold tests.
`However, Osler failed to teach exceptions or some other equivalent.
`It is therefore clear that the Examiner allowed claims 1-13 of the `127 Patent
`
`because the Examiner thought the “exceptions” limitation was not in the prior art.
`
`1. Belkhale’s Significance was not Recognized During Prosecution
`The Examiner was mistaken that exceptions, i.e., non-default timing
`
`constraints, were not in the prior art. Belkhale, which was before the Examiner,
`
`although not relied on, demonstrates that use of exceptions was well known in the
`
`art. Patent Owner cited Belkhale in an information disclosure statement dated
`
`December 16, 1998, although no comments were made regarding Belkhale’s
`
`teachings. Ex. 1002, pgs. 119-121.
`
`Belkhale teaches use of the same “exception” the `127 patent uses as its
`
`exemplary exception throughout the patent, although it does not use the term
`
`“exception.” That is not surprising since the term “exception” was used mainly by
`
`12
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`Petition for Inter Partes Review of U.S. Patent No. 6,237,127
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`Synopsys (Ex. 1007, ¶38), whereas Belkhale’s work was performed at IBM. Ex.
`
`1005, p. 736, n.1. In particular, the `127 patent uses the “set_false_path” command
`
`as an exemplary exception. Yet, the set_false_path command was well known in
`
`the art, and Belkhale talks extensively about how to incorporate false paths in the
`
`context of a static timing analysis of a circuit design. To this end, the Examiner’s
`
`reasoning for allowance was clearly in error and the patentability of the claims of
`
`the `127 Patent must be reevaluated.
`
`How the Challenged Claims Are To Be Construed
`C.
`In this proceeding, claims must be given their broadest reasonable
`
`interpretation in light of the specification. 37 CFR § 42.100(b).
`
`In the Institution Decision of the Prior `127 Petition, the Board construed
`
`“exception” as “non-default timing constraints” and “timing table” as a “table
`
`having a timing value.” Both of these constructions agreed with Petition’s
`
`proposed constructions in the Prior `127 Petition and are adopted herein.
`
`In the Prior `127 Petition, Petitioner proposed construction for claim 5 was
`
`that it contained a typographical error and that the phrase “with the first label”
`
`should actually be “with the first constraint value.” The Board disagreed with the
`
`Petitioner explaining in the Institution Decision:
`
`We are not persuaded that claim 5 requires a timing value to be
`compared to a first label. As written, a comma separates the phrase
`“prior to comparing first timing value” from the phrase “with the first
`label.” Thus, rather than comparing the timing value with the first
`label, we read claim 5 to recite “satisfying an exception . . . with the
`first label.”
`
`13
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`
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`Petition for Inter Partes Review of U.S. Patent No. 6,237,127
`
`For the purposes of this Petition, the Board’s proposed claim construction
`
`for claim 5 has been adopted. Thus, in this Petition, all the Board’s claim
`
`constructions from the Institution Decision of the Prior `127 Petition have been
`
`adopted.
`
`Petitioner addresses the construction of claim terms while comparing the
`
`claims to the prior art. Petitioner addresses below the construction of “marking
`
`certain points in a circuit description according to their being referenced by at least
`
`a first exception” in Section IV.B.2.a. Petitioner address the construction of the
`
`claim term “timing tables” in Section IV.B.3.a. Petitioner addresses the
`
`construction of the claim term “tag” in Section IV.B.4.a. Petitioner respectfully
`
`submits that the discussion of the meaning of these claim terms is best understood
`
`when discussed in the context of the claims, which is found below.
`
`IV. PRECISE REASONS FOR RELIEF REQUESTED
`A.
`Belkhale Renders Claims 5 and 6 and Obvious
`1. Overview Of Belkhale
`Belkhale was published in a digest of technical papers from the 1995
`
`IEEE/ACM International Conference of Computer Aided Design held November
`
`5-9, 1995. The digest was available on the shelf of the Arizona State University
`
`library at least as early as February 19, 1996. Ex. 1005. Thus, the Belkhale
`
`reference is prior art under 35 U.S.C. § 102(b).
`
`Belkhale demonstrates that removing false paths, which are paths that are
`
`not logically realized by the circuit, prior to timing analysis, was well understood
`
`at the time of the `127 Patent. Belkhale states:
`
`14
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`Petition for Inter Partes Review of U.S. Patent No. 6,237,127
`
`Thus some of the paths that are considered by the algorithm may not
`be logically realizable. These paths are often referred to as false paths.
`Such paths must be detected and eliminated from consideration from
`the timing analysis. This problem has been studied extensively by
`many researchers, and various interesting algorithms for false path
`detection and elimination have been discovered [2,3,4,5,6,7].
`
`…In many cases, users do have an idea that certain paths reported by
`the timing system are really false. This formulation allows the user to
`convey this information to the timing system resulting in a more
`meaningful analysis. As will be shown in Section 2, the ability to
`remove entire sub graphs from consideration from timing is a
`powerful feature.
`Ex. 1005, p. 736. As is seen from this quote, Belkhale teaches Patent Owner’s
`
`“exceptions,” the very feature Patent Owner argued during prosecution
`
`distinguished its alleged invention from the prior art. Ex. 1007, ¶¶76-77.
`
`Belkhale discloses methods of removing “false sub graphs” from the timing
`
`analysis. Belkhale explains that that a “false sub graph” is a representation of one
`
`or more false paths. Ex. 1005, p. 736, (“The notion of false sub graphs is more
`
`general than the notion of false paths as we can simultaneously remove the
`
`consideration of multiple paths.”). Ex. 1007, ¶78.
`
`Throughout, Belkhale represents the timing model of the circuit as a graph G.
`
`Belkhale gives two example figures of false sub graphs, identified as F1 and F2,
`
`for the Timing graph G. Ex. 1005, Fig. 1, reprinted below. As seen in Fig. 1, false
`
`graph F1 represents all the paths from v1 to v7 and False graph F2 represents all
`
`the paths from v1 to v8 within the Timing graph G. Ex. 1007, ¶¶79-80.
`
`15
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`Petition for Inter Partes Review of U.S. Patent No. 6,237,127
`
`Belkhale explains how the false sub
`
`graphs may be specified by the user in the
`
`form of a set of ordered pair of vertices. Ex.
`
`1005, p. 737. For the false sub graph F1
`
`shown in Fig. 1, Belkhale states the false
`
`sub graph could be described by specifying
`
`the seven ordered pairs representing the
`
`seven non-diagonal false paths of the false
`
`sub graph. Id. This would be {(v1, v2), (v1,
`
`v3), (v2,v5), (v3, v5), (v2, v4), (v4, v7), (v5, v7)}. Ex. 1007, ¶81.
`
`Belkhale then provides a more specific example of a false path specified by
`
`the user. Referring to its Figure 2, reprinted here, Belkhale explains that if the
`
`control path delays are small, all paths leading from the
`I1 pin of the first multiplexer MUX1, to the I1 pin of the
`second multiplexer MUX2 are false. Id. Belkhale
`teaches that this false sub graph may be specified by the
`user by using the single ordered pair {(MUX1)/I1,
`MUX2/I1)}. Ex. 1005, p. 737. See also Ex. 1007, ¶¶82-
`83.
`
`The next section of Belkhale, Section 3 titled “Algorithm for the problem,”
`
`explai
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