IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
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`U.S. Patent No. 5,839,108
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`Trial Number: To Be Assigned
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`Panel: To Be Assigned
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`In the Inter Partes Review of:
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`Filed: June 30, 1997
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`Issued: November 17, 1998
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`Inventor(s): Norbert P. Daberko,
`Richard K. Davis
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`Assignee: e.Digital Corporation
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`Title: Flash Memory File System In a
`Handheld Record and Playback Device
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`Mail Stop Inter Partes Review
`Commissions for Patents
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`DECLARATION OF R. JACOB BAKER, PH.D.
`UNDER 37 C.F.R. § 1.68 IN SUPPORT OF PETITION
`FOR INTER PARTES REVIEW OF U.S. PATENT NO. 5,839,108
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`Table of Contents
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`
`I.
`INTRODUCTION ........................................................................................... 1
`BACKGROUND AND QUALIFICATIONS ................................................. 4
`II.
`III. UNDERSTANDING OF PATENT LAW ...................................................... 8
`IV. BACKGROUND ...........................................................................................10
`A.
`Background of the Field Relevant to the ’108 Patent .........................10
`1.
`Overview of Computer Memory and Storage Media ...............10
`2.
`File Management Systems ........................................................21
`Summary of Claim 1 of the ’108 Patent ..............................................27
`B.
`Summary of the Prosecution History ..................................................32
`C.
`LEVEL OF ORDINARY SKILL IN THE PERTINENT ART ....................34
`V.
`VI. BROADEST REASONABLE INTERPRETATION ...................................34
`VII. DETAILED INVALIDITY ANALYSIS ......................................................36
`A.
`Summary of Opinions .........................................................................37
`B.
`Claim 1 is Obvious Over Katayama In View of Mills ........................38
`1.
`Background on Katayama .........................................................38
`2.
`Background of Mills .................................................................45
`3.
`It Would Have Been Obvious to One of Ordinary Skill to
`Combine the Teachings of Mills with the Teachings of
`Katayama ..................................................................................48
`Detailed Analysis ......................................................................54
`4.
`Claim 1 is Obvious Over Krueger .......................................................74
`1.
`Background of Krueger .............................................................74
`2.
`Detailed Analysis ......................................................................84
`VIII. SECONDARY CONSIDERATIONS OF NON-OBVIOUSNESS ............104
`IX. CONCLUSION ............................................................................................104
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`C.
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`I, R. Jacob Baker, Ph.D. hereby declare as follows:
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`I.
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`INTRODUCTION
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`1.
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`I have been retained as an expert witness on behalf of Micron Technology,
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`Inc. (“Micron”) for the above-captioned Petition for Inter Partes Review
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`(“IPR”) of U.S. Patent No. 5,839,108 (“the ’108 patent”). I am being
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`compensated for my time in connection with this IPR at my standard
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`consulting rate of $450 per hour. My compensation is in no way dependent
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`on the outcome of this matter.
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`2.
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`I have been asked to provide my opinions regarding whether claim 1 of U.S.
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`Patent No. 5,839,108 (“Claim 1”) is invalid, as anticipated by the prior art,
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`or would have been obvious to a person having ordinary skill in the art at the
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`time of the alleged invention.
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`3.
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`The ’108 patent issued on November 17, 1998, from U.S. Patent Application
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`No. 08/884,245 (“the ’108 Application”), filed on June 30, 1997. (Ex. 1004,
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`the ’108 patent.) The ’108 patent is a continuation-in-part of U.S. Patent
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`Application No. 08/612,772, filed March 7, 1996, which issued as U.S.
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`Patent No. 5,787,445 (“the ’445 patent”) (Ex. 1008). I have been asked to
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`assume that the priority date of the alleged invention recited in the ’108
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`patent is March 7, 1996.1
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`4.
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`The face of the ’108 patent names Norbert P. Daberko and Richard K. Davis
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`as the purported inventors and identifies Norris Communications, Inc. as the
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`purported assignee of the ’108 patent. (Ex. 1004 at Cover.) I have reviewed
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`documentation from the Patent Office regarding the assignment of the ’108
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`patent. These records indicate that Norbert Daberko assigned his interest in
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`the ’108 patent to Norris Communications, Inc. on February 4, 1998.
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`(Ex. 1015.) In 2008, both named inventors assigned their rights in the ’108
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`patent to e.Digital Corporation (“e.Digital”). (Id.)
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`1 Claim 1 of the ’108 patent mirrors the language of claim 1 of the ’445 patent,
`with the exception of the final claim limitation, which further requires “storing the
`data segments to primary memory in a manner consistent with an industry standard
`data storage format while retaining linking between data segments created in
`previous steps.” The written description found in the specification of the ’108
`patent adds disclosure of this step at, e.g., col. 10:55-56, where it states that
`“industry standards such as MPEG-2 can presently be utilized” in conjunction with
`storage of files by the claimed file system. Thus, the priority date for Claim 1 of
`the ’108 CIP patent is, in my opinion, the filing date shown on its cover page, i.e.,
`June 30, 1997, rather than the filing date of the parent ’445 patent. Nevertheless,
`for the purposes of this declaration, all references which I discuss qualify as prior
`art even if the ’108 patent can claim a March 7, 1996 priority date.
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`5.
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`In preparing this Declaration, I have reviewed the ’108 patent, the file
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`history of the ’108 patent, and numerous prior art references and technical
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`references from the time of the alleged invention. I also reviewed the two
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`petitions for inter partes review from Intel Corporation, IPR2014-01429 and
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`IPR2014-01430, including the material contained therein. I reviewed the
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`declaration of Dr. Richard Mihran, and I largely agree with his opinions and
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`reasoning. I set forth much of his material in this declaration.
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`6.
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`I have been advised and it is my understanding that patent claims in an IPR
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`are given their broadest reasonable interpretation in view of the patent
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`specification, file history, and the understanding of one having ordinary skill
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`in the relevant art at the time of the purported invention.
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`7.
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`In forming the opinions expressed in this Declaration, I relied upon my
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`education and experience in the relevant field of the art, and have considered
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`the viewpoint of a person having ordinary skill in the relevant art, as of 1996.
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`My opinions directed to the invalidity of Claim 1 of the ’108 patent are
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`based, at least in part, on the following prior art publications:
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`Reference
`U.S. Patent No. 6,272,610 to
`Katayama, et al. (“Katayama”)
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`U.S. Patent No. 5,696,917 to Mills, et
`al. (“Mills”)
`
`Date of Public Availability
`Katayama was filed on March 9, 1994 and
`issued on August 7, 2001, and is attached
`as Ex. 1005 to the IPR.
`Mills was filed on June 3, 1994 and issued
`on December 9, 1997, and is attached as
`Ex. 1006 to the IPR.
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`European Patent Application
`Publication No. 0 557 736 A2 to
`Krueger, et al. (“Krueger”)
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`Krueger was filed on January 29, 1993 and
`published on September 1, 1993, and is
`attached as Ex. 1007 to the IPR.
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`II. BACKGROUND AND QUALIFICATIONS
`As indicated in my curriculum vitae, I currently serve as a Professor of
`8.
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`Electrical and Computer Engineering at the University of Nevada, Las
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`Vegas (UNLV). I have been teaching electrical engineering at UNLV since
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`2012. Prior to this position, I was a Professor of Electrical and Computer
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`Engineering with Boise State University from 2000. Prior to my position at
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`Boise State University, I was an Associate Professor of Electrical
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`Engineering between 1998 and 2000 and Assistant Professor of Electrical
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`Engineering between 1993 and 1998, both at University of Idaho. I have
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`been teaching electrical engineering since 1991. I received my Ph.D. in
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`Electrical Engineering from the University of Nevada, Reno in 1993. I also
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`received a MS and BS in Electrical Engineering from UNLV in 1988 and
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`1986, respectively.
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`9.
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`As further described in my CV, I am a licensed Professional Engineer in the
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`State of Idaho and have more than 25 years of experience, including
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`extensive experience in circuit design and manufacture of Dynamic Random
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`Access Memory (DRAM) integrated circuit chips and CMOS Image Sensors
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`(CISs) at Micron in Boise, Idaho. I also spent considerable time working on
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`the development of Flash memory while at Micron. My efforts resulted in
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`more than a dozen Flash-memory related patents. Among many other
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`experiences, I led the development of the delay-locked loop (DLL) in the
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`late 90s so that Micron products could transition to the DDR memory
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`standard. I also provided technical assistance with Micron’s acquisition of
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`Photobit during 2001 and 2002. This assistance included help transitioning
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`the manufacture of CIS products into Micron’s DRAM process technology.
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`I have worked as a consultant at other companies designing memory chips,
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`including Sun, Oracle, and Contour Semiconductor. I have worked at other
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`companies designing CISs, including Aerius Photonics and Lockheed-
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`Martin. I am currently working on the design of CISs and memory as a
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`consultant for OmniVision.
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`10.
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`I am the author of several books covering the area of integrated circuit
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`design including: DRAM Circuit Design: Fundamental and High-Speed
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`Topics (two editions), CMOS Circuit Design, Layout, and Simulation (three
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`editions), and CMOS Mixed-Signal Circuit Design (two editions). I have
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`authored, and/or co-authored, more than 75 papers and presentations in the
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`areas of solid-state circuit design.
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`11. As a professor, I have been the main advisor to five Doctoral students and
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`over 50 Masters students.
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`12.
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`I am the named inventor on over 135 granted U.S. patents in integrated
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`circuit design including flash memory, DRAM, and CMOS image sensors.
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`13.
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`I have received numerous awards for my work, including the Frederick
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`Emmons Terman (the “Father of Silicon Valley”) Award. The Terman
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`Award is bestowed annually upon an outstanding young electrical/computer
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`engineering educator in recognition of the educator’s contributions to the
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`profession.
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`14.
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`I have also received the IEEE Circuits and Systems Education Award
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`(2011), the IEEE Power Electronics Best Paper Award (2000), and I am a
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`Fellow of the IEEE for contributions to memory circuit design.
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`15.
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`In addition, I have received the President’s Research and Scholarship Award
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`(2005), Honored Faculty Member
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`recognition
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`(2003), Outstanding
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`Department of Electrical Engineering Faculty recognition (2001), all from
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`Boise State University. I have also received the Tau Beta Pi Outstanding
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`Electrical and Computer Engineering Professor award the two years I have
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`been at UNLV.
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`16.
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`I have also given over 50 invited talks at conferences and Universities in the
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`areas of integrated circuit design including: AMD, Arizona State University,
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`Beijing Jiaotong University, Carleton University, Carnegie Mellon,
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`Columbia University, Dublin City University (Ireland), École Polytechnique
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`de Montréal, Georgia Tech, Hong Kong University of Science and
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`Technology, Indian Institute of Science (Bangalore, India), Instituto de
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`Informatica (Brazil), Instituto Tecnológico y de Estudios Superiores de
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`Monterrey, ITESM (Mexico), Iowa State University, Laval University,
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`Lehigh University, Princeton University, Temple University, University of
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`Alabama, University of Arkansas, University of Buenos Aires (Argentina),
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`University of Illinois, Urbana-Champaign, Utah State University, University
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`of Nevada, Las Vegas, University of Houston, University of Idaho,
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`University of Nevada, Reno, University of Macau, University of Toronto,
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`University of Utah, Yonsei University (Seoul, Korea), University of
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`Maryland, IEEE Electron Devices Conference (NVMTS), IEEE Workshop
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`on Microelectronics and Electron Devices (WMED), the Franklin Institute,
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`Georgia Tech, National Semiconductor, AMI semiconductor, Micron
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`Technology, Rendition, Saintgits College (Kerala, India), Southern
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`Methodist University, Sun Microsystems, Stanford University, ST
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`Microelectronics (Delhi, India), Tower (Israel), Foveon, ICySSS keynote,
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`and Xilinx.
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`17. My professional and educational background, as well as a listing of other
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`matters on which I have provided consulting and/or provided testimony as a
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`technical expert, are detailed in my Curriculum Vitae, attached to this
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`Declaration. (Ex. 1002.)
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`III. UNDERSTANDING OF PATENT LAW
`I understand that prior art to the ’108 patent includes patents and printed
`18.
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`publications in the relevant art that predate the March 7, 1996 priority date I
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`have been asked to assume for this patent for the purposes of this
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`Declaration.
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`19.
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`I understand that a claim is invalid if it is anticipated or obvious.
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`Anticipation of a claim requires that every element of a claim be disclosed
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`expressly or inherently in a single prior art reference, as claimed.
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`Obviousness of a claim requires that the claim be obvious from the
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`perspective of a person having ordinary skill in the relevant art at the time
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`the alleged invention was made. I understand that a claim may be obvious
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`from a combination of two or more prior art references.
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`20.
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`I understand that an obviousness analysis requires an understanding of the
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`scope and content of the prior art, any differences between the alleged
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`invention and the prior art, and the level of ordinary skill in evaluating the
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`pertinent art.
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`21.
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`I further understand that certain factors may support or rebut the obviousness
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`of a claim. I understand that such secondary considerations include, among
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`other things, commercial success of the patented invention, skepticism of
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`those having ordinary skill in the art at the time of invention, unexpected
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`results of the invention, any long-felt but unsolved need in the art that was
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`satisfied by the alleged invention, the failure of others to make the alleged
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`invention, praise of the alleged invention by those having ordinary skill in
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`the art, and copying of the alleged invention by others in the field. I
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`understand that there must be a nexus—a connection—between any such
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`secondary considerations and the alleged invention. I also understand that
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`contemporaneous and independent invention by others is a secondary
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`consideration tending to show obviousness.
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`22.
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`I further understand that a claim may be obvious if common sense directs
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`one to combine multiple prior art references or add missing features to
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`reproduce the alleged invention recited in the claims. If a person having
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`ordinary skill in the relevant art can implement a predictable variation,
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`obviousness likely bars its patentability. For the same reason, if a technique
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`has been used to improve one device and a person having ordinary skill in
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`the art would recognize that it would improve similar devices in the same
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`way, using the technique is obvious. I further understand that a claim can be
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`obvious if it unites old elements with no change to their respective functions,
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`or alters prior art by mere substitution of one element for another known in
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`the field and that combination yields predictable results. While it may be
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`helpful to identify a reason for this combination, common sense should
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`guide and no rigid requirement of finding a teaching, suggestion or
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`motivation to combine is required. When a product is available, design
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`incentives and other market forces can prompt variations of it, either in the
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`same field or a different one.
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`IV. BACKGROUND
`A. Background of the Field Relevant to the ’108 Patent
`23. The ’108 patent is directed generally to the field of digital audio recording
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`devices using non-volatile memory, such as flash memory. (Ex. 1004 at
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`Abstract.) While claims 2-6 are directed to structures of the recording
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`devices, Claim 1 is directed to a particular method of managing the storage
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`of data on non-volatile memory, which the specification asserts is
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`particularly appropriate for flash memory. The method of Claim 1 further
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`includes the use of a volatile cache memory to serve as temporary storage
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`for data to be written to the non-volatile memory. To provide context for the
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`discussion to follow, a brief overview of basic volatile and non-volatile
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`memory types, including flash memory, is presented below.
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`1. Overview of Computer Memory and Storage Media
`24. There were a wide variety of memory technologies and related devices that
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`were known and commonly used by those of skill in the art in the 1996 time
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`frame, both in general purpose computers (e.g., a “personal computer”), as
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`well as more specialized systems or devices utilizing microprocessor-based
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`designs. The digital recording device as disclosed in the ’108 and ’445
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`patents is an example of a microprocessor-based, specialized application
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`utilizing non-volatile storage media.
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`25. At the core of these devices is a microprocessor which, when coupled with
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`appropriate memory and other circuitry, provides a system that can be
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`programmed to execute a wide variety of functions and operations. The
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`audio recording device disclosed in the parent ’445 patent utilizes such a
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`microprocessor directly coupled to flash memory, shown as element 32 in
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`FIG. 3A, which is reproduced below:
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`(Ex. 1008 at FIG. 3A.)
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`26. The specification of the ’445 patent describes this figure as depicting the
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`“apparatus of the present invention:”
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`The present invention takes a very different approach to
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`memory management. This new approach, embodied in
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`a method and apparatus, overcomes the significant
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`drawbacks of Ban. This is accomplished by taking
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`advantage of the properties of flash memory, instead of
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`treating them as a liability.
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`To understand the new method, it is necessary to have an
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`understanding of the arrangement of the underlying
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`hardware. The apparatus of the present invention is
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`shown in block diagram form in FIG. 3A. As
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`illustrated, the components of a system utilizing the
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`memory management method of the present invention
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`include an I/O device 30, a processor 32, a small cache
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`memory 34 for temporary storage of data, and in a
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`preferred embodiment, a relatively larger flash memory
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`36 for nonvolatile, long-term storage of data. (Ex. 1008
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`at 7:62-8:9.)2
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`27. To provide additional context as to how one of ordinary skill in the art
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`would understand the meaning of the term “processor” or “microprocessor”
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`as used in the ’108 and ’445 patents, I have reproduced below the definition
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`of this term as found in the Microsoft Press Computer Dictionary, Second
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`Edition, 1994. 3 The Microsoft Press Computer Dictionary defines
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`“microprocessor” as follows. As noted in this definition, a microprocessor
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`requires “memory and power” to provide the basic “pieces” of a computer:
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`2 For all quotes herein, emphases are added unless otherwise noted.
`3 This dictionary has particular relevance in this matter, because it was one which
`the Examiner and Applicants referred to and relied upon extensively during the
`prosecution history of the related ’774 patent, which is incorporated by reference
`into the ’108 patent (Ex. 1004 at 1:23-30), and the parent ’445 patent. (Ex. 1008 at
`15:8-13.)
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`(Ex. 1010.)
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`
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`28. While there are a variety of ways in which digital memory devices for use in
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`microprocessor-based systems may be categorized, it is helpful as a starting
`
`point to distinguish between basic classes of memory devices based on the
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`underlying materials that are used to provide the data storage capability.
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`These might include memory devices based on magnetic materials, optical
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`materials, and so-called “solid state” or semiconductor materials.
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`29. Examples of magnetic storage devices are familiar to most operators of
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`personal computers, and include the ubiquitous hard disk drives and the now
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`less-common floppy disk drives. Disk drives of this type store digital
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`information based on the manner in which microscopic regions on the disk
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`surface are magnetized, and data can be both written to and read from these
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`devices.
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`30. Examples of optical storage devices are also quite familiar to operators of
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`personal computers, as well as users of digital music and video devices, and
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`include DVD and CD storage devices. These may be “read-only” (i.e., data
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`can be read from the disk, but not written to it), “write-once” (i.e., the disk
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`can be written to or “burned” once, but not rewritten), or “rewritable” (i.e.,
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`data may be written and overwritten later).
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`31. The storage media associated with magnetic and optical disk storage devices
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`is considered “non-volatile,” i.e., once that data is written in the device, it
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`will be retained even when the device is powered off. In addition, these
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`devices read and write data in relatively large “blocks,” i.e., data is not read
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`or written one byte at a time, but rather is assembled into groups consisting
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`of tens, hundreds, or thousands of bytes before being written to or read from
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`these disk-type memory devices.
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`32.
`
`In contrast, many types of so-called “solid state” or semiconductor memory
`
`devices provide “random access” to the individual bytes for reading and/or
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`writing of data, allowing a microprocessor or other device to specify and
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`directly access a specific memory “address”—i.e., a discrete location where
`
`a single byte or word of data can be stored or read from. The term “solid
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`state” refers to the semiconductor materials such as silicon on which
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`transistors and other elements may be fabricated at a microscopic scale to
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`produce what are commonly referred to as integrated circuits, or “chips.”
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`The origin of the term solid state is historical, as it distinguished the
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`transistor made from solid semiconductor material from the vacuum tubes
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`that conduct electricity with a gas which the transistor replaced.
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`33. Semiconductor memory devices may take many different forms which affect
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`their functionality and suitability for different applications. While I will not
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`survey the full spectrum of such devices, there are several types of solid
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`state memory that are of particular relevance to the disclosures of the ’108
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`and ’445 patents, and thus to provide context for my opinions to follow, I
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`will provide an overview of some of these types of memory devices.
`
`(a) Random Access Memory or RAM
`34. Although different types of memory may provide “random access” to stored
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`data, the term “RAM” is conventionally used by those of skill in the art
`
`(both now, and in the 1996 time frame) to refer to a type of semiconductor
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`memory that can be both read from and written to in any order, and is
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`volatile—i.e., it will lose the stored data if power is removed from the device.
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`This is confirmed, for example, by the definition for random access memory,
`
`or RAM, as found in the 1994 Microsoft Press Computer Dictionary:
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`
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`(Ex. 1010.)
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`35. RAM is the type of memory commonly used in computers and other
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`microprocessor-based systems for what is known to those of skill in the art
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`as “main memory,” “primary storage,” or “primary memory.” The
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`microprocessor has direct access to this memory, and it is used for general
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`purpose operations. I note in this context that the ’445 patent emphasizes
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`that the file system of the purported invention utilizing non-volatile flash
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`memory greatly reduces the size of RAM, or system memory, required:
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`The present invention also provides a file system which
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`appears to have significant RAM resources, when in fact
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`there is only a non-volatile long-term storage medium
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`and a small cache, typically comprised of RAM. (Ex.
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`1008 at 8:61-64.)
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`* * *
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`The obvious benefit of the file system, then, is avoiding
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`the use of a large RAM resource and yet accomplishing
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`typical file system functions as well as support features
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`like editing that are normally performed in RAM. (Ex.
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`1008 at 9:65-10:2.)
`
`* * *
`
`If flash memory is to serve as primary memory with a
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`relatively small RAM resource which cannot easily be
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`used for data manipulation, the file system must also
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`provide a method for easily accessing the data stored in
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`flash memory. (Ex. 1008 at 14:29-33.)
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`(b) Electrically Erasable Programmable Read Only
`Memory (EEPROM) and Flash Memory
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`36. Another class of semiconductor memory is that of electrically erasable
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`programmable read only memory, or EEPROM. Flash memory is a type of
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`EEPROM that may take various forms, discussed further below.
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`37. As the name suggests, EEPROM can be erased and programmed (and, of
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`course, read from) electrically, and provides random access capability like
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`RAM, but operates more slowly in terms of its memory operations. It has a
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`further disadvantage in that the number of times it can be reprogrammed
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`before damage to the device occurs is limited. Unlike RAM, it is nonvolatile,
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`and thus will retain stored data indefinitely even when power has been
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`removed. The entry from the 1994 Microsoft Press Computer Dictionary for
`
`EEPROM is provided below:
`
`
`
`
`
`(Ex. 1010.)
`
`38. Flash memory is a particular type of EEPROM that may take a number of
`
`different forms having different characteristics in terms of how data can be
`
`read or written. The Examiner and the Applicants in the related ’774 patent
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`prosecution history relied specifically on the definition of flash memory in
`
`the same 1994 Microsoft Press Computer Dictionary, which is provided
`
`below:
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`(Ex. 1010.)
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`
`
`39. As described in the specification of the parent ’445 patent, flash memory has
`
`certain advantages over other non-volatile storage media, such as traditional
`
`magnetic disks: it requires no moving parts, has lower power usage, and can
`
`achieve faster random reads and higher
`
`throughput. One of
`
`the
`
`disadvantages of flash memory described in the ’445 patent is that the bit
`
`cells in flash memory—each of which stores one bit of data—must be erased
`
`before new data can be written to it. More precisely, a memory cell in flash
`
`existing in a logic state of “1” can be changed to a logical “0” without
`
`erasure, but blocks having cells with logic 0 states must be erased before
`
`being written to or updated. Further, flash memory is erased in blocks,
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`rather than individual bits or bytes. (See, e.g., Ex. 1008 at 2:11-13.)
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`Furthermore, erasure cannot be done for individual flash memory cells or
`
`addresses. Rather, flash memory must be erased a “block” at a time. (See,
`
`e.g., Ex. 1008 at 9:14-15.)
`
`File Management Systems
`
`2.
`40. As I will discuss in greater detail below, claim 1 of the ’108 patent (and all
`
`claims of the parent ’445 patent) is a method claim directed to management
`
`of “data segments” in a non-volatile primary memory “stored therein by a
`
`file system.”
`
`41.
`
`In general terms, file systems are used by an operating system to manage
`
`how data representing files are written to and read from a storage medium.
`
`There were a variety of types of file systems known to those of ordinary skill
`
`in the art at the time of the purported invention.
`
`(a) File allocation table (FAT) file systems
`42. One very common type of file system was the widely-implemented family of
`
`File Allocation Table or FAT file systems used, e.g., in personal computers
`
`running the Microsoft DOS and Windows operating systems at the time of
`
`the purported invention.
`
`43. Although many variations of the FAT family of file systems were developed
`
`over a period of about two decades between its widespread use in hard disks
`
`beginning in the early 1980s through the late 1990s (i.e., through the
`
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`Windows 9.x period), these systems may be characterized in general as those
`
`relying upon an index map or table to manage files. The index table or FAT
`
`contains a series of entries corresponding to individual clusters or
`
`“allocation units” on (most commonly) a disk storage medium, although the
`
`principle may be applied to other forms of storage media as well.
`
`44. Each cluster or allocation unit is a contiguous area comprising one or more
`
`sectors, and represents the minimum unit that a file can utilize. As such,
`
`files are stored across integral numbers of clusters when the file size exceeds
`
`the size of a single cluster. Although a single cluster itself is contiguous in
`
`the storage medium, the data comprising a file commonly occupies multiple
`
`clusters, which themselves may be (and commonly are) non-contiguous. In
`
`such cases, the file is said to be “fragmented.”
`
`45. The File Allocation Table or FAT contains one entry that maps to each
`
`cluster, and describes how the cluster is allocated. For a given file spanning
`
`multiple clusters, e.g., each entry includes the address of the next cluster in
`
`the chain, until the last cluster, in which the entry indicates the last cluster in
`
`the chain. Entries in the FAT may also indicate a bad, unused, or reserved
`
`cluster.
`
`46. With the advent of flash memory as a non-volatile, long-term storage
`
`medium, file systems for flash memory were later developed to better
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`manage the limitations of flash memory as compared to write-in-place media,
`
`such as magnetic disks. One of the earliest of these systems was named
`
`TrueFFS and was developed by the Israeli company, M-Systems Flash Disk
`
`Pioneers, Ltd. M-Systems subsequently filed a patent application on their
`
`flash file system on March 8, 1993, which ultimately issued as U.S. Patent
`
`No. 5,404,485 to Ban (“Ban”).
`
`(b) The ’445 and ’108 patents’ file systems use linked lists
`instead of a FAT
`
`47. Both the ’108 patent and the parent ’445 patent extensively contrasted the
`
`patentee’s flash memory file management methods with those disclosed in
`
`this prior art Ban patent. The specification of the ’445 patent characterizes
`
`Ban as teaching the creation of a “virtual memory map” for “converting
`
`virtual addresses to physical addresses.” (Ex. 1008 at 2:52-61.) According
`
`to the ’108 and ’445 patents, the use of this method of “indirection” in flash
`
`memory causes “severe overhead burdens.” (Ex. 1004 at 2:1-13; Ex. 1008 at
`
`2:50-61.)
`
`48. To address this purported inefficiency, the ’445 patent teaches logically
`
`linking data segments “by creating headers which contain pointers to
`
`absolute physical locations within flash memory.” (Ex. 1008 at 6:16-17.)
`
`During a write operation, a header is placed at the beginning of each data
`
`segment being stored in flash memory. (Ex. 1008 at 4:27-28; FIG. 7A.)
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`49.
`
`In contrast to Ban, the alleged invention was characterized by the Applicants
`
`as eliminating the use of memory maps, and instead using logical links
`
`stored in the headers provide “a logical path to the data segments.” As I will
`
`discuss in further detail in subsequent sections of this Declaration, the effect
`
`of the headers appended to data segments, as disclosed in the parent ’445
`
`patent, is to create a linked-list of data segments that are chained together to
`
`comprise, for example, a file, rather than reliance on an index table or
`
`memory map.
`
`50. The applicants argued this distinction directly in the specification of the ’445
`
`patent, stating for example:
`
`Ban also disadvantageou