United States Patent [191
`Harari
`
`[54] HIGHLY COMPACT EPROM AND FLASH
`EEPROM DEVICES
`[76] Inventor: Eliyahou Harari, 2320 Friars La.,
`Los Altos, Calif. 94022
`[21] Appl.No.: 204,175
`[22] Filed:
`Jun. 8, 1988
`[51] Int. Cl.5 ................... .. H01L 29/78; H01L 27/01;
`HOlL 29/10; H01L 29/40
`[52] US. Cl. ................................ .. 357/235; 357/231;
`357/233; 357/41; 357/45; 357/53; 365/185
`[58] Field of Search ................
`357/235, 23.1, 23.3,
`357/234, 41, 53, 45
`References Cited
`U.S. PATENT DOCUMENTS
`
`[56]
`
`4,331,968 5/1982 Gosney, Jr. et a1. ............ .. 357/235
`4,361,847 11/1982 Harari ............. ..
`..
`4,377,818 3/1983 Kuo et a1.
`4,412,311 10/1983 Miccoli et a1.
`
`..
`
`.
`
`4,422,092 12/1983 Guterman . . . . .
`
`. . . . .. 357/235
`
`4,462,090 6/1984 Iizuka . . . . . . . .
`4,486,769 12/1984 Simko
`
`4,503,519 3/1985 Arakawa . . . . . .
`4,577,215 3/1986 Stewart et a1.
`
`. . . . .. 357/235
`.... .. 357/235
`
`. . . . .. 357/235
`.... .. 357/235
`
`4,665,417 5/1987 Lam . . . . . . . . . . . . . .
`
`. . . . .. 357/235
`
`.... .. 357/235
`4,717,943 1/1988 Wolf et a1.
`365/51
`4,763,299 8/1988 Hazani ......
`357/235
`4,794,565 12/1988 Wu et a1. ..
`357/235
`4,803,529 2/1989 Masuoka .... ..
`.. 357/235
`4,852,062 7/1989 Baker et al. ..
`4,935,378 6/1990 Mori .................................... .. 437/43
`
`FOREIGN PATENT DOCUMENTS
`
`0047153 3/1982 European Pat. Off. ......... .. 357/235
`0219241 4/1987 European Pat. Off. .
`.. 357/235
`58-054668 3/1983 Japan .................. ..
`357/235
`58-121678 7/1983 Japan
`357/235
`62-165370 7/1987 Japan
`357/235
`63-093158 4/1988 Japan ................................ .. 357/235
`
`OTHER PUBLICATIONS
`S. Tanaka et al., “A Programmable 256K CMOS
`EPROM with On-Chip Test Circuits”, 1984 ISSCC
`Digest of Technical Papers, pp. 148-149.
`H. A. R. Wegener, “Endurance Model for Tex
`tured-Poly Floating Gate Memories”, Technical Digest _
`
`llllllllllllllIlllllllIlllllllllllllllllllllllllllllIllllllllllllllllllllll '
`US005095344A
`[11] Patent Number:
`[45] Date of Patent:
`
`5,095,344
`Mar. 10, 1992
`
`of the IEEE International Electron Device Meeting, Dec.
`1984, pp. 480-483.
`Y. Mizutani and K. Makita, “A New EPROM Cell with
`a Side-Wall Floating Gate for High-Density and High
`-Performance Device”, 1985 IEDM Technical Digest,
`pp. 635-638.
`F. Masuoka et al., “A 256K Flash EEPROM Using
`Triple Polysilicon Technology”, Digest of Technical
`Papers, IEEE International Solid-State Circuits Confer
`ence, Feb. 1985, pp. 168-169, p. 335.
`A. T. Wu et al., “A Novel High-Speed, 5-Vo1t Pro
`gramming EPROM Structure with Source-Side Injec
`tion”, 1986 IEDM Technical Digest, pp. 584-587.
`G. Samachisa et al., “A 128K Flash EEPROM Using
`Double-Polysilicon Technology”, IEEE Journal of
`Solid State Circuits, Oct. 1987, vol. SC-22, No. 5, pp.
`676-683.
`
`(List continued on next page.)
`
`Primary Examiner-Andrew J. James
`Assistant Examiner-Daniel Kim
`Attorney, Agent, or Firm-Majestic, Parsons, Siebert &
`Hsue
`
`ABSTRACT
`[s1] -
`Structures, methods of manufacturing and methods of
`use of electrically programmable read only memories
`(EPROM) and ?ash electrically erasable and program
`mable read'only memories (EEPROM) include split
`channel and other cell con?gurations. An arrangement
`of elements and cooperative processes of manufacture
`provide self-alignment of the elements. An intelligent
`programming technique allows each memory cell to
`store more than the. usual one bit of information. An
`intelligent erase algorithm prolongs the useful life of the
`memory cells. Use of these various features provides a
`memory having a very high storage density and a long
`life, making it particularly useful as a solid state memory
`in place of magnetic disk storage devices in computer
`systems.
`
`15 Claims, 28 Drawing Sheets
`
`Page 1 of 49
`
`PETITIONER'S EXHIBIT 1014
`
`

`

`5,095,344
`Page 2
`
`OTHER PUBLICATIONS
`
`H. Kume et al., “A Flash-Erase EEPROM Cell with an
`Asymmetrical Source and Drain Structure”, Technical
`Digest of the IEEE International Electron Devices Meet
`ing, Dec. 1987, pp. 560-563. _
`V. N. Kynett et al., “An In-System Reprogrammable
`256K CMOS Flash Memory”, Digest of Technical Pa
`pers, IEEE International Solid-State Circuits Conference,
`Feb. 1988, pp. 132-133, 330.
`
`M. Horiguchi et al., “An Experimental Large-Capacity
`Semiconductor File Memory Using 16-Levels/ Cell
`Storage”, IEEE Journal of Solid-State Circuits, vol. 23,
`No. 1, Feb. 1988, pp. 27-33.
`T. Furuyama et al., “An Experimental 2—Bit/Cell Stor~
`age DRAM for Macro Cell or Memory-on-Logic Ap
`plication”, IEEE Custom Integrated Circuits Conference,
`May 1988, pp. 4.4.l-4.4.4.
`Muller et al., “Electrically Alterable 8192 Bit N-Chan
`nel MOS PROM”, 1977 IEEE International Solid-State
`Circuits Conference, Feb.. 18, 1977, pp. 188-189.
`
`Page 2 of 49
`
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`

`US. Patent
`
`Mar. 10, 1992
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`Sheet 1 of 28
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`Page 3 of 49
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`PETITIONER'S EXHIBIT 1014
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`US. Patent
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`Mar. 10, 1992
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`Page 4 of 49
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`PETITIONER'S EXHIBIT 1014
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`US. Patent
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`Mar. 10, 1992
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`PETITIONER'S EXHIBIT 1014
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`US. Patent
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`Mar. 10, 1992
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`PETITIONER'S EXHIBIT 1014
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`US. Patent
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`Mar. 10, 1992
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`Page 7 of 49
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`PETITIONER'S EXHIBIT 1014
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`US. Patent
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`Mar. 10, 1992
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`US. Patent
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`Mar. 10, 1992
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`PETITIONER'S EXHIBIT 1014
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`US. Patent
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`Mar. 10, 1992
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`PETITIONER'S EXHIBIT 1014
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`US. Patent
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`Mar. 10, 1992
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`PETITIONER'S EXHIBIT 1014
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`US. Patent
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`Mar. 10, 1992
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`Sheet 10 of 28
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`5,095,344
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`US. Patent
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`Mar. 10, 1992
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`Sheet 11 of 28
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`Page 13 of 49
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`PETITIONER'S EXHIBIT 1014
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`

`US. Patent
`US. Patent
`
`Mar. 10, 1992
`Mar. 10, 1992
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`Sheet 12 of 28
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`5,095,344
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`Page 14 0f 49
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`PETITIONER'S EXHIBIT 1014
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`US. Patent
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`Mar. 10, 1992
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`US. Patent
`
`Mar. 10, 1992
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`Page 16 of 49
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`US. Patent
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`Mar. 10, 1992
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`Sheet 15 of 28
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`>U.S. Patent
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`Mar. 10, 1992
`Mar. 10, 1992
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`Page 18 of 49
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`US. Patent
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`Mar. 10, 1992
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`Sheet 17 of 28
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`US. Patent
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`Mar. 10, 1992
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`Sheet 18 of 28
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`5,095,344
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`US. Patent
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`Mar. 10, 1992
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`PETITIONER'S EXHIBIT 1014
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`US. Patent
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`Mar. 10, 1992
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`Sheet 20 of 28
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`5,095,344
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`US. Patent
`
`Mar. 10, 1992
`
`Sheet 21 of 28
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`5,095,344
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`US. Patent
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`Mar. 10, 1992
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`Sheet 22 of 28
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`PETITIONER'S EXHIBIT 1014
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`US. Patent
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`Mar. 10, 1992
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`Sheet 23 of 28
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`US. Patent
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`Mar. 10, 1992
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`Sheet 24 of 28
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`5,095,344
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`VERASEJ
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`Page 26 of 49
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`PETITIONER'S EXHIBIT 1014
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`PETITIONER'S EXHIBIT 1014
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`US. Patent
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`Mar. 10, 1992
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`Sheet 25 of 28
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`5,095,344
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`Page 27 of 49
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`PETITIONER'S EXHIBIT 1014
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`PETITIONER'S EXHIBIT 1014
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`US. Patent
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`Mar. 10, 1992
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`Sheet 26 of 28
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`2 5,095,344
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`ERASE GATE
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`Page 28 of 49
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`PETITIONER'S EXHIBIT 1014
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`Page 28 of 49
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`PETITIONER'S EXHIBIT 1014
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`US. Patent
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`Mar. 10, 1992
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`Sheet 27 of 28
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`5,095,344
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`Page 29 of 49
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`PETITIONER'S EXHIBIT 1014
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`PETITIONER'S EXHIBIT 1014
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`US. Patent
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`Mar. 10, 1992
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`Sheet 28 of 28
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`5,095,344
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`Page 30 of 49
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`PETITIONER'S EXHIBIT 1014
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`PETITIONER'S EXHIBIT 1014
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`I
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`5,095,344
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`2
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`HIGHLY COMPACT EPROM AND FLASH
`EEPROM DEVICES
`
`BACKGROUND OF THE INVENTION
`
`This invention relates generally to semiconductor
`electrically programmable read only memories (Eprom)
`and electrically erasable programmable read only mem-
`ories (EEprom), and specifically to semiconductor
`structures of such memories, processes of making them,
`and techniques for using them.
`An electrically programmable read only memory
`(Eprom) utilizes a floating (unconnected) conductive
`gate,
`in a field effect transistor structure, positioned
`over but insulated from a channel region in a semicon-
`ductor substrate, between source and drain regions. A
`control gate is then provided over the floating gate, but
`also insulated therefrom. The threshold voltage charac-
`teristic of the transistor is controlled by the amount of
`charge that is retained on the floating gate. That is, the
`minimum amount of voltage (threshold) that must be
`applied to the control gate before the transistor is
`turned ”on” to permit conduction between its source
`and drain regions is controlled by the level of charge 011
`the floating gate. A transistor is programmed to one of
`two states by accelerating electrons from the substrate
`channel region, through a thin gate dielectric and onto
`the floating gate.
`The memory cell transistor’s state is read by placing
`an operating voltage across its source and drain and on
`its control gate, and then detecting the level of current
`flowing between the source and drain as to whether the
`device is programmed to be “on” or “off" at the control
`gate voltage selected. A specific, single cell in a two-di-
`mensional array of Eprom cells is addressed for reading
`by application of a source-drain voltage to source and
`drain lines in a column containing the cell being ad-
`dressed, and application of a control gate voltage to the
`control gates in a row containing the cell being ad-
`dressed.
`This type of Eprom transistor is usually implemented
`in one of two basic configurations. One is where the
`floating gate extends substantially entirely over the
`transistor’s channel region between its source and drain.
`Another type, preferred in many applications, is where
`the floating gate extends from the drain region only part
`of the way across the channel. The control gate then
`extends completely across the channel, over the floating
`gate and then across the remaining portion of the chan-
`nel not occupied by the floating gate. The control gate
`is separated from that remaining channel portion by a
`thin gate oxide. This second type is termed a “split-
`channel" Eprom transistor. This results in a transistor
`structure that operates as two transistors in series, one
`having a varying threshold in response to the charge-
`level on the floating gate, and another that is unaffected
`by the floating gate charge but rather which operates in
`response to the voltage on the control gate as in any
`normal field effect transistor.
`Early Eprom devices were erasable by exposure to
`ultraviolet light. More recently, the transistor cells have
`been made to be electrically erasable, and thus termed
`electrically erasable and programmable read only mem-
`ory (EEprom). One way in which the cell is erased
`electrically is by transfer of charge from the floating
`gate to the transistor drain through a very thin tunnel
`dielectric. This is accomplished by application of appro-
`priate voltages to the transistor’s source, drain and con-
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`trol gate. Other EEprom memory cells are provided
`with a separate, third gate for accomplishing the eras-
`ing. An erase gate passes through each memory cell
`transistor closely adjacent to a surface of the floating
`gate but insulated therefrom by a thin tunnel dielectric.
`Charge is then removed from the floating gate of a cell
`to the erase gate, when appropriate voltages are applied
`to all the transistor elements. An array of EEprom cells
`are generally referred to as a Flash EEprom array be-
`cause an entire array of cells, or significant group of
`cells, is erased simultaneously (i.e., in a flash).
`EEprom’s have been found to have a limited effective
`life. The number of cycles of programming and erasing
`that such a device can endure before becoming de-
`graded is finite. After a number of such cycles in excess
`of 10,000, depending upon its specific structure, its pro-
`grammability can be reduced. Often, by the time the '
`device has been put through such a cycle for over
`100,000 times,
`it can no longer be programmed or
`erased properly. This is believed to be the result of ‘
`electrons being trapped in the dielectric each time
`charge is transferred to or away from the floating gate
`by programming or erasing, respectively.
`It is the primary object of the present invention to
`provide Eprom and EEprom cell and array structures
`and processes for making them that result in cells of
`reduced size so their density on a semiconductor chip
`can be increased. It is also an object of the invention
`that the structures be highly manufacturable, reliable,
`scalable, repeatable and producible with a very high
`yield.
`It is yet another object of the present invention to
`provide EEprom semiconductor chips that are useful'
`for solid state memory to replace magnetic disk storage
`devices.
`
`Another object of the present invention is to provide
`a technique for increasing the amount of information
`that can be stored in a given size Eprom or EEprom
`array.
`.
`Further, it is an’ object of the present invention to
`provide a technique for increasing the number of pro-
`gram/read cycles that an EEprom can endure.
`SUMMARY OF THE INVENTION
`
`These and additional objects are accomplished by the
`various aspects of the present invention, either alone or
`in combination, the primary aspects being briefly sum-
`marized as below:
`-
`
`l. The problems associated with prior art split chan-
`nel Eprom and split channel Flash EEprom devices are
`overcome by providing a split channel memory cell
`constructed in one of the following ways:
`(A) In one embodiment, one edge of the floating gate
`is self aligned to and overlaps the edge of the drain
`diffusion and the second edge of the floating gate is self
`aligned to but is spaced apart from the edge of the
`source diffusion. A sidewall spacer formed along the
`second edge of the floating gate facing the source side is
`used to define the degree of spacing between the two
`edges. Self alignment of both source and drain to the
`edges of the floating gate results in a split channel
`Eprom device having accurate control of the three most
`critical device parameters: Channel segment lengths L1
`and L2 controllable by floating gate and control gate,
`respectively, and the extent of overlap betWeen the
`floating gate and the drain diffusion. All three parame-
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`3
`ters are insensitive to mask misalignment and can be
`made reproducibly very small in scaled-down devices.
`(B) In a second embodiment of the split channel
`Eprom a heavily doped portion of the channel adjacent
`to the drain diffusion is formed by a novel, well—con-
`trolled technique. The length Lp and doping concentra-
`tion of this channel portion become the dominant pa—
`rameters for programming and reading, thereby permit-
`ting the formation of a split channel structure which is
`relatively insensitive to misalignments between the
`floating gate and the source/drain regions.
`2. A separate erase gate is provided to transform a
`Eprom device into a Flash EEprom device. The area of
`overlap between the floating gate and the erase gate is
`insensitive to mask misalignment and can therefore be
`made reproducibly very small.
`3. In some embodiments of this invention, the erase
`gate is also used as a field plate to provide very compact
`electric isolation between adjacent cells in a memory
`array.
`4. A new erase mechanism is provided which em—
`ploys tailoring of the edges of a very thin floating gate
`so as to enhance their effectiveness as electron injectors.
`5. A novel intelligent programming and sensing tech-
`nique is provided which permits the practical imple-
`mentation of multiple state storage wherein each
`Eprom or flash EEprom cell stores more than one bit
`per cell.
`6. A novel intelligent erase'algorithm is provided
`which results in a significant reduction in the electrical
`stress experienced by the erase tunnel dielectric and
`results in much higher endurance to program/erase
`cycling.
`The combination of various of these features results
`in new split channel Eprom or split channel Flash EE-
`prom devices which are highly manufacturable, highly
`scalable, and offering greater storage density as well as
`greater reliability than any prior art Eprom or Flash
`EEprom devices. Memories that utilize the various
`aspects of this invention are especially useful in com-
`puter systems to replace existing magnetic storage
`media (hard disks and floppy disks), primarily because
`of the very high density of information that may be
`stored in them.
`
`Additional objects, features and advantages of the
`present invention will be understood from the following
`description of its preferred embodiments, which de-
`scription should be taken in conjunction with the ac-
`companying drawings.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a cross section of the split channel Flash
`EEprom Samachisa prior art cell which erases by tun-
`neling of electrons from the floating gate to the drain
`diffusion.
`FIG. 2a is a cross section of the Flash EEprom Ky-
`nett prior art cell which erases by tunneling of electrons
`from the floating gate to the source diffusion.
`FIG. 2b is a cross section of the Flash EEprom
`Kupec prior art cell with triple polysilicon.»
`-
`FIG. 2c is a schematic of the Kupec cell during erase.
`FIG. 3a is a topological view of the triple polysilicon
`split channel Flash EEprom prior art Masuoka cell
`which erases by tunneling of electrons from the floating
`gate to an erase gate.
`FIG. 3b is a schematic view of the Masuoka prior art
`cell of FIG. 3a.
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`FIG. 30 is a view of the Masuoka prior art cell of
`FIG. 3a along cross section AA.
`FIG. 3d is a cross section view of the split channel
`Eprom Harari prior art cell.
`FIG. 4a is a cross section view of the split channel
`Eprom Eitan prior art cell having a drain diffusion self
`aligned to one edge of the floating gate.
`FIG. 4b is a cross section view of the prior art Eitan
`cell of FIG. 4a during the process step used in the for-
`mation of the self aligned drain diffusion.
`FIG. 4c is a cross section view of the split channel
`Eprom Mizutani prior cell with sidewall spacer forming
`the floating gate.
`FIG. M is a cross section View of the split channel
`Eprom Wu prior art cell with sidewall spacer forming
`one of two floating gates.
`FIG. 4e is a cross section view of a stacked gate
`Eprom Tanaka prior art cell with heavily doped chan-
`nel adjacent to the drain junction.
`FIG. 5a is a cross section of a split channel Eprom
`cell in accordance with this invention.
`FIGS. 5b through 5f are cross sections of the cell of
`FIG. 5:: during various stages in the manufacturing
`process.
`FIG. 6a is a top view of a 2X2 array of Flash EE-
`prom cells formed in a triple layer structure in accor-
`dance with one embodiment of this invention.
`FIG. 6b is a view along cross section AA of the struc-
`ture of FIG. 6a.
`.
`.
`
`FIG. 7a is a top view of a 2X2 array of Flash EE-
`prom cells formed in a triple layer structure in accor-
`dance with a second embodiment of this invention
`wherein the erase gates also provide field plate isola-
`tion.
`
`FIG. 7b is a view along cross section AA of the struc-
`ture of FIG. 7a.
`FIG. 7c is a view along cross section CC of the struc-
`ture of FIG. 7a.
`
`FIG. 8a is a top view of a 2x2 array of Flash EE-
`prom cells formed in a triple layer structure in accor-
`dance with a third embodiment of this invention
`wherein the tunnel erase dielectric is confined to the
`vertical surfaces at the two edges of the floating gate.
`FIG. 8b is a view along cross section AA of the struc-
`ture of FIG. 80.
`FIG. 9a is a top view of a 2X2 array of Flash EE-
`prom cells formed in a triple layer structure in accor-
`dance with a fourth embodiment of this invention
`wherein the erase gate is sandwiched in between the
`floating gate and the control gate.
`FIG. 9b is a view along cross section AA of the struc-
`ture of FIG. 911.
`FIG. 9c is a view along cross section DD of the struc-
`ture of FIG. 9a.
`FIG. 10 is a schematic representation of the coupling
`capacitances associated with the floatings gate of the
`Flash EEprom cell of the invention.
`FIG. lla is 'a schematic representation of the compos-
`ite transistor forming a split channel Eprom device.
`FIG. 11b shows the programming and erase charac-
`teristics of a split channel Flash EEprom device.
`FIG. 11c shows the four conduction states of a split
`channel Flash EEprom device in accordance with this
`invention.
`
`FIG. 11d shows the program/erase cycling endur-
`ance characteristics of prior art Flash EEprom devices.
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`FIG. lle shows a circuit schematic and program-
`ming/read voltage pulses required to implement multi-
`state storage.
`FIG. 12 outlines the key steps in the new algorithm
`used to erase with a minimum stress.
`FIG. 13 shows the program/erase cycling endurance
`characteristics of the split channel Flash EEprom de-
`vice of this invention using intelligent algorithms for
`multistate programming and for reduced stress during
`erasing.
`FIGS. 14a, 14b and 14c are cross sections of another
`embodiment of this invention during critical steps in the
`manufacturing flow.
`FIGS. 15a and 15b are schematic representations of
`two memory arrays for the Flash EEprom embodi-
`ments of this invention.
`FIGS. 16a and 16b are cross sectional views of Flash
`EEprom transistors, illustrating the erase mechanism by
`asperity injection (16a) and sharp tip injection (16b).
`FIGS. 16c and 16d are cross sectional views of parts
`of Flash EEprom transistors illustrating the formation
`of sharp-tipped edges of the floating gate by directional
`etching to facilitate high field electronic injection.
`FIG. 170 contains Table I which shows voltage con-
`ditions for all operational modes for the array of FIG.
`15a.
`FIG. 17b contains Table II which shows example
`voltage conditions for all operational modes for the
`virtual ground array of FIG. 15b.
`
`DETAILED DESCRIPTION OF THE PRIOR ART
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`near the drain junction. Injected electrons are trapped
`on floating gate 104 and raise the conduction threshold
`voltage of channel region 112 and therefore of transistor
`100. To erase transistor 100 the oxide in region 112
`separating between the floating gate 104 and drain diffu—
`sion 102 and channel 112 is thinned to between 15 and
`20 nanometers, to allow electronic tunneling of trapped
`electrons 108 from the floating gate to the drain. In the
`Samachisa cell
`the appropriate voltages applied to
`achieve
`programming
`are ch= 12V, VD=9V
`VBB=OV, Vs=OV, and to achieve erase are ch=OV,
`VD=19V, VBB=OV, V5=floating. Samachisa points
`out that the electrical erase is not selflimiting. It is
`possible to overerase the cell, leaving the floating gate
`positively charged, thus turning the channel portion L1
`into a depletion mode transistor. The series enhance-
`ment transistor L2 is needed therefore to prevent tran-
`sistor leakage in the overerase condition.
`The Samachisa cell suffers from certain disadvan-
`tages. These are:
`.
`(a) It is difficult to prevent avalanche junction break-
`down or high junction leakage current at the drain
`junction 102 during the time the very high erase voltage
`is applied to the drain;
`(b) It is difficult to grow with high yields the thin
`oxide layer 112 used for tunnel erase;
`(c) Because of the presence of thin oxide layer be-
`tween the floating gate and the drain diffusion,
`it is
`difficult to prevent accidental tunneling of electrons
`from the floating gate to the drain in what is known as
`the “program disturb” condition. Under this condition
`an unselected cell in a memory array sharing the same
`drain (bit line) as a programmed cell may have a drain
`voltage of approximately 10 volts and a control gate
`voltage of 0 volts. Although this represents a much
`weaker electric field than that experienced during tun-
`nel erase (when the drain is at approximately 19 volts),
`it nevertheless can, over a prolonged period of time
`alter by slow tunneling the charge stored on the floating
`gate.
`The Kynett and Kume cells (FIG. 2a) are similar to
`the Samachisa cell except for the elimination of the
`series enhancement transistor 120, and the performing
`of tunnel erase 208 over the source diffusion 201 rather
`than over the drain diffusion 202. Typically the Kynett
`cell uses during programming voltages Vcc=12V,
`VD: 8V, V5=0V, VBB=OV, and during erase voltages
`Vs=12V, V35=OV, Vc5=OV, VD=Floating. Ky-
`nett achieves a lower erase voltage than Samachisa by
`thinning tunnel dielectric 212 to 10 nanometers or less,
`so that even though the voltage applied to the source
`diffusion during erase is reduced, .the electric field
`across tunnel dielectric 212 remains as high as in the
`case of the Samachisa cell.
`The Kynett cell can be contrasted with the Sama-
`chisa cell:
`(a) Kynett is less susceptible to avalanche breakdown
`of source diffusion 201 during erase because the voltage
`is reduced from 19 volts to 12 volts.
`(b) Kynett’s cell is more susceptible to low yields due
`to pinholes in the thin dielectric layer 212 because its
`thickness is reduced from approximately 20 nanometers
`to approximately 10 nanometers.
`(c) Because Kynett uses a lower voltage for erase but
`essentially the same drain voltage for programming
`Kynett is far more susceptible to accidental “program
`disturb" due to partial tunnel erase (during program-
`ming) occuring from floating gate 204 to drain 202.
`
`There are two distinctly different approaches in the
`prior art of Flash EEproms. A triple polysilicon device
`was described by J. Kupec et al. in 1980 IEDM Techni-
`cal Digest, p. 602 in an article entitled “Triple Level
`Polysilicon EEprom with Single Transistor per Bit”.
`An improvement to the Kupec device was proposed by
`F. Masuoka and H. Iizuka in US. Pat. No. 4,531,203,
`issued July 23, 1985. Variations on the same cell are
`described by C. K. Kuo and S. C. Tsaur in US. Pat. No.
`4,561,004 issued Dec. 24, 1985, and by F. Masuoka et a].
`in an article titled “A 256K Flash EEprom Using Triple
`Polysilicon Technology", Digest of Technical Papers,
`IEEE International Solid-State Circuits Conference, Feb-
`ruary 1985, p. 168.
`The second approach is a double polysilicon cell
`described by G. Samachisa et al., in an article titled “A
`128K Flash EEprom Using Double Polysilicon Tech-
`nology”, IEEE Journal of Solid State Circuits, October
`1987, Vol. 5022, No. 5, p. 676. Variations on this sec-
`ond cell are also described by H. Kume et al. in an
`article titled “A Flash-Erase EEprom Cell with an
`Asymmetric Source and Drain Structure”, Technical _
`Digest of the IEEE International Electron Devices Meet-
`ing, December 1987, p. 560, and by V. N. Kynett et al.
`in an article titled “An In-System Reprogrammable
`256K CMOS Flash Memory”, Digest of Technical Pa-
`pers, IEEE International Solid-State Circuits Conference,
`February 1988, p. 132. A cross-section of the Samachisa
`cell is shown in FIG. 1. Transistor 100 is an NMOS
`transistor with source 101, drain 102,.substrate 103,
`floating gate 104 and control gate 109. The