L \'
`
`RandalIL.Geiger DESIGN TECHNIQUES
`—
`
`PhillipE.AlIen
`
`FOR ANALOG AND
`
`1
`
`\
`
`BARNES“;ELNDBLE’
`51:1?-
`
`
`
`—
`
`NoeIFl.Strader
`
`DIGITAL CIRCUITS
`#
`
`5W fi
`
`-
`
`Page 1 of 30
`
`PETITIONER'S EXHIBIT 1012
`
`Page 1 of 30
`
`PETITIONER'S EXHIBIT 1012
`
`

`

`This book was set in Times Roman by Publication Services, Inc.
`The editors were Alar E. Elken and John M. Morriss;
`the production supervisor was Janelle S. Travers.
`The cover was designed by Robin Hessel.
`Project supervision was done by Publication Services, Inc.
`Arcata GraphicsfHalliday was printer and binder.
`
`VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS
`
`Copyright © 1990 by McGraw—Hill, Inc. All rights reserved. Printed in the United States
`of America. Except as permitted under the United States Copyright Act of 1976, no part of
`this publication may be reproduced or distributed in any form or by any means, or stored
`in a data base or retrieval system, without the prior written permission of the publisher.
`
`254567890 HDHD 99876543210
`
`ISBN D-D?—DEE|EEEl—=l
`
`Library of Congress Cataloging-in—Publication Data
`
`1
`
`1.0
`1.1
`1.2
`1.3
`1.4
`1.5
`1.6
`
`ISBN 0-07-023253-9
`
`Geiger, Randall L.
`VLSI design techniques for analog and
`digital circuits.
`(McGraw-Hill series in electrical engineering)
`Includes index.
`1. Integrated circuits—Very large scale
`integration—Design and construction. I. Allen, P. E.
`(Phillip E.) II. Strader, Noel R. 111. Title.
`IV. Series.
`TK7874.G43 1990
`
`621.381‘73
`
`88-37737
`
`Page 2 of 30
`
`PETITIONER'S EXHIBIT 1012
`
`

`

`mama SYSTEMS 615
`
`Bipolar digital logic
`I
`MOS digital logic
`4————-——p|
`
`I
`
`Optical
`
`I
`
`Discrete-time
`analog (CCD.SCF)
`
`I
`|
`I Surface
`acoustic waves
`
`1H:
`
`10
`
`100 1kHz
`
`1O
`
`1DO1MHZ 10
`
`1001GHZ 101WGHZ
`
`FIGURE 8.1-3
`
`Signalbandwidth
`
`Signal bandwidths that can be processed by present—day (1989) technologies.
`
`8.2 DIGITAL-TO-ANALOG CONVERTERS
`
`The ability to convert digital signals to analog and vice versa is very important
`in signal processing. This section will examine the digital-to-analog conversion
`aspect of this important interface. Analog-to-digital conversion will be discussed
`in the next section. Most of the discussion in these two sections will be indepen-
`dent of whether the technology is BJT or MOS. The op amps and comparators
`used can be of either type. The switches will be MOS. The resistors and capac-
`itors can be implemented by either technology, depending on the performance
`requirements.
`Figure 8.2—1 illustrates how analog—todigital (ND) and digital-to-analcg
`(DEA) converters are used in data systems.2 In general, an AID conversion
`process will convert a sampled and held analog signal
`to a digital word that
`is a representation of the analog sampled signal. Often, many analog inputs are
`multiplexed to the AID converter. The DIA conversion process is essentially the
`inverse of the AID process. Digital words are applied to the input of the DEA
`converter to create from a reference voltage an analog output signal that is a
`representation of the digital word.
`'
`This section will introduce the principles of BM converters and will then
`discuss the performance characterization of DEA converters. The various types
`of linear DEA converters that will be examined include current-scaling, voltage-
`scaling, charge-scaling, combinations of the preceding types, and serial DIA
`converters. In the next section, we will see that DJA converters have an important
`role in the design and implementation of some AID converters.
`
`
`
`Page 3 of 30
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`PETITIONER'S EXHIBIT 1012
`
`Page 3 of 30
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`PETITIONER'S EXHIBIT 1012
`
`

`

`616
`
`VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS
`
`Multiplexer
`
`
`
`
`A/D
`converter
`
`Digital
`
`systems
`
`Reference
`
`(8)
`
`Transmission links
`Magnetic tape
`recorders
`Computer memories
`Paper tape recorders
`Punched cards
`
`Real-time processor
`Comparators
`System and 'process
`controls
`Numerical machine
`controls
`Minicomputers
`Microcomputers
`
`->
`
`->
`'
`' Digital
`'
`system '
`'
`'
`‘
`'
`
`
`
`D/A
`converter
`
`Amplifier
`
`
`
`Reference
`
`Audio systems
`Controllers
`Actuators
`CRT displays
`Analog recorders
`Analog computers
`Hybrid computers
`Analog meters
`Transducers
`Servomotors
`X-Y plotters
`Circuit test fixtures
`Component test
`fixtures
`Synchros/resolvers
`
`Analog computer
`Audio signals
`Video signals
`Power sources
`Chemical cells
`Synchros/resolvers
`Pressure cells
`
`Thermocouples
`Strain gauges
`Bridges
`Photomultiplier
`
`Transmission links
`
`Magnetic tape
`recorders
`Computer memories
`Paper tape recorders
`Punched cards
`Real-time processor
`Comparators
`System and process
`controls
`
`Numerical machine _,
`controls
`Minicomputers
`Microcomputers
`
`FIGURE 8.2-1
`
`Converters in signal processing systems: (a) A/D, (b) D/A.
`
`(b)
`
`Figure 8.2-2a shows a conceptual block diagram of a D/A converter. The
`inputs are a digital word of N bits (b1, b2, b3, .
`.
`.
`, 1m) and a reference voltage,
`Vref. The voltage output, VOUT, can be expressed as
`
`where K is a scaling factor and the digital word D is given as
`
`VOUT = K VrefD
`
`(8.2-1)
`
`(8.2-2)
`
`N is the total number of bits of the digital word, and bi is the ith bit coefficient
`and is either 0 or 1. Thus, the output of a D/A converter can be expressed by
`combining Eqs. 8.2-1 and 8.2-2 to get
`
`b3
`b2
`b1
`_
`VOUT—KVref§_1+§+§+
`
`bN
`-.- + 2—N_
`
`(8.2-3)
`
`
`
`Page 4 of 30
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`PETITION ER'S EXHIBIT 1012
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`Page 4 of 30
`
`PETITIONER'S EXHIBIT 1012
`
`

`

`ANALOG SYSTEMS
`
`617
`
`Vref
`
`
`
`D/A
`converter
`
`Vour Sample VOUT'
`and
`'
`hold
`
`--
`
`- Clocks
`
`(a)
`
`FIGURE 8.2-2
`
`(b)
`
`((1) Conceptual block diagram of a D/A converter, (b) Clocked D/A converter.
`
`01‘
`
`VOUT =KVref<b12—1 + [722—2 + b32_3 +
`N
`
`+ bN 2_N)
`
`=erefZ b; 2‘1
`j =1
`
`(8.2-4)
`
`In many cases, the digital word is synchronously clocked. In this case it is
`necessary to use latches to hold the word for conversion and to provide a sample-
`and-hold circuit at the output, as Shown in Fig. 8.2—2b. A voltage that has been
`sampled and held is denoted by an asterisk. The sample—and-hold circuit consists
`of a circuit such as that shown in Fig. 8.2-3, where the analog Signal is sampled
`
`wM’W
`
`‘1)
`
`$01..
`
`Volts
`
`
`
`
`
`Switch
`1
`Switch
`closed —>|<—- Switch open —>i<—-— closed ——>
`
`
`
`
`(sample)
`I
`(hold)
`'
`(sample)
`
`V1(t)
`
`(b)
`
`FIGURE 8.2-3
`(a) Simple sample-and-hold circuit, (b) Waveforms illustrating the operation of the sample-and-hold.
`
`Page 5 of 30
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`PETITIONER'S EXHIBIT 1012
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`
`PETITIONER'S EXHIBIT 1012
`
`

`

`618
`
`VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS
`
`on a capacitor, CH, when the switch is closed; this is called the sample mode.
`During the time that the switch is open, or the hold mode, the voltage at time
`to remains available at the output. An alternate version of the sample-and-hold
`circuit with higher performance is shown in Fig. 8.2-4. It is important that the
`sample-and-hold circuit be able to rapidly track changes in the input voltage
`when in the sample mode and not discharge the capacitor when in the hold
`mode.
`
`The basic architecture of the D/A converter without an output sample-and—
`hold circuit is Shown in Fig. 8.2-5. The various blocks are a voltage reference,
`which can be externally supplied, binary switches, a scaling network, and an
`output amplifier. The voltage reference, binary switches, and scaling network
`convert the digital word as either a voltage or current signal, and the output
`amplifier converts this signal to a voltage signal that can be sampled without
`affecting the value of the conversion.
`The characterization of the D/A converter is very important in understanding
`its use and design. The characteristics of the D/A converter can be divided into
`static and dynamic properties. The static properties are independent of time and
`include the converter transfer characteristic, quantization noise, dynamic range,
`gain, offset, and nonlinearity.3
`Figure 8.2-6 Shows the transfer characteristic of an ideal D/A converter.
`This D/A converter has been designed so that the analog output occurs at odd
`multiples of the full scale signal (FS) divided by 16. The right-most bit of the
`digital input code is called the least significant bit (LSB). Each time the LSB
`changes, the analog output changes by FS/2N , where N is equal to the number
`of digital bits. Although this change is an analog quantity, it is often called an
`LSB change and should be interpreted as the analog change due to a change in
`the LSB of the digital input code.
`The resolution of a converter is the smallest analog change that can be
`distinguished by an A/D converter or produced by a D/A converter. Resolution
`may be Stated in percent of FS, but is commonly expressed in number of bits,
`N, where the converter has 2” possible States. The finite resolution of converters
`causes an inherent uncertainty in digitizing an analog value. This uncertainty
`is called the quantization noise and has a value of up to i0.5 LSB. In the
`characteristic of Fig. 8.2-6,
`the quantization noise is seen to be $0.5 LSB
`
`
`
`FIGURE 8.2-4
`An improved sample-and-hold circuit.
`
`Page 6 of 30
`
`PETITIONER'S EXHIBIT 1012
`
`Page 6 of 30
`
`PETITIONER'S EXHIBIT 1012
`
`

`

`Voltage
`reference
`
`Vraf
`
`ANALOG SYSTEMS
`
`619
`
`Vour =KDV,“
`
`Dvref
`
`Output
`amplifier
`
`'
`
`b1 Q be
`
`h“
`
`FIGURE 8.2-5
`Block diagram of a DIA converter.
`
`or iFSfZN +1 about each of the multiples of FSi’S. The straight line in Fig. 8.2-6
`through the midpoint of each analog step change represents the ideal performance
`of the DEA converter as N approaches infinity.
`The full scale range (FSR) is the difference between the maximum and
`minimum analog values and is equal to F8 in Fig. 8.2-6 as N approaches infinity.
`The dynamic range (DR) of a noiseless converter is the ratio of the FSR to the
`smallest difference it can resolve. Thus, the DR can be given as
`
`or in terms of decibels as
`
`DR = 2N
`
`DR(dB) = 2010mm”) = 6.02N
`
`(3.2-5)
`
`(8.2-6)
`
`
`
`
`
`000
`
`001 010 011 100 101 110 111
`Digital input code
`
`02mb ‘
`
`5S
`
`-DO
`D)
`2(UC
`«.1:
`
`FIGURE 8.2-6
`
`Ideal input-output characteristics for a 3—bit DIA converter.
`
`
`
`Page 7 of 30
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`PETITIONER'S EXHIBIT 1012
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`PETITIONER'S EXHIBIT 1012
`
`

`

`620
`
`VLSl DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS
`
`in characterizing the capability
`The signal-to-noise ratio (S/N) is also useful
`of a converter. Assume that an analog ramp input is applied to an ideal A/D
`converter cascaded with an ideal D/A converter. If the analog output of the D/A
`converter is subtracted from the original analog ramp input, a sawtooth wave-
`form of iFS/2N +1 results. This sawtooth waveform represents the ideal quan-
`tization noise and has an rms value of (FS/ZN )/\/E. The S/N expressed as a
`power ratio in dB can be found from the ratio of the peak—to-peak signal, F8,
`to the noise as
`
`S/N(dB)
`
`
`lOlogm FS/[2N(12)1/2]]
`
`FS
`
`2
`
`=2010g10(2N) + 2010g10(12)1/2 = 6.02N + 10.8
`
`(8.2-7)
`
`It can be seen that the S/N ratio increases by a factor of approximately 6 dB for
`each additional bit of resolution.
`
`The remaining static characteristics include ofi‘set error, gain error, non-
`linearity, and nonmonotonicity. Figure 8.2-7 illustrates the first three of these
`characteristics for a 3-bit D/A converter. In each case the ideal characteristic of
`
`Fig. 82-6 is shown by dashed lines for comparison. An illustration of offset error
`is shown in Fig. 8.2-7a. An offset error is seen to be a vertical shift in the D/A
`transfer characteristic of the ideal D/A transfer characteristic. The offset error is
`
`defined as the analog output value by which the transfer characteristic fails to
`pass through zero. It may be expressed in millivolts or percent of FS.
`Figure 8.2-7b illustrates the gain or scale factor error of a 3-bit D/A
`converter. The gain or scale factor error is defined as the difference in the full
`scale values between the ideal and actual transfer characteristics when the offset
`
`error is zero and may be expressed in percent of full scale.
`in a 3-bit D/A
`Figure 8.2-7c is an illustration of nonlinearity error
`converter. Nonlinearity is further divided into integral nonlinearity and differential
`nonlinearity. Integral linearity is a global measure of nonlinearity of the converter
`and is defined as the maximum deviation of the actual transfer characteristic from
`
`a straight line drawn between zero and the FS of the ideal converter. Integral
`nonlinearity is expressed in terms of percent of FS or in terms of LSBs. In the
`characteristics of Fig. 82-76, the maximum deviation, which occurs at 111,
`is
`—l.5 LSB or —18.75% of FS.
`
`Differential nonlinearity is defined as the maximum deviation of any of the
`analog output changes caused by an LSB change from its ideal size of FS/2N or
`1 LSB. It is typically expressed in terms of :LSBs. In the characteristic of Fig.
`8.2-7c, the maximum deviation also occurs at 111 and is a differential nonlinear—
`
`ity of :1 LSB. The characteristic of Fig. 8.2-8 shows how differential nonlin-
`earity differs from integral nonlinearity. Figure 8.2-8a is for a 4-bit D/A converter
`having :2 LSB integral nonlinearity and $0.5 LSB differential nonlinearity.
`Figure 8.2-8b illustrates a 4-bit D/A converter having i 0.5 LSB integral non-
`linearity and i 1 LSB differential nonlinearity.
`
`Page 8 of 30
`
`PETITIONER'S EXHIBIT 1012
`
`Page 8 of 30
`
`PETITIONER'S EXHIBIT 1012
`
`

`

`
`
`Offset
`error
`
`
`
`ANAIDG SYSTEMS 62]
`
`s
`9
`‘5
`%
`o
`
`3
`as
`I:
`4:
`
`7!:
`
`
`
`
`000 001010 011 100101 110111
`
`Digital input code
`(I!)
`
`00 001010 011100101 110111
`
`Digital inputcode
`(a)
`
`
`
`
`FS
`
`? §
`
`FSs
`s 3‘3
`3 §Fs
`‘5 i
`% -Fs
`o 3
`
`3' 9F3
`as 3
`I: 2
`:1: -FS
`
`s 1B
`
`FS
`
`00
`
`
`
`Nonlinean'ty
`
`00 0011310 011100101 110111
`
`Digital inputcode
`{8}
`
`FS
`
`.7
`BFS6
`
`u 5
`:1 EFS
`@- EFS
`o 8
`
`.3” §Fs
`m 8
`5 2F88
`
`1s
`
`FS
`
`00
`
`FIGURE 3.2-7
`Examples of various types of static characteristics for a 3-bit DEA converter: (:1) Offset error, (b)
`Gain error, (e) Nonlinearity.
`
`Figure 8.2-9 illustrates a 3-bit DKA converter that is not monotonic. A
`monotonic DEA converter is one in which an increasing digital input code produces
`a continuously increasing analog output value. A nonrnonotonic Di’A converter
`can result if the differential nonlinearity error exceeds +l LSB.1n Fig. 8. 2-9, a
`differential nonlinearity of + 1.5 LSB occurs at a digital input code of 001. Note
`that there are two occurrences of nonmonotonicity in Fig. 8. 2-9
`The dynamic characteristics of the BIA converter are associated with chang-
`es in the input digital word. The time required for the output of the converter to
`
`
`
`Page 9 of 30
`
`PETITION ER'S EXHIBIT 1012
`
`Page 9 of 30
`
`PETITIONER'S EXHIBIT 1012
`
`

`

`622
`
`VLS] DESIGN TECHNIQUES FOR mm min DIGITAL CIRCUITS
`
`10
`
`9
`
`,__ 3
`0:1
`
`3 7
`Tu
`
`fl 6
`
`E s
`
`a 3
`
`’ 4
`g 3
`
`0110
`0100
`0010
`000
`0001
`0011
`0101
`0111
`
`1010
`1000
`1001
`
`Digital word input
`(a)
`
`
`
`
`2 1 00
`
`10
`
`9
`
`h am
`‘3 7
`
`a E
`
`s
`
`:9; 5
`. 49
`g 3
`2
`
`8u
`
`FIGURE8.2-8
`Distinction between integral and
`differential nonlinearity for a DEA
`converter: (a BM converter with :2
`LSB integral nonlinearily and 10.5
`
`0000
`
`0010
`
`0100
`
`0110
`
`1000
`
`1010
`
`CI
`.
`.
`D'g'lal wor
`(b1
`
`.
`Input
`
`converter with 10.5 LSB integral
`nonlinearity and :1 LSB differential
`nonlinearity.
`
`Page 10 of 30
`
`PETITIONER'S EXHIBIT 1012
`
`Page 10 of 30
`
`PETITIONER'S EXHIBIT 1012
`
`

`

`
`
`“l10‘}
`
`ANALOG SYSTEMS 623
`
`‘I10‘)
`
`'I'IU) Analog
`
`
`
`col—ncalmcalma3_:1-hcalmable::2on a:
`
`
`“l1CD
`
`'I"IU)
`
`"I10'!
`
`
`
`outputvalue
`
`000
`
`001
`
`010
`
`101
`100
`011
`Digital input code
`
`110
`
`111
`
`FIGURES-24"
`Example of a3—blt DEA con—
`verter that is not monotonic.
`
`respond to a bit change is called the settling time and is defined similarly to the
`settling time for op amps in Fig. 6.5-2] . Settling time for Di’A converters depends
`on the type of converter and can range from as much as 100 its to less than 100
`ns.
`
`Many techniques have been used to implement DEA converters. Three ap-
`proaches that are compatible with integrated circuit technology will be examined.
`These methods are current-scaling or division, voltage~scaling or division,
`and charge-scaling or division. Current-scaling is widely used with BJT techno-
`logy. whereas voltage- and chargevscaling are popular for MOS technology.
`
`8.2.1 Current-Scaling DIA Converters
`
`The general principle of current-scaling or division DEA converters is shown in
`Fig. 8.2—10a. The reference voltage is converted to binary-weighted currents,
`11,12,13,....IN . An implementation of this technique using resistors is shown
`in Fig. 8.2-106. Each of the switches, 53, is connected to Vref if the ith bit, 16,-,
`is l and to ground if b,- is 0. It is seen that the output voltage of the op amp can
`be expressed as
`'
`
`—R as + b_2 + 3
`VOHIZ—IO=—
`2
`2 R
`2!?
`4R
`
`+...+
`
`
`bn
`v
`2N‘1R “‘
`
`= —V,e;{b]2_1 + 5122—? + 532—3 +
`
`+ by 2—”)
`
`(82-8)
`
`The feedback resistor, RF. can be used to achieve the scaling factor K of Eq.
`8.2—1. The switches can be moved from the me side of the resistors to the
`
`
`
`Page 11 of 30
`
`PETITIONER'S EXHIBIT 1012
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`

`

`624
`
`VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS
`
`Digital
`input code
`
`
`
`{b}
`
`FIGURE 8.2-1!)
`(a) Conceptual illustration of a current-scaling DIA converter. (b) Implementation of (a).
`
`side connected to the inverting input of the op amp. The advantage of the latter
`configuration is that the voltages at the switch terminals are always ground. As
`a consequence, the switch parasitic capacitances are not charged or discharged.
`The binary-weighted resistor ladder configuration of Fig. 82-10!) has the
`disadvantage of a large ratio of component values. For example, the ratio of the
`resistor for the MSB, RMSB, to the resistor for the LSB, RLSB, is
`
`RMSB
`1
`RLSB
`21F,
`
`(8.2-9)
`
`For an 8-bit DIA converter, this gives a ratio of U128. The difficulty with this
`approach is that the accuracy of RMSB must be much better than that of the value
`of RLSB for the converter to work properly. For example, RMSB of an 8-bit DIA
`converter must have a relative accuracy with respect to RLSB to within 10.78%,
`and preferably better. Such accuracy is difficult to achieve without trimming the
`resistors, which is done for high-resolution DIA converters using binary-weighted
`components.
`
`
`
`Page 12 of 30
`
`PETITIONER'S EXHIBIT 1012
`
`Page 12 of 30
`
`PETITIONER'S EXHIBIT 1012
`
`

`

`ANALOG SYSTEM 625
`
`
`
`FIGURE 8.2-1]
`A current-scaling DEA converter using an R-2R ladder.
`
`An alternative to the binary-weighted approach is the use of an R-2R ladder.
`shown in Fig. 8.2-11. Each of the switches, SE, is connected to Q if the r'th bit
`is l and to ground if the ith bit is 0. Q is the inverting input of the op amp.
`Obviously, the current 11 is equal to VrefJZR. Using the fact that the resistance
`to the right of any of the vertical 2R resistors is 2R, we see that the currents ll,
`[2, I3, .
`.
`.
`, IN are binary-weighted and given as
`
`11: 212 = 413 =
`
`= 2"”er
`
`(8.2-10)
`
`Thus, the output voltage of the R-2R DEA converter of Fig. 8.2-“ is given by
`Eq. 8.2—8. Figure 8.2-” is an example of using the switches connected either to
`ground or the inverting terminal of the op amp. me and the inverting input of the
`op amp (point Q) can be interchanged if desired. While the R-2R DEA converter
`has twice as many resistors as the binary-weighted resistor DEA converter,
`it
`requires resistors with only the ratio of 2:1, which is more practical to accomplish.
`One disadvantage of the R-2R configuration is that there are up to 2” " floating
`nodes, which are sensitive to parasitic capacitances. Floating nodes are nodes
`with relatively large resistance to ground. The charging and discharging of these
`capacitances will require time and delay the response of the converter. Possible
`architectures for bipolar DIA converters using the R-2R ladder approach are shown
`in Fig. 8.2— 12. Note that the emitter areas of the BJT devices must be proportional
`to the emitter current in Fig. 82-1241.
`Two approaches for using binary-weighted Dr'A converters while keeping the
`M83 and LSB resistor ratios small deserve mention. The first is called cascading
`and is illustrated in Fig. 8.2-l3a. The use of a current divider allows two 4-bit,
`binary-weighted current sources to be cascaded to achieve an 8-bit Di’A converter.
`The accuracy of the 1:16 attenuating resistors must be within the magnitude of
`the LSB of the entire ladder. A second approach is shown in Fig. 8.2-l3b and
`is called the mster—slave ladder. In this approach, a master ladder consists of the
`
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`PETITIONER'S EXHIBIT 1012
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`PETITIONER'S EXHIBIT 1012
`
`

`

`626
`
`VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS
`
`
`
`
`
`
`
`{17)
`
`FIGURE 8.2-12
`Two implementations of DM converters using R—2R ladders and BJT current sinks. (a) Binary-
`weighted emitter areas, and (b) Equal emitter areas. Both converters are described by Von-r =
`—Rp1[bl + 2—le +
`+ 2” “b~].
`
`half of the bits that are most significant, and the slave ladder consists of the
`half of the bits that are least significant. The crucial point in this approach is the
`accuracy of the If 16 current source for the slave ladder. It must have accuracy
`better than :05 LSB.
`
`8.2.2 Voltage-Scaling DEA Converters
`
`Voltage-scaling uses series resistors connected between me and ground to selec—
`tively obtain voltages between these limits. For an N—bit converter, the resistor
`string would have at least 2” segments. These segments can all be equal or
`
`Page 14 of 30
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`PETITIONER'S EXHIBIT 1012
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`PETITIONER'S EXHIBIT 1012
`
`

`

`.____—.
`
`ANALOG svsnms 627
`
`Vour
`RF
`in
`1531 i
`Attenuating resistors —-:
`
`
`§
`
`
`
`(b)
`
`FIGURE 8.2-13
`(a) Use of current division to cascade two 4—bit, binary—weighted current sinks to get an 8-bit Di’A
`converter, (b) Master-slave technique to combine two 4-bit binary weighted current sources to obtain
`an 8-bit DIA converter. Note that I I = I 116.
`
`the end segments may be partial values, depending on the requirements. Figure
`8.2-l4a shows a 3—bit voltage scaling DEA converter. Note that the op amp is
`used simply to buffer the resistor string. Each tap is connected to a switching tree
`whose switches are controlled by the bits of the digital word. If the ith bit is 1,
`then the switches controlled by b5 are closed. If the 5th bit is 0, then the switches
`controlled by hi are closed.
`The voltage—scaling Di’A converter of Fig. 8.2-]4a works as follows.
`Suppose that the digital word to be converted is b] = Lb: = 0, and b3 2 1.
`Following the sequence of switches. we see that Vour is equal to 11! 16 of War.
`In general, the voltage at any tap i of Fig. 8.2-l4a can be expressed as
`
`v
`gift: — 0.5)
`
`(8.2-11)
`
`Vi:
`
`
`
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`PETITIONER'S EXHIBIT 1012
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`
`

`

`VOUT
`
`628
`
`VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS
`
`+ Vref
`
`:3
`
`AmwmwmAmmmmmummB
`
`13m
`
`
`Vref
`
`If:
`
`Vout
`
`
`
`0‘(.2
`
`ca
`
`re
`
`___0'
`
`m
`
`____O"
`
`
`
`
`000
`
`001 010 011
`
`100 101 110 111
`
`Input
`(b)
`
`FIGURE 8.2-14
`(a) Illustration of a 3-bit voltage-scaling D/A converter, (b) Input-output characteristics of a.
`
`Figure 8.2—14b shows the input-output characteristics of the D/A converter of Fig.
`8.2-14a. It may be desirable to connect the bottom tap to ground, so that a well-
`defined output (ground) is available when the digital word is all Os.
`
`Example 8.2-1. Find the accuracy requirement for a resistor string consisting of
`N equal segments as a function of the number of bits N. If the relative resistor
`accuracy is 2%, what is the largest number of bits than can be resolved to within
`: 0.5 LSB?
`
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`PETITIONER'S EXHIBIT 1012
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`
`

`

`ANALOG SYSTEMS 629
`
`Solution. The ideal voltage to ground across it resistors can be expressed as
`kR
`Vt = Evans
`
`The worst case variation in this voltage can be found by assuming that all resistors
`above this point in the string are maximum and below this point are minimum.
`Therefore, the worst case lowest voltage to ground across k resistors is
`kRminVREF
`V’ = ——
`(2" — mm + mm
`*
`
`The difference between the ideal and worst case voltages can be expressed as
`
`Vk
`V}:
`VREF
`VREF
`
`kRmin
`(2N _ K)Rmax + kRmin
`
`= fl _
`ZNR
`
`Since this difference must be less that 0.5 LSB, then the desired relationship can
`be obtained as
`
`k
`
`_
`
`kRmi"
`
`2”
`
`(2" — HRH.” + kRmin
`
`0.5
`é _
`2”
`
`The relative accuracy of the resistor R can be expressed as ARIR. which gives
`Rm = R + 0.5M and Rm“. = R — 0.5AR. Normally, the worst case occurs when
`k is midway in the resistor string or k = 0.50” ). Assuming a relative accuracy of
`2% and substituting the above values gives
`
`Solving this equation for N gives N = 6 as the largest integer.
`
`|0.01| < 2‘”
`
`It is seen that the voltage-scaling DEA structure is very regular and thus well
`suited for MOS technology. An advantage of this architecture is that it guarantees
`monotonicity, since the voltage at each tap cannot be greater than the tap below
`it. The area required for the voltage-scaling DIA converter is large if the number
`of bits is 3 or more. The converter will be sensitive to parasitic capacitances at
`each of the floating nodes resulting in signal delays.
`
`8.2.3 Charge-Scaling DIA Converters
`
`Charge-scaling BIA converters operate by dividing the total charge applied to
`a capacitor array. Typically, all capacitors are discharged first. Figure 8.2-]5a
`shows an illustration of a charge-scaling DfA converter. A nonoverlapping, two-
`phase clock is used. o1 indicates that a switch is closed during phase 1, and
`similarly for $2. During d)“ all capacitors in the array are discharged. Next,
`during (b2, the capacitors associated with bits that are l are connected to Vrcf and
`those with bits that are 0 are connected to ground. The resulting situation can be
`described by equating the charge on the capacitors connected to Vref (Ceq) to the
`charge in the total capacitors (Cm). This is expressed as
`
`Em C
`+ 2N-1 = CrotVOUT = 2CV0U1
`(8.2-12)
`
`b2C
`b3C
`meCeq = Vref bIC + —2“‘ + F +
`
`
`
`Page 17 of 30
`
`PETITIONER'S EXHIBIT 1012
`
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`
`PETITIONER'S EXHIBIT 1012
`
`

`

`630 um DESIGN TECHNIQUES FOR ammo AND DIGITAL CIRCUITS
`
`21v— 1
`
`Terminating
`capacitor
`
`i1’2"i3l1\1r
`2:92:6thVour
`
`FIGURE 8. 2-15
`
`{11) Charge--scaling DIA converter. switches designated as of); b-,--(¢»2 b) close if both 452 and b(bf )
`are true during 1152, ((1) Equivalent circuit of a.
`
`From Eq. 8.2-12 we may solve for Voo'r as
`
`Vow = (b12" + 1722'2 + b32‘3 +
`
`+ 1,1,2“)me
`
`(3.2-13)
`
`Another approach to understanding the circuit of Fig. 82-150 is to consider
`the capacitor array as a capacitive attenuator,
`illustrated in Fig. 8.2-15b. As
`before, Ceq consists of the sum of all capacitances connected to Vref, and Cm is
`the sum of all the capacitors in the array
`The DEA of Fig. 8.2-15a can be extended to have both + and — analog
`outputs if the bottom plates of all capacitors are connected to me during the (b1
`phase period. During the (15; phase period, the capcitance associated with b, C,
`is connected to ground if b is 1 or to Vref if b- is 0. The resulting output voltage
`is
`
`Vour = —(b12" + 522‘? + b32_3+
`
`+ bN 2‘N)Vwas
`
`(s 2.14)
`
`The decision to select the + or — output will require an additional sign bit. If
`me is also bipolar. then a four-quadrant DEA converter results.
`The accuracy of the capaCitors and the area required are both factors that
`limit the number of bits used. The accuracy of the DIA converter is seen to
`depend totally on the capacitor ratios and any parasitics. The accuracy of the
`equal-valued capacitor ratios for an MOS technology can be as low as 0.1% or
`better. If all of the capacitor ratios have this accuracy, then the DA converter
`
`Page 18 of 30
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`PETITIONER'S EXHIBIT 1012
`
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`
`PETITIONER'S EXHIBIT 1012
`
`

`

`ANALOG SYSTEMS
`
`631
`
`of Fig. 8.2—15a Should be capable of a 10-bit resolution. However, this implies
`that the ratio between the MSB and LSB capacitors will be 1024:1 which is
`undesirable from an area viewpoint. Also, the 0.1% capacitor ratio accuracy is
`applicable only for ratios in the neighborhood of unity.
`
`Example 8.2-2. Assume that unit capacitors of 50 p. X 50 ,u. are used in the charge-
`scaling D/A converters of Fig. 8.2-15a and that the relative accuracy is 0.1%. Find
`the number'of bits possible using a worst case approach assuming that the worst
`conditions occur at midscale (1 MSB). Next, assume that the relative accuracy of
`the unit capacitors deteriorates with N as given by
`
`A_: 2 0.001 + 0.0001N
`
`and find the number of bits possible using a worst case approach.
`
`Solution. From Fig. 8.2-15b the ideal output voltage of the charge-scaling D/A
`. converter can be expressed as
`
`
`Vour = E
`VREF
`2C
`
`Assume the worst-case output voltage is given as
`
`W = __L
`VREF
`[2C — Ceq](max) + Ceq(min)
`
`The difference between the ideal and the worst case output can be written as
`
`VOUT
`V (BUT
`
`Ceq( min)
`
`Ceq
`
`VREF
`
`VREF
`
`2C
`
`[2C — Ceq](max) + Ceq(min)
`
`If we assume that the worst—case condition occurs at midscale, then Ceq is equal to
`C. Therefore the difference between the ideal output and the worst—case output is
`
`VOUT
`V601-
`VREF
`VREF
`
`C (min)
`C( max) + C( min)
`
`1
`2
`
`Replacing C(max) by C + 0.5AC and C(min) by C — 0.5AC and setting the
`difference between the ideal and worst-case output voltage equal to $0.5 LSB
`results in the following equation
`
`E 1
`2C
`27
`
`Using a value of 0.001 for AC/C gives approximately 11 bits. Using the
`approximation for AC/ C of
`
`AC9 2 0.001 + 0.0001N
`shows that a 9-bit D/A converter should be realizable.
`
`The cascade configuration of Fig. 8.2-l3a can also be applied to the
`charge-scaling configuration. Figure 8.2—16a shows a 13-bit D/A converter with
`bipolar capability for Vref. The 1.016 pF capacitor acts as a 64:1 divider,
`
`
`
`Page 19 of 30
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`PETITION ER'S EXHIBIT 1012
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`
`

`

`632
`
`VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS
`
`which scales up the last 6 bits by a factor of 64. An equivalent circuit to the
`13-bit D/A converter is shown in Fig. 8.2-16b. Two voltage sources are shown
`that depend on the state of each of the switches. The right—hand voltage source
`is given as
`
`_bCV
`VR =.:§:—127 ”f
`i=1
`
`(8.2-15)
`
`where C,- = C/2"_l and the polarity of Vref depends on the polarity of the digital
`word. The left-hand voltage source is given as
`13
`:bCV
`VL=Z}—%ffi
`k=8
`
`sz)
`
`where Ck = C/(2k_7). The overall output of the D/A converter of Fig. 8.2—16a
`can be written as
`
`
`
`
`Ail switches
`within the
`<— dashed box
`are ANDed
`with it 2.
`
`
`
`FIGURE 8.2-16
`(a) A 13-bit, cascaded, charge-scaling D/A converter where C = 64 pF. Note that whether or not
`the switches in the dashed box close depends on the state of the binary variables, (b) An equivalent
`circuit of a.
`
`Page 20 of 30
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`PETITIONER'S EXHIBIT 1012
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`
`

`

`
`
`
`
`ANALOG SYSTEMS
`
`633
`
`
`
`(8.2-17)
`
`The charge-scaling DKA converters are sensitive to capacitive loading at
`the summing node. If this capacitance is designated as CL, then Eq. 8.2-]? is
`modified as
`
`“”(zac. +Zbkg
`V0“ 2 [I _ lzsjlw128
`
`
`i=1
`
`
`
`
`
`(8.2-18)
`
`We see that CL has caused an error of [l — (CLII28)]. If CL is 1% of the total
`ladder capacitance, then a 1% error is introduced by the capacitance CL.
`The accuracy of the capacitor attenuator must also be good enough for the
`cascade approach to work. A deviation of the 1.016 pF divider capacitance from
`the desired ratio of l.016:l introduces both gain and linearity errors. Assuming
`a variation of :AC in the 1.016 pF capacitor modifies the output given in Eq.
`8.2-l7to
`
`
`
`Ciao,- +(1 +AC)ZbkE—k
`
`
`i=1
`
`128
`
`
`
`(8.2-19)
`
`If we assume that AC} C = :0.016 (1.6% error). then the gain term has an error of
`
`G'
`
`amerror erm
`
`r
`
`l
`
`[128)
`
`1
`AC '
`= e—=1—— .2—20
`
`[(64)(123)]
`
`(8
`
`)
`
`which is negligible. The linearity error term is given by
`3
`Linearity error term = AC 2 bici
`k=8 64
`
`(8.2—21)
`
`The worst-case error occurs for all b,- = l and is essentially AC . It is also important
`to keep + Vrer and — me stable and equal in amplitude. This influences the long-
`term stability and gain tracking of the DEA converter.
`A different, charge redistribution, two-stage, 8-bit DEA converter is shown
`in Fig. 8.2-1?. An op amp is connected in its inverting configuration with the 2C
`capacitor fed back from the output to the inverting input of the op amp. Because
`the input node is a virtual ground during operation,
`the capacitive parasitics
`associated with the input node to the op amp are eliminated. The converter of
`Fig. 8.2-1? should give better transient response and less error because of the
`removal of the influence of the capacitive parasitic at the op amp input.
`
`8.2.4 DEA Converters Using Combinations of
`Scaling Approaches
`
`The voltage-scaling and charge-scaling approaches to implementing DEA convert-
`ers can be combined, resulting in converters having a resolution that exceeds the
`number of bits of the separate approaches. An M—bit resistor string and a K—bit
`binary-weighted capacitor array can be used to achieve an N = (M + K )-bit
`
`
`
`Page 21 of 30
`
`PETITIONER'S EXHIBIT 1012
`
`Page 21 of 30
`
`PETI