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DECLARATION OF R. JACOB BAKER, Ph.D.
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`I, R. Jacob Baker, hereby declare as follows:
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`1. My name is R. Jacob Baker. My findings as set forth herein, are
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`based on my education and background in the fields discussed below.
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`2.
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`I have been retained on behalf of Petitioner Micron Technology, Inc.
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`(“Micron”) to provide this Declaration concerning technical subject matter relevant
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`to the inter partes review petition (“Petition”) concerning U.S. Patent No.
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`5,764,571 (the “’571 patent”). I reserve the right to supplement this Declaration in
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`response to additional evidence that may come to light.
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`3.
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`I am over 18 years of age. I have personal knowledge of the facts
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`stated in this Declaration and could testify competently to them if asked to do so.
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`I.
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`Education, Experience, Publications, and Awards
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`4.
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`As indicated in my curriculum vitae, attached as Exhibit 1, I currently
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`serve as a Professor of Electrical and Computer Engineering at the University of
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`Nevada, Las Vegas (UNLV). I have been teaching electrical engineering at UNLV
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`since 2012. Prior to this position, I was a Professor of Electrical and Computer
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`Engineering with Boise State University from 2000. Prior to my position at Boise
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`State University, I was an Associate Professor of Electrical Engineering between
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`1998 and 2000 and Assistant Professor of Electrical Engineering between 1993 and
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`1998, both at University of Idaho. I have been teaching electrical engineering
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`since 1991.
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`5.
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`I received my Ph.D. in Electrical Engineering from the University of
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`Nevada, Reno in 1993. I also received a MS and BS in Electrical Engineering
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`from UNLV in 1988 and 1986, respectively.
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`6.
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`As further described in my CV, I am a licensed Professional Engineer
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`in the State of Idaho and have more than 25 years of experience, including
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`extensive experience in circuit design and manufacture of Dynamic Random
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`Access Memory (DRAM) integrated circuit chips and CMOS Image Sensors
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`(CISs) at Micron in Boise, Idaho. I also spent considerable time working on the
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`development of Flash memory while at Micron. My efforts resulted in more than a
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`dozen Flash-memory related patents. Among many other experiences, I led the
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`development of the delay-locked loop (DLL) in the late 90s so that Micron
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`products could transition to the DDR memory standard. I also provided technical
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`assistance with Micron’s acquisition of Photobit during 2001 and 2002. This
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`assistance included help transitioning the manufacture of CIS products into
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`Micron’s DRAM process technology. I have worked as a consultant at other
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`companies designing memory chips, including Sun, Oracle, and Contour
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`Semiconductor. I have worked at other companies designing CISs, including
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`Aerius Photonics and Lockheed-Martin. I am currently working on the design of
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`CISs and memory as a consultant for OmniVision.
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`7.
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`I have taught courses in integrated circuit design (analog, digital,
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`mixed-signal, etc.), linear circuits, microelectronics, communication systems, and
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`fiber optics. As a professor, I have been the main advisor to five Doctoral students
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`and over 50 Masters students.
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`8.
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`I am the author of several books covering the area of integrated circuit
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`design including: DRAM Circuit Design: Fundamental and High-Speed Topics
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`(two editions), CMOS Circuit Design, Layout, and Simulation (three editions), and
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`CMOS Mixed-Signal Circuit Design (two editions). I have authored, and co-
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`authored, more than 75 papers and presentations in the areas of solid-state circuit
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`design, and I am the named inventor on over 135 granted U.S. patents in integrated
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`circuit design including flash memory, DRAM, and CMOS image sensors.
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`9.
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`I have received numerous awards for my work, including the
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`Frederick Emmons Terman (the “Father of Silicon Valley”) Award. The Terman
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`Award is bestowed annually upon an outstanding young electrical/computer
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`engineering educator in recognition of the educator’s contributions to the
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`profession.
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`10.
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`I have also received the IEEE Circuits and Systems Education Award
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`(2011), the IEEE Power Electronics Best Paper Award (2000), and I am a Fellow
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`of the IEEE for contributions to memory circuit design.
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`11.
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`In addition, I have received the President’s Research and Scholarship
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`Award (2005), Honored Faculty Member recognition (2003), Outstanding
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`Department of Electrical Engineering Faculty recognition (2001), all from Boise
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`State University. I have also received the Tau Beta Pi Outstanding Electrical and
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`Computer Engineering Professor award the two years I have been at UNLV.
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`12.
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`I have also given over 50 invited talks at conferences and Universities
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`in the areas of integrated circuit design including: AMD, Arizona State University,
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`Beijing Jiaotong University, Carleton University, Carnegie Mellon, Columbia
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`University, Dublin City University (Ireland), École Polytechnique de Montréal,
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`Georgia Tech, Hong Kong University of Science and Technology, Indian Institute
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`of Science (Bangalore, India), Instituto de Informatica (Brazil), Instituto
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`Tecnológico y de Estudios Superiores de Monterrey, ITESM (Mexico), Iowa State
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`University, Laval University, Lehigh University, Princeton University, Temple
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`University, University of Alabama, University of Arkansas, University of Buenos
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`Aires (Argentina), University of Illinois, Urbana-Champaign, Utah State
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`University, University of Nevada, Las Vegas, University of Houston, University of
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`Idaho, University of Nevada, Reno, University of Macau, University of Toronto,
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`University of Utah, Yonsei University (Seoul, Korea), University of Maryland,
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`IEEE Electron Devices Conference (NVMTS), IEEE Workshop on
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`Microelectronics and Electron Devices (WMED), the Franklin Institute, Georgia
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`Tech, National Semiconductor, AMI semiconductor, Micron Technology,
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`Rendition, Saintgits College (Kerala, India), Southern Methodist University, Sun
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`Microsystems, Stanford University, ST Microelectronics (Delhi, India), Tower
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`(Israel), Foveon, ICySSS keynote, Xilinx, etc.
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`II. Materials Considered
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`13.
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`In addition to reviewing U.S. Patent No. 5,764,571, I also reviewed
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`and considered:
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`the prosecution history of the ’571 patent;
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`U.S. Patent No. 5,394,362;
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`U.S. Patent No. 5,218,569;
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`U.S. Appl. Ser. No. 07/337,579;
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`U.S. Patent No. 5,172,338;
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`U.S. Patent No. 4,952,821;
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`U.S. Patent No. 5,319,348;
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`U.S. Patent No. 5,095,344;
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`U.S. Patent No. 5,218,246;
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`U.S. Patent No. 4,809,224;
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`U.S. Patent No. 5,991,517;
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`U.S. Patent No. 4,964,079;
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`“An Experimental 2-bit / Cell Storage DRAM for Macrocell or Memory-on-
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`Logic Application” by Furuyama et al., IEEE Journal of Solid-State Circuits,
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`Vol. 24, No. 2, April 1989;
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`“MACMILLAN DICTIONARY OF MICROCOMPUTING,” Third Edition
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`(1985);
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`April 27, 2010, Tutorial Transcript, MLC Flash Memory Devices and
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`Products Containing Same, Inv. No. 337-TA-683, (January 19, 2011)
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`(Completed);
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`“Fundamentals of Digital Systems Design,” by Rhyne, 1973;
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`“VLSI Design Techniques for Analog and Digital Circuits,” by Geiger,
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`Allen, and Strader, McGraw-Hill, March 1989;
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`“An Introduction to Analog and Digital Communications,” by Simon S.
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`Haykin (1989);
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`U.S. Patent No. 4,415,992;
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`Japanese Patent Application Kokai No. S62-34398 (A);
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`U.S. Patent No. 4,449,203; and
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`U.S. Patent No. 5,119,330.
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`14. My compensation is not based on the resolution of this matter. My
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`findings, as explained below, are based on my education, experience, and
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`background in the fields discussed above.
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`III. Level of Ordinary Skill in the Art
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`15.
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`In my opinion, a person of ordinary skill in the art (POSITA) at the
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`time of the claimed invention(s) would have had a bachelor’s degree in computer
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`engineering, electrical engineering, computer science, or a closely related field,
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`along with at least 2-3 years of experience in the development and use of memory
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`devices and systems. An individual with an advanced degree in a relevant field,
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`such as computer or electrical engineering, would require less experience in the
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`development and use of memory devices and systems (e.g., 1-2 years).
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`16.
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`I reserve the right to amend or supplement this declaration if the
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`Board adopts a definition of a person of ordinary skill other than that described
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`above, which may change my conclusions or analysis.
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`17. My opinions below explain how a POSITA would have understood
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`the technology described in the references I have identified herein around the 1991
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`time period.
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`IV. Applicable Legal Standard
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`A.
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`Claim Construction
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`18.
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`I have been informed that in an inter partes review proceeding, the
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`claims of a patent are to be given their broadest reasonable meaning as they would
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`be understood by a POSITA, consistent with the specification of the patent. I have
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`been informed that the ’571 patent will expire on June 9, 2015. I have been
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`informed that when a patent is set to expire during the pendency of an inter partes
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`review the standard for claim construction shifts from the broadest reasonable
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`interpretation standard to the district court’s Markman standard. Under a
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`Markman standard, I have been informed that the claims of a patent are to be given
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`their meaning as understood by a POSITA at the time of invention in light of the
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`patent’s intrinsic evidence (e.g., specification and prosecution history) and, when
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`appropriate, extrinsic evidence (e.g., technical dictionaries). The constructions
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`proposed herein are consistent with the specification and claims (i.e., the intrinsic
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`evidence) and therefore should not be affected by the standard applied.
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`B. Anticipation and Obviousness
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`19.
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`I have been informed that a patent claim is invalid as anticipated
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`under 35 U.S.C. § 102 if each and every element of a claim, as properly construed,
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`is found either explicitly or inherently in a single prior art reference.
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`20.
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`I have been informed that a claim is invalid under 35 U.S.C. § 102(a)
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`if the claimed invention was known or used by others in the U.S., or was patented
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`or published anywhere, before the applicant's invention. I further have been
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`informed that a claim is invalid under 35 U.S.C. § 102(b) if the invention was
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`
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`patented or published anywhere, or was in public use, on sale, or offered for sale in
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`this country, more than one year prior to the filing date of the patent application
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`(critical date). I further have been informed that a claim is invalid under 35 U.S.C.
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`§ 102(e) if an invention described by that claim was disclosed in a U.S. patent
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`granted on an application for a patent by another that was filed in the U.S. before
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`the date of invention for such a claim.
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`21.
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`I have been informed that a patent claim is invalid as “obvious” under
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`35 U.S.C. § 103 in light of one or more prior art references if it would have been
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`obvious to one of ordinary skill in the art, taking into account (1) the scope and
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`content of the prior art, (2) the differences between the prior art and the claims, (3)
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`the level of ordinary skill in the art, and (4) any so called “secondary
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`considerations” of non-obviousness, which include: (i) “long felt need” for the
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`claimed invention, (ii) commercial success attributable to the claimed invention,
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`(iii) unexpected results of the claimed invention, and (iv) “copying” of the claimed
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`invention by others. For purposes of my analysis, and because I know of no
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`indication from the patent owner or others to the contrary, I have applied a date of
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`February 8, 1991, as the date of invention in my obviousness analyses, although in
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`many cases the same analysis would hold true even at an earlier time than February
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`8, 1991.
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`22.
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`I have been informed that a claim can be obvious in light of a single
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`prior art reference or multiple prior art references. To be obvious in light of a
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`single prior art reference or multiple prior art references, there must be a reason to
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`modify the single prior art reference, or combine two or more references, in order
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`to achieve the claimed invention. This reason may come from a teaching,
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`suggestion, or motivation to combine, or may come from the reference or
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`references themselves, the knowledge or “common sense” of one skilled in the art,
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`or from the nature of the problem to be solved, and may be explicit or implicit
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`from the prior art as a whole. I have been informed that the combination of
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`familiar elements according to known methods is likely to be obvious when it does
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`no more than yield predictable results. I also understand it is improper to rely on
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`hindsight in making the obviousness determination. See KSR Int'l Co. v. Teleflex
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`Inc., 550 U.S. 398, 421 (2007).
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`C.
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`Means Plus Function Terms
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`23.
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`I have been informed that a claim limitation may be written in “means
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`plus function” or “112(6)” format. I have been informed that a claim limitation using
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`the term “means” and including functional language is presumed to invoke 35 U.S.C.
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`§ 112(6). I have been informed that a claim limitation written in the means plus
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`function format is literally met if the element in the prior art corresponding to the
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`means plus function limitation (i) performs the same function recited in the means
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`plus function limitation (ii) using the same structure disclosed in the patent
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`specification for performing the recited function, or its statutory equivalent. A prior
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`art structure is a statutory equivalent to a structure disclosed in the patent
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`specification if it performs exactly the same function, in substantially the same way,
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`to achieve substantially the same result. I understand that a structural equivalent for
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`a means plus function limitation must have been available at the time of the issuance
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`of the claim.
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`V. Background of the Technology
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`24. Computer memories can be classified as volatile and non-volatile.
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`Volatile memories, such as DRAM, SRAM, SDRAM, and DDR-DRAM, only
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`store data while powered by the system they are in, and lose the data stored therein
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`when the power is turned off. Non-volatile memories retain their stored data even
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`without power. Examples of non-volatile memories and memory systems include
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`magnetic tape, magnetic and optical drives, read only memories (ROMs),
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`electrically programmable read only memories (EPROMs), and electrically
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`erasable programmable read-only memories (EEPROMs).
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`25. Flash memory technology can store one bit of data in each transistor
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`cell of the memory, or it can be made to store more than one bit of data in each
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`memory cell. Flash memory that stores one bit per cell is typically called single
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`level cell or SLC memory. Flash memory that stores two bits per cell is typically
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`called MLC, for multi-level cell memory. Flash memories have been developed
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`that store three bits per cell, and even four bits per cell. However, as the number of
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`bits stored in a flash memory cell increases, the programming speed decreases, the
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`reliability and longevity of the memory decreases, and the error rate increases.
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`Some of the earliest MLC flash memory patents and publications include Japanese
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`Patent Application Kokai No. S62-34398 (A) to Kitamura; and U.S. Patent Nos.
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`5,095,344 to Harari and 5,172,338 to Mehrotra, Harari, et al., which were filed in
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`the mid to late 1980s.
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`VI. Brief Summary of the ’571 Patent
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`26. Generally, I understand that the ’571 patent is directed to MLC
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`devices, and more particularly to systems and techniques for reading,
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`programming, and verifying the programming of MLC devices. See Ex. 1001 at
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`Abstract, 7:9-43, 9:60-10:37. More specifically, the ’571 patent is directed to an
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`electrically alterable, non-volatile memory device. See Ex. 1001 at 4:21-23. The
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`’571 patent describes electrically alterable as “electrically varying the conductivity
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`of the channel of a floating gate FET [by applying programming pulses to the cell]
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`to be within any one of Kn conductivity ranges . . . . The conductivity range is then
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`sensed and encoded. This forms the basis of an n-bit EANVM memory cell.” See
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`Ex. 1001 at 4:21-33. As such, an electrically alterable memory cell includes one in
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`which programming the cell, e.g., by applying programming pulses to change the
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`conductivity of the channel of a floating gate, changes its threshold voltage and
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`thus can change its memory state. Non-volatile memory cells are cells that
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`maintain their memory state even after power is removed from the memory device.
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`See Ex. 1001 at 2:21-28.
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`27. To this end, the ’571 patent describes a process for reading the current
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`memory state of a memory cell by comparing the bit line voltage of the memory
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`cell to each of three reference voltages that delineate between the various memory
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`states. See Ex. 1001 at 7:9-8:11. The ’571 patent describes this reading process in
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`the context of a memory cell having four possible memory states, which allows the
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`memory cell to store two bits of information. The four memory states (i.e., (0,0),
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`(1,0), (0,1), and (1,1) in two-bit form) of the memory cell are distinguished by the
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`three reference voltages (Ref 1, Ref 2, and Ref 3), which are shown and described
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`with reference to Figure 7.
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`28. The ’571 patent instructs that the Sense Amplifier 152 and Encode
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`Logic 160, collectively described below and in Figure 8 as the 4-Level
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`Sense/Encode circuit 152, 160 (“Read Circuit”), can determine the memory state of
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`the cell based on the comparison results of the memory cell bit line voltage to each
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`of the reference voltages (Ref1, Ref2, Ref3). See Ex. 1001 at 7:15-43.
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`29. More specifically, the ’571 patent describes that the Read Circuit uses
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`three sense amplifiers to make the necessary three comparisons of the reference
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`voltages to the bit line voltage. The three sense amplifiers 154, 156 and 158 are
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`shown in Figure 6. See id.
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`30. Each sense amplifier compares the bit line voltage of the memory cell
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`from the memory cell’s output terminal 168 to the sense amplifier’s respective
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`reference voltage. See id. For example, sense amplifier 154 compares the bit line
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`voltage to reference voltage Ref 3, sense amplifier 156 compares the bit line
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`voltage to reference voltage Ref 2, and sense amplifier 158 compares the bit line
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`voltage to reference voltage Ref 1. The encode logic 160 uses the
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`outputs/comparison results from the three sense amplifiers to encode the results
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`into two-bit form representing the current memory state of the memory cell, e.g.,
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`based on the encode logic shown at col. 7, lines 30-38 of the ’571 patent.
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`31. Generally, the ’571 patent describes the programming and verification
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`of a memory cell as an iterative process. See id. at 10:14-36. Each iteration of the
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`process includes a programming pulse applied to the memory cell followed by a
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`check to determine if the last programming pulse placed the memory cell into its
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`desired memory state, as further described below. See id. If the check indicates
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`that the memory cell is correctly programmed to its desired memory state then
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`programming ends. See id. However, if the check indicates that the cell is not
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`correctly programmed then additional programming and verification steps are
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`carried out until the cell is determined to be correctly programmed. See id.
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`32. Figure 11 illustrates an example iterative programming and
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`verification process of the ’571 patent.
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`33.
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`In this example, the memory cell is being programmed from an erased
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`(1,1) memory state to a desired (1,0) memory state through a series of
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`programming pulses represented as stair steps up the voltage threshold y-axis. See
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`id. Each stair step corresponds to a programming pulse increasing the voltage of
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`the memory cell (e.g., threshold voltage or bit line voltage, which is representative
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`of the threshold voltage). See id. After each programming pulse (e.g., stair step), a
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`verification process determines if the memory cell is in its desired memory state.
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`If not, programming continues. See id.
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`34. The verification process determines if the memory cell is in its desired
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`memory state by comparing the memory cell’s bit line voltage, which is
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`representative of the cell’s threshold voltage1 and increases after each
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`programming pulse, to a reference voltage representing the desired memory state.
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`See id. Here in Figure 11, the reference voltage for memory state (1,0) is Vref3, as
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`Vref3 is in the voltage window defining state (1,0), i.e., the voltage window
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`defined by Vt2 and Vt3. See id. Each memory state has a different reference
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`voltage particularly representing that memory state. See id. at 8:26-40. For
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`1 A memory cell’s threshold voltage cannot readily be measured directly. There
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`are known (or determinable) relationships between a memory cell’s threshold
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`voltage and the signal on its bit line. The bit line signal is a representation of, but
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`different from, the threshold voltage, and can be used as a proxy for the threshold
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`voltage in determining the current memory state of the cell. This is applicable to
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`the ’571 patent, Kitamura and Mehrotra.
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`example, a reference voltage Vref2 representing memory state (0,1) would be in
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`the voltage window defined by Vt1 and Vt2. See id. Thus if the desired memory
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`state was (0,1), the verification process would compare the memory cell’s bit line
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`voltage to Vref2 to determine if the memory cell has been correctly programmed.
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`35. The ’571 patent further describes the programming and verification
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`process with respect to Figure 8.
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`
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`36. The ’571 patent describes that the verification process can be
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`performed through either analog or digital comparators. In one implementation,
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`the ’571 patent describes that the verification process can be performed with use of
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`the Verify Reference Select device 222 and the Analog Comparator 202. See Ex.
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`1001 at 9:64-65, 8:64-9:18, 11:49-58. In this implementation, the Analog
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`Comparator 202 compares the bit line voltage of the memory cell, representing the
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`current memory state of the cell, with the reference voltage, representing the
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`desired memory state of the cell, to determine when the cell is correctly
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`programmed. See id. The Comparator 202 receives the current memory state of
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`the cell from the output terminal 168 in the form of an analog bit line
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`voltage/signal, and receives the reference voltage corresponding to desired
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`memory state from the Verify Reference Select device 222 in the form of an
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`analog signal. See id.
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`37. The Verify Reference Select device 222 determines which reference
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`voltage to select, e.g., Vref1, Vref2, Vref3 or Vref4, based on the output from the
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`2-Bit Input Latch/Buffer 224. See id. The 2-Bit Input Latch/Buffer 224, in turn,
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`receives the inputs corresponding to the input information/desired memory state
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`from I/O terminals 162 and 164. See id. Thus the Verify Reference Select device
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`222 selects the reference signal, to pass to the Comparator 202, corresponding to
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`the input information/desired memory state. It’s worthy to note that the process of
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`using a digital input to select, and output, an analog voltage is often called digital-
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`to-analog conversion which can be abbreviated as DAC or D/A.
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`38. When the Comparator 202 determines that the bit line voltage of the
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`memory cell exceeds the reference signal corresponding to the desired memory
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`state, the Comparator 202 generates an output signal to disable the Program
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`Voltage Switch 220,2 thereby ending programming. See id. at 9:3-7.
`
`39. As mentioned above, in addition to an analog implementation, the
`
`’571 patent also describes a digital implementation of the Comparator 202. See id.
`
`at 11:49-58; 9:64-65. More particularly, the ’571 patent instructs that in this digital
`
`implementation, the digital comparator uses the digital, encoded data, representing
`
`the current memory state of the memory cell, from the encode circuitry 160. See
`
`id. at 11:49-58. The encode circuitry 160 receives its input from the sense
`
`amplifier 152. See id. The input into the digital comparator for the current
`
`memory state of the memory cell is a digital signal representing the two-bits from
`
`the sense/encode circuitry 152, 160, which is analogous information to the bit line
`
`voltage from output terminal 168 used in the analog comparator implementation.
`
`40. The other input to the digital comparator, representing the desired
`
`memory state and analogous to the selected reference voltage in the analog
`
`implementation, e.g., Vref1, Vref2, Vref3 or Vref4, is an encoded, digital voltage
`
`from the Verify Reference Select device 222. See id. This encoded, digital
`
`voltage is based on the output of the 2-Bit Input Latch/Buffer 224 and represents
`
`
`2 The Program Voltage Switch 220 and the Program/Verify Timing Circuit 208
`
`manage the programming pulses. See id. at 8:50-57.
`
`
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`20
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`the desired memory state/input information. See id. The ’571 patent notes that,
`
`beyond the above changes, the function of the comparator remains the same. See
`
`id.
`
`41. Notably, the ’571 patent describes no other device(s) or process(es)
`
`that manipulate or change the output of the Verify Reference Select device 222
`
`into the digital signal needed by the digital comparator or that otherwise select
`
`which digital signal, corresponding to the input information, to send to the digital
`
`comparator. Thus a POSITA would understand that in this digital comparator
`
`implementation the Verify Reference Select device 222 selects the particular one
`
`digital signal corresponding to the desired memory state to provide to the digital
`
`comparator.
`
`42. The encoded, digital signal from the Verify Reference Select device
`
`222, representing the desired memory state of the cell, could be selected and
`
`provided to the digital comparator in several well-known ways. For example, if
`
`the output of the 2-Bit Input Latch/Buffer 224 received by the Verify Reference
`
`Select device 222 is a (1,0), representing the third of four possible memory states,
`
`and the memory device uses a scheme where a 5 Volt signal corresponds to a “1”
`
`bit and a 0 Volt signal corresponds to a “0” bit, then the Verify Reference Select
`
`
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`21
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`device 222 would select a 5 Volt, 0 Volt reference signal3 to represent the (1,0)
`
`memory state.
`
`43. Conversely, if the output of the 2-Bit Input Latch/Buffer 224 was
`
`(1,1), (0,1) or (0,0) then the Verify Reference Select device 222 would respectively
`
`select a 5 Volt, 5 Volt signal; a 0 Volt, 5 Volt signal; or a 0 Volt, 0 Volt signal to
`
`send to the comparator. Thus the reference signals corresponding to the various
`
`memory states are predetermined, e.g., based on number of desired memory states
`
`and the encoding scheme, and the Verify Reference Select device 222 selects the
`
`one of these reference signals that corresponds to the desired memory state
`
`consistent with the output of the 2-Bit Input Latch/Buffer 224. Unless the memory
`
`device system parameters change, the reference signals will not change. Based on
`
`
`3 Based on the specific design of the circuit, a POSITA at the time of the ’571
`
`patent invention would have understood that the Verify Reference Select device
`
`222 could send the reference signal in serial or parallel manner. For example, for
`
`the 5 Volt, 0 Volt reference signal the Verify Reference Select device 222 could
`
`serially send a 5 Volt waveform followed by a 0 Volt waveform to the comparator
`
`as the digitally encoded (1,0) reference signal. Likewise, the Verify Reference
`
`Select device 222 could send in parallel the reference signal to the comparator via
`
`a 5 Volt waveform on a first data line and a 0 Volt waveform on a second data line.
`
`
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`the above-described disclosure of the ’571 patent, the claims of the ’571 patent,
`
`and for the reasons presented below in Section VII, it is my opinion that a POSITA
`
`would understand that the ’571 patent’s claims cover both digital and analog
`
`implementations as described above.
`
`44. As depicted in Figure 8 above, the 4-Level Sense/Encode circuit 152,
`
`160 and the Verify Reference Select device 222 are shown as separate
`
`components/functions. However, the ’571 patent describes that the 4-Level
`
`Sense/Encode circuit 152, 160 and the Verify Reference Select circuit 222 can be
`
`“coupled together to . . . time share common circuit components.” See id. at 9:19-
`
`24. Such coupling would allow the program/verify process to share components
`
`and function with the read process.
`
`VII. Claim Terms of the ’571 Patent
`
`A. Reference voltage selecting means for selecting one of a plurality
`
`of reference voltages in accordance with said input information
`
`45. Claim 1 recites a “reference voltage selecting means for selecting one
`
`of a plurality of reference voltages in accordance with said input information, each
`
`of said reference voltages corresponding to a different one of said predetermined
`
`memory states.” I understand that a claim limitation using the term “means” and
`
`including functional language is presumed to invoke 35 U.S.C. § 112(6) and be a
`
`means-plus-function limitation. This limitation includes the term “means” and
`
`
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`functional language, e.g., selecting one of a plurality of reference voltages in
`
`accordance with said input information. Therefore I understand that this limitation
`
`is presumed to be a means-plus-function limitation.
`
`46. As such, I understand that the ’571 patent must disclose a structure to
`
`perform the recited function, which, as mentioned above, could be in the context of
`
`either an analog or digital implementation. The ’571 patent describes that the
`
`“voltage threshold of memory cell 102 is then determined by using the comparator
`
`202 to compare the bit line voltage at terminal 168 with the selected verify
`
`reference voltage from the verify reference voltage select circuit 222.” See id. at
`
`8:66-9:3. “The verify reference voltage select circuit 222 analog output voltage X
`
`is determined by decoding the output of the n-bit input latch/buffer 224 (n=2 in the
`
`illustrative form).” See id. at 9:11-14.
`
`47.
`
`“The verify reference voltage select 222 would provide the voltage to
`
`be encoded with the input coming from the output of the n-bit input latch/buffer
`
`224, representing the data to be programmed.” See id. at 11:54-57. “For the write
`
`mode of operation, a verify reference voltage select circuit 222 provides an analog
`
`voltage reference level signal X to one input terminal of an analog comparator
`
`202.” See id. at 8:26-29. Figure 8 also shows the Verify Reference Select circuit
`
`222 provides the reference signal “X” to the Comparator 202. Thus I understand
`
`
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`24
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`that the corresponding structure for this limitation is the Verify Reference Select
`
`circuit 222.
`
`48. Additionally, the ’571 patent describes an analog output as a “signal.”
`
`See Ex. 1001 at 8:26-29 (“verify reference voltage select circuit 222 prov

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