O
`
`UIllted States Patent [19]
`Banks
`
`lllllllllllllllllllllllllll?lllllllllllllllllllllllllllllllll
`
`[11] Patent Number:
`[45] Date of Patent:
`
`5,764,571
`Jun. 9, 1998
`
`[54] ELECTRICALLY ALTERABLE NON-
`XEIIJIATILE MEMORY WITH N-BITS PER
`
`W090/01984 3/1990 WLPO .
`OTHER PUBLICATIONS
`
`_
`[75] Inv?ntor: Gerald J‘ Banks- Fremont Cahf-
`,
`_
`_
`[73] Asslgnee' BTG USA Inc“ Gulph Mlus‘ Pa‘
`
`[211 Appl' NM 410,200
`[22] Filed;
`Feb 27, 1995
`
`Related U.S_ Application Data
`
`[62] Division of Sel". No. 71,816, Jun. 4, 1993, Pat. No. 5,394,
`352, which is a Continuation of 5611 NO- 652,373. Feb- 3,
`1991, Pat. No. 5,218,569.
`[51] lm. cl.6 ................................................... .. G11C 13/00
`[52] us. Cl. .............................. .. 365/l89.01; 365/189.07;
`365/163; 365/201
`[58] Field of Search ....................... .. 365118901. 189.07.
`365/168_ 201
`
`[56]
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`317/235 R
`5/1972 Frohman-Bentchkowsky
`3,660,819
`.. 340/173 R
`4/1974 Keller et al.
`3,801,965
`307/238
`1/1977 Raj et a1.
`4,004,159
`. 340/173 R
`4,054,864 10/1977 Audaire et a1.
`4,090,258
`5/1978 Cricchi .................................. .. 365/184
`-
`-
`(Llst contmued on next page‘)
`FOREIGN PATENT DOCUMENTS
`22:
`Pat. Om _
`
`WO82/02276 7/1982 WIPO .
`
`M. Bauer et al.. A Multilevel-Cell 32Mb Flash Memory.
`1995 IEEE International Solid—State Circuits Conference.
`Session 7. Paper TA7.7.
`John A. Bayliss et al.. The Interface Processor for the 32b
`Computer. 1981 IEEE International Solid-State Circuits
`Conference. Feb. 1931. at 116-117.
`Christoph Bleiker & Hans Melchior. A Four-State
`EEPROM Using Floating-Gate Memory Cells. IEEE Jour
`nal of Solid-State Circuits, vol. SC-22. No. 3. Jun. 1987. at
`260-263.
`Raymond A. Heald & David A. Hodges. Multilevel Ran
`dam-Access Memory Using One Transistor Per Cell. IEEE
`Journal of Solid-State Circuits. vol. SC-ll. N0. 4. Aug.
`1976- 211519428.
`David A- Rich A Survey of Mull/‘valued Memories. [BEE
`Transactions on Computers. vol. C-35. No. 2. Feb. 1986. at
`99-106
`RS. VVlthers et al.. Nonvolatile Analog Memory in MNOS
`Capacitors. IEEE Electron Device Letters. vol. EDL-l. No.
`3. Mar. 1980. at 42-45.
`
`Primary Examiner—Terrell W. Fears
`Attorney’ Agent’ or F” Shame and Shame
`[57]
`ABSTRACT
`
`All electrically alterable. non-volatile multi-bit memory cell
`has K" predetermined memory states (K">2), where K is a
`base of a predetermined number system and n is a number
`of bits stored per cell. Programming of the cell is veri?ed by
`selecting a reference signal corresponding to the information
`221:; asdtolrzcittirzggccsotgnlpazfing a signal of the cell With the
`
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`Mode
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`wme Tm
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`Input/Output 11-bit LalchlBu?er
`
`p115
`
`‘22
`
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`
`-
`
`-
`
`,1,
`
`Page 1 of 24
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`
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`

`5,764,571
`Page 2
`
`US. PATENT DOCUMENTS
`,
`4,122,541 10/1973 Uchlda .................................. .. 365/154
`4,139,910 2/1979
`~-
`44149370 ‘"1979
`4,181,980
`1/1980
`4,192,014
`3/1980
`4,272,830
`6/1981
`4,287,570
`9/1981
`4,300,210 11/1981
`4,306,300 12/1981
`4,327,424 4/1982
`4,357,685 11/1982
`
`4,333,702
`6/1933
`4,415,992 11/1933
`4,449,203
`5/1934
`4,462,033
`7/1934
`4,495,602
`1/1935
`4,503,518
`3/l985
`4558241 12/1985
`4,573,777
`3/1986
`4,586,163 ‘"1986
`446274097 “"1986
`2,22%; 313:;
`447093350 11/1987
`417333394 3,1988
`4,771,404
`9/1988
`4,799,195
`1/1989
`4,809,224 2/1989
`4,847,808
`7/1989
`4,853,892
`8/1989
`4,890,259 1211939
`,
`4,914,631
`4/1990 Johnson et a1.
`4,964,079 10/1990 Devin .................................... .. 365/168
`4,989,179
`1/1991 Simko ..................................... .. 365/45
`5,021,999
`6/1991 Kohda et a1. ......................... .. 365/168
`
`3/1991 Hanm' ................................... .. 365/163
`5,043,940
`3/1992 Harari .................................. .. 357/235
`5,095,344
`5,163,021 11,992 Mehmtm eta,‘
`' 365,185
`5,172,333 12/1992 Mehrotra e131, ..................... .. 365/135
`5,213,569
`6/1993 Banks ............................... .. 365/189.01
`5,258,958 11/1993 lwahashi et a1.
`5,262,984 11/1993 Noguchi et a1. ...................... .. 365/185
`5,268,870 12/1993 Harari ................................... .. 365/218
`5,293,560 3/1994 Harari ........ ..
`. 365/185
`5,295,255
`3/1994 Malecek et a1. .
`. 395/425
`5,321,655
`6/1994 IWahashi et a1.
`365/200
`5,351,210
`9/1994 S3110 .......... ..
`365/189.01
`
`.
`
`. . . .. 365/185
`6/19'95 011g . . . . . . .
`5,422,845
`. 365/163
`7/1995 Parks 6131.
`5,432,735
`.365/135
`7/1995 Harari ..... ..
`5,434,325
`365/45
`3/1995 Fazio et a1.
`5,440,505
`365/189.01
`311995 1330616131 ..
`5,444,656
`365/205
`9/1995 Chlistophemon et
`5,450,363
`365/134
`5,457,650 10/1995 Sugiura et a1. .... ..
`.. 365/185.13
`5,469,334 11/1995 Lacey ............. ..
`371/102
`5,475,693 12/1995 Chlislopherson et a1.
`365/163
`5,435,422
`1/1996 13311616161.
`5,497,119
`3/1996 Tedrowet a1. ........................ .. 327/540
`5,506,313
`4/1996 Mochizuki el al. ............. .. 365/23003
`5,503,953 4/1996 Fazio et a1, ..... ..
`365/135.19
`5,515,317
`5/1996 11761156131,
`......... .. 395/427
`5,523,972
`6/1996 Rashid et a1. .
`.... .. 365/18522
`5,539,690 7/1996 Talreja et a1. .
`.. 365118522
`5,541,886
`7/1996 Hasbun
`365/23001
`5,544,118
`8/1996 Harari
`365/18503
`5,550,772
`8/1996 G111
`...... .. 365/218
`5,568,439 10/1996 Harati
`365/185.33
`5,583,812 12/19'96 Hamri
`365/189.09
`5,594,691
`1/1997 Bashir ..... ..
`5,596,527
`1/1997 Tomioka et a1. ................... .. 36511852
`
`...... .. 365/218
`
`Page 2 of 24
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`

`

`US. Patent
`
`Jun. 9, 1998
`
`Sheet 1 of 14
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`5,764,571
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`US. Patent
`
`Jun. 9, 1998
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`US. Patent
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`Jun. 9, 1998
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`US. Patent
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`PETITIONER'S EXHIBIT 1001
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`Page 7 of 24
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`US. Patent
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`US. Patent
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`US. Patent
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`Jun. 9, 1998
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`

`1
`ELECTRICALLY ALTERABLE NON
`VOLATILE IVIEMORY WITH N-BITS PER
`CELL
`
`5.764571
`
`Cross Reference to Related Applications
`This application is a continuation-in-part of U.S. patent
`application Ser. No. 081071.816. ?led Jun. 4. 1993 entitled
`“Electrically Alterable Non-Volatile Memory with N-Bits
`Per Memory Cell.” now U.S. Pat. No. 5.394.362. which is a
`continuation of U.S. patent application Ser. No. 07/652878.
`?led Feb. 8. 1991 (now U.S. Pat. No. 5.218.569) entitled
`“Electrically Alterable Non-Volatile Memory with N-Bits
`Per Ce .”
`
`10
`
`20
`
`25
`
`35
`
`40
`
`2
`These approaches to a multi-bit ROM commonly have
`one of 2" different conductivity levels of each memory cell
`being determined during the manufacturing process by
`means of a customized mask that is valid for only one data
`pattern. Thus. for storing n different data information
`patterns. a minimum of n diiferent masks need to be pro
`duced and incorporated into a manufacturing process. Each
`time a data information pattern needs to be changed a new
`mask must be created and a new batch of semiconductor
`wafers processed. This dramatically increases the time
`between a data pattern change and the availability of a
`memory product programmed with that new data pattern.
`Prior art electrically alterable multiple-bit per cell
`memory approaches store multiple levels of charge on a
`capacitive storage element. such as is found in a conven
`tional dynamic random access memory (DRAM) or a charge
`coupled device (CCD). Such approaches are described in
`U.S. Pat. No. 4.139.910 by Anantha. U.S. Pat. No. 4.306.300
`by Terrnan. U.S. Pat. No. 4.661.929 by Aoki. U.S. Pat. No.
`4.709.350 by Nakagome. and U.S. Pat. No. 4.771.404 by
`Mano. All of these approaches use volatile storage. that is.
`the charge levels are not permanently stored. They provide
`2" different volatile charge levels on a capacitor to de?ne 2"
`di?‘erent states corresponding to n-bits of data per memory
`cell. All of these approaches have the common characteristic
`that whatever information is stored on such a memory cell
`is volatile because such a cell loses its data whenever power
`is removed. Furthermore. these types of memory cells must
`be periodically refreshed as they have a tendency to lose
`charge over time even when power is maintained.
`It would be advantageous to develop a multi-bit semicon
`ductor memory cell that has the non-volatile characteristic of
`a mask programmable read-only-memory (ROM) and the
`electrically alterable characteristic of a multi-bit per cell
`DRAM. These characteristics combined in a single cell
`would provide a multi-bit per cell electrically alterable
`non-volatile memory (EANV M) capable of storing K" bits
`of data. where “K” is the base of the numbering system
`being used and “n” is the number of bits to be stored in each
`memory cell. Additionally. it would be advantageous if the
`EANVM described above was fully compatible with con
`ventional industry standard device programmers/erasers and
`programming/erasing algorithms such that a user can
`program/erase the multi-bit per cell memory in a manner
`identical to that used for current single-bit per cell memory
`devices.
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`This invention relates to non-volatile memory (NVM)
`devices; and. more particularly. is concerned with an appa
`ratus and method for programming and/or verifying pro
`gramming of a multi-level NVM device with stable refer
`ence voltages.
`2. Description of the Background Art
`In conventional single-bit per cell memory devices. the
`memory cell assumes one of two information storage states.
`either an “on" state or an “off” state. This combination of
`either “on” or “off” de?nes one bit of information. As a
`result. a memory device which can store n-bits of data
`requires 11 separate memory cells.
`Increasing the number of bits which can be stored in a
`single-bit per cell memory device relies upon increasing the
`number of memory cells on a one-for-one basis with the
`number of bits of data to be stored. Methods for increasing
`the number of memory bits in a single memory device have
`relied upon the following advanced manufacturing tech
`niques: manufacture larger die which contain more memory
`cells; or use improved lithography techniques to build
`smaller memory cells and allow more memory cells to be
`placed in a given area on a single chip.
`An alternative approach to the single-bit per cell approach
`involves storing multiple-bits of data in a single memory
`cell. Previous approaches to implementing multiple-bit per
`cell non-volatile memory devices have only involved mask
`programmable read only memories (ROMs). In one of these
`approaches. the channel width and/or length of the memory
`cell is varied such that 2” different conductivity values are
`obtained which correspond to 2" different states correspond
`ing to n-bits of data which can be stored on a single memory
`cell. In another approach. the ion implant for the threshold
`voltage is varied such that the memory cell will have 2"
`different voltage thresholds (Vt) corresponding to 2" dilfer
`ent conductance levels corresponding to 2" different states
`corresponding to n-bits of data which can be stored on a
`single memory cell. Examples of memory devices of these
`types are described in U.S. Pat. No. 4.192.014 by Craycraft.
`U.S. Pat. No. 4.586.163 by Koike. U.S. Pat. No. 4.287.570
`by Stark. U.S. Pat. No. 4.327.424 by Wu. and U.S. Pat. No.
`4.847.808 by Kobatake.
`Single-bit per cell read-only-memory devices are only
`required to sense. or read. two different levels or states per
`cell. consequently they have need for only one voltage
`reference. Sensing schemes for multi-level memory devices
`are more complex and require 2"—1 voltage references.
`Examples of such multiple state sensing schemes for ROMs
`are described in U.S. Pat. No. 4.449.203 by Adlhoch. U.S.
`65
`Pat. No. 4.495.602 by Shepard. U.S. Pat. No. 4.503.578 by
`Iwahashi. and U.S. Pat. No. 4.653.023 by Suzuki.
`
`45
`
`50
`
`55
`
`SUMMARY OF THE INVENTION
`
`The present invention provides a multi-level electrically
`alterable non-volatile memory (EANVM) device. wherein
`some or all of the storage locations have more than two
`distinct states.
`In a speci?c embodiment. the present invention provides
`a multi-level memory device. The present multi-level
`memory device includes a multi-level cell means for storing
`input information for an inde?nite period of time as a
`discrete state of the multi-level cell means. The multi-level
`cell means stores information in K“ memory states. where K
`is a base of a predetemrined number system. n is a number
`of bits stored per cell. and K">2. The present multi-level
`memory device also includes a memory cell programming
`means for programming the multi-level cell means to a state
`corresponding to the input information. A comparator means
`for comparing the memory state of the multi-level cell
`means with the input information is also included. The input
`information corresponds to one of a plurality of reference
`
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`PETITIONER'S EXHIBIT 1001
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`

`

`5.764.571
`
`IO
`
`4
`FIG. 13 is a timing diagram illustrating the voltage
`threshold of a 2-bit per cell EANVM during a program!
`verify cycle using variable width program pulses.
`FIG. 14 is a timing diagram illustrating the bit line voltage
`of a 2-bit per cell EANVM during a program/verify process
`which uses variable Width program pulses.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENT
`
`Reference will now be made in detail to the speci?c
`embodiments of the invention. examples of which are illus
`trated in the accompanying drawings. While the invention
`will be described in conjunction with the speci?c
`embodiments. it will be understood that they are not
`intended to limit the invention to those embodiments. On the
`contrary. the invention is intended to cover various
`alternatives. modi?cations and equivalents. which may be
`included within the spirit and scope of the invention as
`de?ned by the appended claims.
`In general. the invention described here allows n-bits of
`information to be stored on and read from an Electrically
`Alterable Non-Volatile Memory (EANVM). This is accom
`plished by electrically varying the conductivity of the chan
`nel of a ?oating gate FBI‘ to be within any one of K"
`conductivity ranges where “K” represents the base of the
`numbering system being employed (in a binary system. “K"
`equals 2). The conductivity range is then sensed and
`encoded. This forms the basis of an n-bit EANVM memory
`cell. The ?oating gate FET conductivity is electrically
`modi?ed by using external programming hardware and
`algorithms which supply signals and voltages to the
`EANVM memory device.
`These external signals and voltages are then modi?ed
`internal to the device to provide an internally controlled
`program/verify cycle which incrementally stores electrons
`on the ?oating gate until the desired conductivity range is
`achieved. For the purpose of illustration. the n-bit per cell
`descriptions will assume a binary system which stores 2-bits
`per memory cell.
`
`20
`
`25
`
`30
`
`35
`
`3
`voltages. The present comparator means further generates a
`control signal indicative of the memory state as compared to
`the input information.
`An alternative speci?c embodiment also provides a multi
`level memory device. The present multi-level memory
`device includes a multi-level cell means for storing input
`information for an inde?nite period of time as a discrete state
`of the multi-level cell means. The multi-level cell means
`stores information in K" memory states. where K is a base
`of a predetermined number system. 11 is a number of bits
`stored per cell. and K">2. A memory cell programming
`means for programming the multi-level cell means to a state
`corresponding to the input information is also included. The
`present multi-level memory device further includes a com
`parator means for comparing the memory state of the
`multi-level cell means with the input information. The input
`information corresponds to one of a plurality of reference
`voltages. The present comparator means further generates a
`control signal indicative of the memory state as compared to
`the input information. A reference voltage means for de?n
`ing the plurality of reference voltages is also included. The
`present reference voltage means is operably coupled to the
`comparator means.
`BRIEF DESCRIPTION OF THE DRAWINGS
`The accompanying drawings. which are incorporated in
`and form a part of this speci?cation. illustrate embodiments
`of the invention and. together with the description. serve to
`explain the principles of the invention:
`FIG. 1 is a generic schematic representation of a non
`volatile ?oating gate memory cell.
`FIG. 2 is a block diagram of a prior art single-bit memory
`system.
`FIG. 3 is a timing diagram of the voltage threshold of a
`prior art single-bit per cell EANVM system being pro
`grammed from an erased “1” state to a programmed “0".
`FIG. 4 is a timing diagram of the bit line voltage of a prior
`single-bit per cell EANVM during a read operation. It
`illustrates waveform levels for both the programmed and
`erased conditions.
`FIG. 5 is a block diagram of an MXN memory array
`implementing a multi-bit per cell EANVM system.
`FIG. 6 is a block diagram for reading a multi-bit per cell
`EANVM system.
`FIG. 7 shows the bit line voltage during a read cycle as a
`function of time for a 2-bit per cell EANVM which has been
`programmed to one of four possible states. (0. O). (l. O).
`(0.1) and the fully erased condition (1.1). Four separate
`voltage levels are represented on this ?gure. each represent
`ing one of the four possible states. Only one of these would
`be present for any given read operation.
`FIG. 8 is a block diagram of a multi-bit per cell system
`combining program/verify and read circuitry.
`FIG. 9 is a timing diagram for the voltage threshold for a
`2-bit per cell EANVM being programmed from a fully
`erased (1.1) state to one of the other three possible states.
`FIG. 10 is a timing diagram which illustrates the voltage
`threshold of a 2-bit per cell EANVM being erased from a
`fully programmed (0.0) state to one of the other three
`possible states.
`FIG. 11 is a timing diagram illustrating the voltage
`threshold of a 2-bit per cell EANVM during a program/
`verify cycle using ?xed width program pulses.
`FIG. 12 is a timing diagram illustrating the bit line voltage
`of a 2-bit per cell EANVM during a program/verify process
`which uses ?xed width program pulses.
`
`I. PRIOR ART SINGLE-BIT EANVM DEVICES
`
`FIG. 1 is a generic schematic representation of a non
`volatile ?oating gate memory cell 10. It is not intended that
`this schematic drawing is in any way indicative of the device
`structure. It is used to illustrate the fact that this invention
`refers to an FET memory cell which uses an electrically
`isolated. or ?oating. gate 14 to store charged particles for the
`purpose of altering the voltage threshold and hence channel
`conductivity of the FET memory cell 10.
`The FET memory cell 10 includes a control gate 12 which
`is used either to select the memory cell for reading or is used
`to cause electrons to be injected onto the ?oating gate 14
`during the programming process. Floating gate 14 is an
`electrically isolated structure which can inde?nitely store
`electrons. The presence or absence of electrons on ?oating
`gate 14 alters the voltage threshold of the memory cell 10
`and as a result alters the conductivity of its channel region.
`A drain region 16 of the FET is coupled to a source region
`18 by a channel region 19. When the ?oating gate 14 is fully
`erased and the control gate 12 has been selected. the channel
`region 19 is in the fully “011". or high conductivity. state.
`When the ?oating gate 14 is fully programmed the channel
`region 19 is in the fully “o?”. or low conductivity state.
`FIG. 2 is a block diagram of a prior art conventional
`single-bit EANVM memory system 30. The memory system
`
`55
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`PETITIONER'S EXHIBIT 1001
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`

`5 .764.571
`
`6
`shown as a single signal and which are both controlled by
`the PGM/Write signal. The memory cell is being pro
`grammed from the fully erased “1” state to the fully pro
`grammed “0” state. For the duration of the PGM/Write
`pulse. the bit and word line program voltages. which need
`not be the same. are respectively applied to the source
`connected to the bit line 38 and to the control gate 34 of the
`memory cell 32. As electrons are injected onto the ?oating
`gate. the voltage threshold of the memory cell begins to
`increase. Once the voltage threshold has been increased
`beyond a speci?c threshold value as indicated by the dashed
`horizontal line. the memory cell 32 is programmed to a “0”
`state.
`Note that Fowler-Nordheim tunnelling can also be used
`instead of hot electron injection to place electrons on the
`?oating gate. The multi-bit EANVM device described here
`functions with either memory cell programming technique.
`The prior art programming algorithms and circuits for either
`type of programming are designed to program a single-bit
`cell with as much margin as possible in as short a time as
`possible. For a single-bit memory cell. margin is de?ned as
`the additional voltage threshold needed to insure that the
`programmed cell will retain its stored value over time.
`FIG. 4 is a timing diagram showing the bit line voltage at
`terminal 38 as a function of time during a memory read
`operation. In this example. prior to time t1 the bit line is
`charged to the Vpull-np condition. Note that it is also
`possible that the bit line may start at any other voltage level
`prior to time t1. At time t1. the EANVM cell 32 is selected
`and. if the cell 32 is in the erased or tilt state. the cell 32
`provides a low impedance path to ground. As a result. the bit
`line is pulled down to near the ground potential provided at
`terminal 36 in FIG. 2. If the EANVM cell 32 were in the “0”
`or fully programmed state. the bit line voltage would remain
`at the Vpull-up voltage after time t1. The voltage on the
`bit-line terminal 38 and the reference voltage Vref at termi
`nal 43 are compared by the comparator 42. whose bu?’ered
`output drives I/O terminal 50. When Vref is greater than the
`bit line voltage. the output on I/O terminal 50 is a logical
`“1”. When Vref is lower than the bit line voltage. the output
`on I/O terminal 50 is a logical "0”.
`
`25
`
`30
`
`35
`
`5
`30 stores a single bit of information in an EANVM cell 32.
`The cell 32. as described in FIG. 1. is selected for reading
`or writing when a row. or word. select signal is applied to a
`control gate terminal 34. A source terminal 36 for the FBI"
`of the cell 32 is connected to a reference ground potential.
`A drain terminal 38 is connected through a pull-up device 39
`to a voltage Vpull-up at a terminal 40. Terminal 38 serves as
`the output terminal of the cell 32. When the cell 32 stores a
`“1” bit. the channel of the PET is in a low conductivity. or
`high impedance. state so that the voltage at terminal 38 is
`pulled-up to the voltage level Vpull-up on terminal 40.
`When the cell 32 stores a “1” bit. the channel of the FBI‘ is
`in a high conductivity. or low impedance. state so that the
`voltage at terminal 38 is pulled-down by the ground poten
`tial at terminal 36.
`For reading the value of the single-bit stored in the cell 32.
`a sense ampli?er 42 compares the voltage at terminal 38
`with a reference voltage Vref at terminal 43. If a “0” is stored
`on the EANVM cell 32. the cell will be in a low conductivity
`state and as a result the voltage at terminal 38 is above the
`reference voltage at terminal 43. For a “0” stored in the cell
`32. the output terminal 44 of the sense ampli?er 42 will be
`a low voltage which will be transmitted through an output
`butfer 46 to a terminal 48 and then coupled to the I/O
`terminal 50 as a logical “0”. If a “1” is stored on the
`EANVM cell 32. the cell is in a high conductivity state and
`as a result the voltage at terminal 38 is below the reference
`voltage at tenninal 43. The output of the sense ampli?er 42
`will be a high voltage which will be transmitted to the I/O
`terminal 50 as a logical “1”.
`For writing the value of an information bit stored in the
`cell 32. it is assumed that the cell 32 is in the erased. or fully
`“on”. state which corresponds to a logical “1". The U0
`terminal 50 is connected to the input terminal of an input
`latch/bu?‘er S2. The output of the input latch/buffer 52 is
`connected to an enable/disable terminal 54 of a program
`voltage switch 56. The program voltage switch 56 provides
`a bit-line program voltage on a signal line 58 connected to
`terminal 38. Another output from the program voltage
`switch 56 is the word line program voltage on a signal line
`62. which is connected to the control gate 34 of the EANVM
`cell 32. When a logical “0” is present at terminal 54 of the
`program voltage switch 56 from the output of Input Latch!
`Bu?er 52 and when the program voltage switch S6 is
`activated by a program pulse on a signal line 62 from a
`program pulse 66. activated by a PGM/Write signal. the
`program voltage switch 56 provides the Program Voltage
`Vpp from a terminal 68 to the control gate 34 of the
`EANVM cell 32. The program voltage switch 56 also biases
`the drain of the EANVM cell 32 to a voltage. typically
`between 8 to 9 volts. and the gate of the EANVM cell 32 to
`the program voltage Vpp. typically 12 volts. Under these
`conditions. electrons are injected onto the ?oating gate by a
`phenomenon known as hot electron injection. This program
`ming procedure raises the voltage threshold of the EANV M
`cell which increases its source-drain impedance. This con
`tinues until the FET memory cell 32 is effectively turned 011.
`which corresponds to a “0" state. When a “1" is present on
`terminal 54 from the output of the Input Latch/Bu?‘er 52 and
`when the PGMIWrite is enabled. the signal line 58 is driven
`low and programming is inhibited and the “1”. or erased.
`state is maintained
`FIG. 3 is a timing diagram of a prior-art single-bit
`EANVM cell 32. as described in connection with FIG. 2.
`The timing diagram shows the change in voltage threshold
`of the EANVM cell 32. as controlled by the word line and
`bit line programming voltages. which are illustratively
`
`45
`
`50
`
`II. MEMORY ARRAY FOR A MULTI-BIT
`EANVM SYSTEM
`FIG. 5 is a block diagram of a multi-bit per cell EANVM
`system 100 which includes an M><N array of memory cells.
`The cells are typically shown as a ?oating gate FET. or
`EANVM. 102. as described in connection with FIG. 1. The
`array uses similar addressing techniques. external control
`signals. and I/O circuits as are used with currently available
`single bit per cell EANVM devices such as EPROM.
`EEPROM. FLASH. etc. devices. Row Address signals are
`provided at input terminals 103A and Column Address
`signals are provided at input terminals 103B.
`Each of the EANVM cells in a row of cells has its source
`connected to a ground reference potential and its drain
`connected to a column bit line. typically shown as 106. Each
`of the columns is connected to a pull-up device. as indicated
`by the block 105. All of the control gates of a row are
`connected to a row select. or word. line. typically shown as
`104. Rows are selected with a row select circuit 108 and
`columns are selected with a column select circuit 110. Sense
`ampli?ers 112 are provided for each of the selected columns.
`Decode/encode circuits 114 and n-bit input/output latches/
`buffers 116 are also provided. A PGM/Write signal is pro
`vided at an input terminal 118 for activating a mode control
`circuit 120 and a timing circuit 122.
`
`Page 19 of 24
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`PETITIONER'S EXHIBIT 1001
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`

`

`5,764,571
`
`7
`A signi?cant feature of this n-bit per cell system 100 as
`compared to a single-bit per cell implementation is that the
`memory density is increased by a factor of n. where n is the
`number of bits which can be stored on an individual multi
`bit memory cell.
`
`In. BASIC READ MODE OF AN N-BIT
`MEMORY CELL
`FIG. 6 shows a binary system 150 for reading the state of
`an n-bit ?oating gate memory cell 102. as described in
`connection with FIG. 1. according to the invention. where n
`is the number of bits stored in the memory cell. For this
`example. it is set to 2 and one of four states of the memory
`cell must be detected. The four possible states being. (0.0).
`(0.1). (1.0). or (1.1). Detecting which state is programmed
`requires a 3-level sense ampli?er 152. This ampli?er
`includes three sense ampli?ers 154. 156. 158 each of which
`have their negative input terminals connected to the output
`terminal 168 of the memory cell 102. Sense ampli?er 154
`has a reference voltage Ref 3 connected to its positive input
`terminal. Sense ampli?er 156 has a reference voltage Ref 2
`connected to its positive input terminal. Sense ampli?er 158
`has a reference voltage Ref 1 connected to its positive input
`terminal. The voltage references are set such as follows:
`Vpull-up>Ref 3>Ref 2>Ref 1. The respective output signals
`S3. S2. S1 of the three sense ampli?ers drive an encode logic
`circuit 160. which encodes the sensed signals S3. S2. S1 into
`an appropriate 2-bit data format. Bit 0 is provided at an I/O
`terminal 162 and Bit 1 is provided at an I/O terminal 164. A
`truth