United States Patent 1191
`Lee et a1.
`
`USO05319348A
`[11] Patent Number:
`[45] Date of Patent:
`
`5,319,348
`Jun. 7, 1994
`
`[54] CACHE MEMORY SYSTEM, AND
`COMPARATOR AND MOS ANALOG XOR
`AMPLIFIER FOR USE IN THE SYSTEM
`[75] Inventors: Sheau-Jiung Lee; Gene Yang, both of
`Taoyuan, Taiwan
`[73] Assignee: ACER Incorporated, Taipei, Taiwan
`[21] Appl. No.: 23,964
`[22] Filed:
`Feb. 26, 1993
`
`[62]
`
`Related US. Application Data
`Division of Ser. No. $83,228, Sep. 14, 1990, Pat. No.
`5,218,246.
`
`[51] 1111.01; ......................... .. c0513 1/03; G06F 7/02
`[52] US. 01. ............................... .. 340/146.2; 307/362;
`307/471
`[58] Field of Search ................... .. 340/146.2; 307/471,
`307/362, 442, 451
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`3,955,177 5/1976 Miller ............................. .. 340/ 146.2
`4,450,432 5/1984 Schmidtpott et a1.
`.. 340/ 146.2
`4,839,841 6/1989 Hagen et a1. .... ..
`340/ 146.2
`4,961,067 10/1990 Suzuki ............................ .. 340/ 146.2
`Primary Examiner-John Zazworsky
`Attorney, Agent, or Firm-Townsend and Townsend
`Khourie and Crew
`ABSTRACT
`[57]
`This invention relates to the MOS analog multi-bit com
`parator ampli?er for performing the high speed digital
`multi-bit comparator function which is required, for
`example, in Cache Tag Random Access Memory of a
`computer system, and to the MOS analog XOR ampli
`
`?er for performing the digital XOR function. The MOS
`analog comparator provided comprises N number of
`MOS analog XOR means for performing the digital
`XOR function and a MOS analog NOR means for per
`forming the digital NOR function. The analog XOR
`provided comprises a constant current source; a ?rst
`MOS switch having its source terminal connected to
`said constant current source, its gate terminal connected
`to the ?rst input signal of said analog XOR ampli?er; a
`?rst MOS differential pair having two input MOS tran
`sistors, the source terminals of said input MOS transis
`tors being commonly connected to the drain terminal of
`said ?rst MOS switch, one gate terminal of said input
`MOS transistors being connected to the second input
`signal of said analog XOR ampli?er whilst the other
`gate terminal of said input MOS transistors being con
`nected to the complementary signal of second input
`signal to said analog XOR ampli?er; a second MOS
`switch having its source terminal connected to the
`source terminal of said ?rst MOS switch, its gate termi
`nal connected to complementary signal of said ?rst
`input signal of said analog XOR ampli?er; and a second
`MOS differential pair having two input MOS transis
`tors, the source terminals of said input MOS transistors
`being commonly connected to the drain terminal of said
`second MOS switch, one gate terminal of said input
`MOS transistors being connected to the second input
`signal of said analog XOR ampli?er whilst the other
`gate terminal of said input MOS transistors being con_
`nected to the complementary signal of the second input
`signal to said analog XOR ampli?er. The analog XOR
`provided has advantage of high speed, low noise and
`easy implementation.
`
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`1
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`5,319,348
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`CACHE MEMORY SYSTEM, AND COMPARATOR
`AND MOS ANALOG XOR AMPLIFIER FOR USE
`IN THE SYSTEM
`
`10
`
`20
`
`2
`such as sub-micron CMOS technology or bipolar tech
`nology, is usually required. However, those technolo
`gies are very complicated and therefore costly.
`FIG. 2 depicts a conventional multi-bit Tag compari
`son architecture which forms a part of the Cache Tag
`RAM. Data is ?rst read out from the Tag static RAM
`(SRAM) as differential signals and appear on the bit
`lines. Since the differential signals representative of the
`data are of the order of only several hundred millivolts,
`they are ?rst ampli?ed and converted into CMOS level
`signal by the sense ampli?er. The CMOS level data
`output from the sense ampli?er then are compared with
`the CPU address A0, . . . , An-l by a digital comparator
`to determine a HIT or MISS condition. The prior art
`digital comparator (shown within dotted lines in FIG.
`2) consists of N XOR and one NOR gate with N inputs
`for making N bits data comparison, as shown in FIG. 2.
`Every XOR makes XOR comparison of each bit and
`the results are combined at the NOR. These gates are
`switched between the logic level “1” and “0” by turn
`ing the MOSFETs in the XOR- and NOR-gates, either
`NMOS or PMOS, on and off.
`In the physical chip layout, not shown in this applica
`tion, the interconnection line between the XORs and
`the NOR are often very long, thereby causing substan
`tial parasitic line capacitance along the interconnection
`path. In order to drive substantial capacitance between
`0 and 5 volts, the logic gates used need to have more
`driving capability. This requirement makes the logic
`gate capacitance large. Due to the large line capaci
`tance and gate capacitance, it is difficult to achieve high
`speed performance unless an advanced process technol
`ogy is utilized.
`Digital comparators operated by turning the MOS on
`and off at very high speed generate switching noise, in
`addition to the power bouncing problem.
`
`This is a divisional of copending application Ser. No.
`07/583,228 ?led on Sep. 14, ,1990, now US. Pat. No.
`5,218,246.
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`This invention relates in general to a Cache memory
`system for use in computers and more speci?cally re
`lates to :1 M05 analog multi-bit comparator sense ampli
`?er and MOS analog XOR ampli?er for performing the
`comparison and XOR functions normally performed by
`digital circuits in computers and to a Cache memory
`system employing such ampli?ers.
`2. Description of the Prior Art
`In a high speed computer system utilizing high speed
`central processing unit (CPU), such as the i80386 or
`i80486 CPU of Intel Corp., the memory data access is a
`major bottleneck of the throughput of such computer
`system. To eliminate this bottleneck and increase the
`throughput, a small and high-speed Cache memory
`25
`subsystem is added between the CPU and the main
`memory. The Cache memory increases the effective
`speed of the main memory by responding quickly with
`a copy of the most frequently used main memory data.
`When the CPU tries to read data from the main mem
`ory, the high-speed Cache memory will respond ?rst to
`check if it has a copy of the requested data. Otherwise,
`a normal main memory cycle will take place. FIG. 1
`depicts the Cache memory system arrangement of mod
`ern computer system.
`A typical Cache memory subsystem consists of Tag
`Random Access Memory (Tag RAM), Data RAM,
`both being usually in form of high speed Static RAM
`(SRAM) and control logic. The Data RAM stores a
`copy of the most frequently used main memory data.
`The Tag RAM stores addresses of the most frequently
`used main memory having a copy in Data RAM. When
`the CPU sends out the address of main memory it tries
`to access, the Tag RAM makes a comparison between
`the external CPU address and the data stored in the Tag
`45
`RAM to determine it is a HIT or a MISS. If it is a HIT,
`data is accessed from the Cache Data RAM. Otherwise,
`the data is accessed from the main memory. The HIT
`and MISS signals appear at the MATCH outputs of the
`Cache Tag RAMs in FIG. 1. The Memory Read/W rite
`50
`Control Logic then controls the reading and writing of
`data from the Cache Data RAM or the main memory in
`response to the HIT, MISS signals.
`The performance of the Cache memory subsystem is
`largely dependent on how fast the Tag RAM can do the
`Cache Tag comparison or, in other words, the compari
`son between the address provided by the CPU on the
`address lines and the addresses stored in the Cache Tag
`RAMs. Therefore, improving the Tag comparison
`speed in the Tag RAM becomes a very important de
`sign issue in a Cache memory subsystem.
`For detailed treatments on the state of art Cache Tag
`RAM, please refer to “Cache Tag RAM Chips Simplify
`Cache Memory Design,” by David C. Wyland in the
`Application Note AN-07 by Integrated Device Tech
`nology, Inc. of Santa Clara, Calif.
`In order to achieve high performance Tag compari
`son speed, a very advanced manufacturing technology,
`
`35
`
`40
`
`65
`
`SUMMARY OF THE INVENTION
`This invention is based on the observation that by
`using a MOS comparator containing MOS analog XOR
`ampli?ers in the Cache memory, the above-described
`disadvantages are not present. In the preferred embodi
`ment, the comparator is analog and employs a MOS
`analog NOR means. The analog XOR ampli?er prefera
`bly is operated at low gain to reduce switching noise. In
`the preferred embodiment, the difference between the
`two outputs of the XOR ampli?er is less than 2 volts,
`and preferably between 1 to 1.2 volts, so that the ampli
`?er can be operated at higher speed. In the preferred
`embodiment, the analog gates in the XOR ampli?er that
`are controlled by the SRAM outputs are always oper
`ated at saturation instead of being switched on and off.
`This reduces the power bouncing problem and im
`proves the overall circuit stability.
`The Cache system of this invention is for use with a
`computer system having main memory with N-bit ad
`dress lines. The Cache system includes a data random
`access memory (Data RAM) for storing a copy of the
`most frequently used main memory data, and a Tag
`RAM. The Tag RAM includes a static random access
`memory (SRAM) for storing the addresses of fre
`quently used main memory data having a copy in the
`Data RAM. The SRAM has N-bit data output. The Tag
`RAM also includes a MOS analog comparator for com
`paring N-bits data output of SRAM with a N-bit ad
`dress or said N-bits address lines of the computer sys
`tem. The comparator causes the Data RAM to supply
`said copy of main memory data when said N-bits data
`
`9
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`

`
`3
`output of the SRAM are identical to the N-bit address
`on the address lines of the computer system.
`Another aspect of the invention is directed towards a
`Tag RAM memory device for use in the Cache memory
`of a computer system with N-bit address lines. The Tag
`RAM memory device includes a Tag static RAM hav
`ing N-bit data output and a MOS comparator for com
`paring the N-bit data output of said static RAM with a
`N-bit address on said N-bit address lines of the com
`puter system. The comparator comprises MOS analog
`XOR means, each having an input connected to one bit
`of address lines of said computer system and having a
`reference input connected to one bit of said data output
`of said Tag static RAM for XOR comparison with one
`bit of said address lines. The comparator further com
`prises a MOS NOR means having N input gate termi
`nals, each connected to one output of said analog XOR
`means. The NOR means outputs a logic “l” state when
`every bit of the address on the address lines of said
`computer system is identical with a corresponding bit of
`20
`data output of said Tag RAM. The NOR means outputs
`a logic “0” state when at least one bit of the address on
`the address lines of the computer system is not identical
`with a corresponding bit of data output of said Tag
`RAM.
`Another aspect of the invention is directed towards
`the MOS comparator used in the Tag RAM memory
`device and in the Cache system described above. The
`comparator compares ?rst input data with second input
`data, where each bit of the ?rst input data corresponds
`to one bit of the second input data. The comparator
`comprises a plurality of MOS analog XOR means, each
`having three inputs, one connected to one bit of the ?rst
`input data, and the remaining two inputs to two signals
`representing one bit of the second input signal. In the
`preferred embodiment, said two representative signals
`are simply a logic value and its complement. The com
`parator performs XOR comparison between said one bit
`of said ?rst input data and the corresponding bit of said
`second input data.
`40
`The comparator further comprises a MOS NOR
`means having a plurality of input gate terminals, each of
`which is connected to one output of said analog XOR
`means, said analog NOR means outputting a logic “1"
`state when every bit of the ?rst input data is identical
`with the corresponding bit of the second input data and
`outputting a logic “0” state when at least one bit of the
`?rst input data is not identical with its corresponding bit
`of the second input data. In the preferred embodiment,
`the MOS NOR means is analog.
`Another aspect of the invention is directed towards a
`MOS analog XOR ampli?er for comparing one bit of a
`?rst input signal with one bit of a second input signal.
`The ampli?er comprises a constant current source, a
`?rst and a second MOS switch, each having its source
`terminal connected to said constant current source, the
`gate terminals of the two switches connected to said one
`bit of ?rst input signal and its complement respectively,
`and a ?rst and a second MOS differential pair. The ?rst
`differential pair has a ?rst and a second input MOS
`transistors whose source terminals are commonly con
`nected to the drain terminal of the ?rst MOS switch.
`The second MOS differential pair has a third and a
`fourth input MOS transistor whose source terminals are
`commonly connected to the drain terminal of said sec
`ond MOS switch. The drain terminals of the ?rst and
`third input MOS transistors are commonly connected to
`the ?rst output of the analog XOR means and a drain
`
`45
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`50
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`5,319,348
`4
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`terminal of the second and fourth input MOS transistors
`are commonly connected to the second output of the
`analog XOR means.
`Said one bit of said second input signal is represented
`by two different signal values. Each of the two signal
`values is applied to one of the gate terminals of the two
`transistors of each differential pair in order to compare
`the one bit of the ?rst input signal with the one bit of the
`second input signal.
`DESCRIPTION OF THE DRAWINGS
`FIG. 1 is an arrangement of the Cache memory sub
`system in modern computer system.
`FIG. 2 is N-bit-digital comparator in a Tag RAM in
`accordance with the prior art.
`FIG. 3 depicts a static RAM, a N-bit MOS analog
`comparator, and a sense ampli?er in a Tag RAM in
`accordance with the present invention.
`FIG. 4 depicts the MOS analog XOR circuit in accor
`dance with the present invention.
`FIG. 5 depicts the MOS analog NOR circuit em
`ployed in this invention.
`FIG. 6 is a circuit of the sense ampli?er in accordance
`with the prior art.
`FIG. 7 depicts a second embodiment of the MOS
`analog XOR circuit in accordance with the present
`invention.
`FIG. 8 depicts a third embodiment of the MOS ana
`log XOR circuit in accordance with the present inven
`tion.
`FIG. 9 depicts a fourth embodiment of the MOS
`analog XOR circuit in accordance with the present
`invention.
`FIG. 10 is a block diagram of a static RAM and a
`N-bit MOS comparator of a Tag RAM in accordance
`with another embodiment of the present invention. The
`comparator includes N analog XOR gates, N sense
`ampli?ers and a digital NOR gate.
`FIGS. 11-14 depict alternative embodiments of the
`MOS analog XOR circuit in accordance with the pres
`ent invention.
`
`30
`
`35
`
`DESCRIPTION OF THE DETAILED
`EMBODIMENT
`FIG. 3 depicts a static RAM, a N-bit MOS analog
`comparator 1, and a sense ampli?er in a Tag RAM in
`accordance with the present invention. As opposed to
`the prior art, the bit line differential signals B0, .
`.
`. ,
`Bn-l; m, .
`.
`. , m from the static RAM, where n is
`equal to N, are ?rst sent into N analog XOR circuits 11
`to be compared with the corresponding input address
`A0, . . . , An-l from the CPU on the address lines of the
`computer system. The results of the comparison of the
`XOR circuits are combined at the analog NOR circuit
`12. The result thereof is ?nally ampli?ed and converted
`into a CMOS signal by the sense ampli?er 13 determin
`ing a HIT or MISS situation. The analog comparator 1
`has a better transient response than the digital one in
`FIG. 2 because of the reasons which will be described
`in detail in the following related paragraphs.
`FIG. 4 shows the MOS analog XOR circuit 11 ac
`cording to the present invention. The analog XOR
`comprises a current source, two input MOS switches
`M5 and M6, four MOSFETs M1-M4 operated in the
`saturation region and two pullup transistors M7, M8.
`The input CPU address A and its complementary signal
`A are CMOS level signals used to control the ON/ OFF
`of the switch M5 and M6. The signal from the static
`
`65
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`5,319,348
`5
`RAM is a differential signal, represented by two voltage
`signals having several hundreds millivolts difference
`between them, coming from the Tag static RAM bit
`line. This differential signal may be written as B and its
`complementary signal B. It will be understood, how
`ever, that the signal from the static RAM may be single
`ended signal B instead. In such circumstances, the com
`parator circuit should include one or more inverters for
`inverting the signal B so that each bit of the signal B and
`its complement are supplied to the analog XOR circuits
`11.
`Conceptually, MOS M8, M7, M4, M2, M6 and cur
`rent source constitute one differential ampli?er, while
`M8, M7, M3, M1, M5 and current source constitute
`another differential ampli?er. In this con?guration, M7,
`M8 are loads common to the two ampli?ers. The MOS
`FETs M1, M3 form a differential pair and so do M2,
`M4. This special circuit con?guration 11 can perform
`the required XOR function as explained below.
`For example, in a typical modern microcomputer
`system, signal A assumes a logic “0” when it is 0 volt
`and assumes a logic “1” when it is 5 volts, while differ
`ential signal (B, B) assumes a logic “0” when (B,
`B)=(4.7 V, 5 V) and assumes a logic “1” when (B,
`B)=(5 V, 4.7 V).
`When the input A is low at logic “0,” the current
`?ows throug_h differential pairs M1, M3. If input B is
`higher than B, then the current in the right pullup tran
`sistor M7 will be smaller than that in the left pullup
`transistor M8. The voltage Y on the output node 52 is
`going high representing a logic “1.” On the contrary, if
`the input B is lower than B, the output node 52 will be
`at a logic “0.”
`If input A is high at logic “I,” then the current ?ows
`through differential pairs M2, M4. The current in the
`35
`right pullup transistor M7 is smaller than that in t_l_1e left
`pullup transistor M8 if the signal B is lower than B. The
`output Y at 52 is then at “1.” But if the signal B is higher
`than B, the current through M7 is higher than that
`through M8, so that output 52 is at “0.”
`The voltage difference between two output logic
`levels Y, Y at outputs 52, 54 is less than 2 volts and is
`about 1 to 1.2 volts due to the small voltage gain. From
`the foregoing statements, if the inputs A, (B, B) are at
`different logic levels, the output will be “1.” Otherwise,
`the output will be “0.” This is exactly the XOR function
`as required. Hence the analog XOR circuit 11 performs
`the same logic function as the conventional digital XOR
`gate.
`In the digital XOR circuit, the logic function is per
`formed by turning ON/OFF of the MOS. Such circuit
`provides very high gain and therefore, the transient
`characteristics are degraded due to the high output
`impedance. But in the analog XOR 11 shown, gain is
`about two and not large, the output impedance can be
`greatly reduced and the transient characteristics is im
`proved signi?cantly. Therefore, the analog XOR pro
`vided in this invention can be operated at much higher
`speed.
`As indicated above, transistors M1-M4 are operated
`always in saturation. It is known that a MOSFET has a
`lower MOS gate capacitance when it is operated in
`saturation than when it is operated in the linear region.
`Another bene?t of this design is that the input Miller
`capacitance in each input MOS can be reduced below a
`certain level since the input MOS Ml-M4 can never be
`driven into the linear region because of the small volt
`age swing due to the low voltage gain. The input Miller
`
`6
`capacitance seen from the input node can be very small
`and this feature is important since it allows the analog
`XOR 11 to operate at very high speed.
`As described in the above paragraphs, the analog
`XOR 11 has very good transient characteristics due to
`its small output impedance and input Miller capaci
`tance. With such good transient characteristics, the
`voltage difference the XOR circuit 11 needs to drive is
`only 1 to 1.2 volts rather than the 5 volts. So the analog
`XOR 11 has high speed performance.
`The gates Ml-M4 are operated always in saturation
`instead of being turned ON and OFF as in the conven
`tional design so the gates themselves generate very little
`noise. This will reduce the power bouncing problem
`and improve the overall chip stability. Furthermore, the
`analog XOR ampli?er 11 shown consists of symmetrical
`differential pairs and a constant current source I. It can
`be easily fabricated by a low cost PMOS, NMOS or
`CMOS process technology.
`Overall, the analog XOR circuit 11 presented has the
`advantage of high speed, low noise and easy implemen
`tation.
`FIG. 5 shows the MOS analog NOR ampli?er circuit
`12 employed by this invention. The analog NOR circuit
`12 comprises constant current source I, input transistor
`M'O-M'n and the pullup transistor Mr, Ms. The con
`stant current I ?ows through two transistors Mr, Ms.
`There are N input transistors on the lefthand side,
`where n in “M'n” is equal to N. The Y output of com
`parison of each analog XOR 11 shown in FIG. 3 is
`connected to the gate terminal of one of the N input
`transistors M’l-M’n. A reference voltage which_lies
`between the voltage levels of two logic outputs Y, Y of
`the analog XOR gate 11 is applied to the gate of the
`transistor M’O.
`When the N-bit data output Bs of the Tag SRAM is
`not equal to the CPU address As, at least one output of
`the analog XOR 11 will go high, then more current will
`?ow through the lefthand side pullup transistor Ms than
`the right side Mr. Node voltage V+ will be lower than
`V- representing a MISS. On the other hand, when the
`data output Bs of the Tag SRAM is equal to the CPU
`address As, all inputs to NOR 12 will be “0” and lower
`than the reference voltage at M’O. The current ?ows
`through the lefthand side pullup transistor Ms is smaller
`than that through the righthand side pullup transistor
`Mr. The V+ will be higher than V-- representing a
`HIT. The voltage level between two logic levels V+,
`V- is less than 2 V and is preferably about 1.5 V.
`Hence the analog NOR 12 performs the same function
`as a digital NOR gate.
`The analog NOR circuit 12 shown is a low voltage
`gain differential ampli?er having a small output impe
`dance and Miller capacitance. The analog NOR 12 can
`drive the line capacitance between 1.5 volts voltage
`difference at very high speed. The voltage difference
`between V+ and V- is small, so an additional sense
`ampli?er 13 is needed to amplify and convert the signal
`into a CMOS level signal as shown in FIG. 3.
`For more in-depth explanation on the topics of the
`analog NOR 12 used by this invention, please refer to
`the copending US. patent application Ser. No.
`07/318,383 ?led on Mar. 3, 1989.
`Overall, the analog NOR amplifier circuit 12 used in
`the analog comparator 1 has the advantage of high
`speed, low noise and easy implementation.
`Since the MOS analog XORs 11 and the analog NOR
`l2 employed by analog comparator 1 of this invention
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`all have the characteristics of high speed and low noise,
`1. A comparator for comparing a plurality of bits of
`the analog comparator 1 shown in FIG. 3 is suitable for
`?rst input data with a plurality of bits of second input
`high speed operation and can be fabricated by a low
`data, wherein each bit of said ?rst input data is com
`cost MOS process technology.
`pared to a bit of said second input data, said comparator
`comprising:
`FIG. 6 shows a prior art sense ampli?er 13 used in the
`analog comparator l of this invention. It consists of two
`a plurality of XOR means for performing the compar
`stages: the ?rst stage is the level shifter and the second
`ison, each of said XOR means having an input
`one is the high gain differential ampli?er. The level
`connected to one bit of the ?rst input data to be
`shifter shifts the DC voltage level of the analog NOR
`compared and each of said XOR means including a
`differential output V+, V—. The output of the level
`plurality of interconnected transistors in a con
`shifter is then ampli?ed by the differential ampli?er
`stantly on state and having a reference input con
`stage.
`nected to one bit of the second input data for XOR
`Referring to FIGS. 7, 8 and 9, different embodiments
`comparison with one bit of said ?rst input data; and
`of the MOS analog XOR circuit according to this in
`a NOR means having a plurality of input gate termi
`vention have been shown. The required XOR output is
`nals each of which is connected to one output of
`obtained at the common drain terminal of input MOS
`each of said XOR means, said NOR means output
`ting a logic "I" state when every bit of said plural
`transistors M3, M4 in FIGS. 7 and 9 while XOR output
`ity of bits of the ?rst input data is identical with its
`is obtained at the drain terminal of input MOS transis
`compared bit of the second input data and output
`tors M1, M2 in FIG. 8.
`While in FIG. 3, circuit 12 is labeled analog NOR, it
`ting a logic “0” state when at least one bit of the
`?rst input data is not identical with its compared bit
`will be understood that a digital NOR circuit may be
`of the second input data.
`used instead. In such event, the outputs of the analog
`2. A MOS comparator in accordance to claim 1,
`XOR means 11 may need to be ampli?ed by a sense
`ampli?er. In such event, FIG. 3 needs to be modi?ed
`wherein said NOR means comprises a plurality of inter
`slightly by passing the outputs of each of the N analog
`connected transistors in a constantly on state.
`XOR means 11 through N sense ampli?ers 13 before
`3. A comparator in accordance with claim 2, said
`they are applied to circuit 12. The outputs V+ and V
`logic “0", “1” states being at two different voltage lev
`els, said reference voltage being between the two volt
`of NOR circuit 12 will then be at the proper CMOS
`digital levels for processing by a digital NOR gate. In
`.age levels.
`other words, FIG. 3 needs to be modi?ed only by plac
`4. The comparator according to claim 1 wherein said
`ing N sense ampli?ers 13 in between the N analog XOR
`plurality of transistors of each of said XOR means are
`means 11 and the NOR digital circuit 12’. The modi?ed
`interconnected for forming at least one differential am
`con?guration is shown in FIG. 10. Such and other vari
`pli?er having an input connected to said one bit of said
`second input data.
`ations are within the scope of the invention.
`From FIGS. 4 and 7-9, it is evident that the signal B
`5. The comparator according to claim 4 wherein each
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`and its complement may be applied to the four input
`of said XOR means further comprises a transistor con
`nected in series with said differential ampli?er and hav
`MOS transistors Ml-M4 in various combinations, the
`only requirement being that for each of the two pairs,
`ing an input terminal coupled to said one bit of said ?rst
`input data.
`M1, M3 and M2, M4, the signal B is applied to the gate
`terminal of one transistor in each pair and the comple
`6. A MOS comparator for comparing a plurality of
`ment of the signal, F, is applied to the remaining transis
`bits of ?rst input data with a plurality of bits of second
`tor in each pair. From the above discussion, it is clear
`input data, wherein each bit of said ?rst input data cor
`that only one of the differential pairs is supplied with
`responds to a bit of said second input data, said compar
`ator comprising:
`current at any one time, so that the two differential pairs
`essentially operate independently of one another. Also
`a plurality of MOS analog XOR means for perform
`ing the comparison, each of said analog XOR
`as shown in FIGS. 4 and 7-9, transistors M1-M6 are
`N-channeled MOSFETs whereas M7, M8 are P-chan
`means having an input connected to one bit of the
`neled MOSFETs, so that ampli?er 11 is a CMOS analog
`?rst input data to be compared and having a refer
`XOR ampli?er. The ampli?er in FIGS. 4 and 7-9 can be
`ence input connected to one bit of the second input
`modi?ed slightly so that M7, M8 are NMOS transistors
`data for XOR comparison with one bit of said ?rst
`input data; and
`while the transistors Ml-M6 are PMOS transistors. See
`FIGS. 11-14. In such event, FIGS. 4, 7-9 need to be
`a MOS NOR means having a plurality of input gate
`modi?ed slightly so that the current source in such
`terminals each of which is connected to one output
`?gures should be coupled to a Vdd source instead of to
`of each of said analog XOR means, said NOR
`ground while the common source terminal of M7, M8
`means outputting a logic "I" state when every bit
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`of said plurality of bits of the ?rst input data is
`should be grounded or connected to a negative power
`supply instead of to Vdd. The modi?ed circuits again
`identical with its corresponding bit of the second
`form CMOS analog XOR ampli?ers.
`input data and outputting a logic "0” state when at
`In FIG. 5, the load means Mr, Ms are shown as P
`least one bit of the ?rst input data is not identical
`with its corresponding bit of the second input data,
`channel MOSFETs; it will be understood that other
`implementations may be used which are within the
`the MOS NOR means comprising:
`scope of the invention. For example, these MOSFETs
`a constant current source;
`may be simply replaced by resistors.
`a ?rst and a second load means;
`The scope of protection intended in this invention is
`a reference MOS transistor having its source terminal
`set forth in, but not limited to, the following claims.
`connected to said constant current source, its gate
`Any equivalent modi?cation by the persons skillful in
`terminal connected to a substantially constant ref
`this art is deemed to be covered by the attached claims.
`erence voltage and drain terminal connected to the
`What is claimed is:
`?rst load means; and
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`a plurality of input MOS transistors, the source termi
`being commonly connected to the drain terminal of
`nal of each of said input MOS transistors being
`said ?rst MOS switch;
`connected to said constant current source and the
`a second MOS switch having its source terminal
`drain terminal of each of said input MOS transis
`connected to the s