United States Patent [191
`Kokubun
`
`[11] Patent Number:
`[45] Date of Patent:
`
`4,952,821
`Aug. 28, 1990
`
`[54] VOLTAGE DETECTION CIRCUIT AND
`COMPARISON VOLTAGE GENERATOR
`THEREFOR
`[75] Inventor:
`Hitoshi Kokubun, Tokyo, Japan
`[73] Assignee: Oki Electric Industry Co., Ltd.,
`Tokyo, Japan
`[21] Appl. No.: 206,864
`[22] Filed:
`Jun. 13, 1988
`[30]
`Foreign Application Priority Data
`Jun. 12, 1987 [JP]
`Japan .............................. .. 62-14-5186
`
`[51] Int. Cl.5 ........................ .. H03K 5/08; H03K 5/24
`[52] U.S. Cl. .................................. .. 307/350; 307/356;
`307/ 362; 307/ 494
`[58] Field of Search ............. .. 307/264, 362, 356, 490,
`307/491, 494, 497, 350
`References Cited
`U.S. PATENT DOCUMENTS
`
`[56]
`
`4,533,846 8/1985 Simko .
`4,668,932 5/1987 Drori .
`4,721,865 l/1988 Tallaron et a1. .................. .. 307/350
`
`FOREIGN PATENT DOCUMENTS
`
`0117812 6/1985 Japan ................................. .. 307/362
`
`OTHER PUBLICATIONS
`IEEE Journal of Solid-State Circuits, vol. SC-l-S, No.
`5; Oct., 1983, “High-Voltage Regulation and Process
`Considerations for High-Density 5 V~Only E2‘
`PROM’s”; Oto. et al.
`Primary Examiner-John Zazworsky
`Attorney, Agent, or Firm-Wenderoth, Lind & Ponack
`[57]
`ABSTRACT
`In a voltage detection circuit, a comparison voltage
`generator includes reference-setting capacitors, each
`having a ?rst terminal connected to a comparison vo1t~
`age node, and switching circuits provided in association
`with the respective reference-setting capacitors, each
`switching circuit selectively connecting a second termi
`nal of the associated reference setting capacitor either
`to a ?rst potential node or to a second potential node.
`
`21 Claims, 5 Drawing Sheets
`
`(1
`
`WRITING
`VOLTAGE
`GENERATOR
`
`Nso-
`fECSt
`
`5o
`OUT
`
`ZREFERENCE VOLTAGE GENERATOR
`
`MICRON-1005
`
`1
`
`

`
`U.S. Patent Aug-28,1990
`
`Sheet 1 0f 5
`
`4,952,821
`
`F I (5.1
`PRIOR ART
`
`R35’
`,
`
`I
`2
`
`N
`v1
`
`r- —— -— — —— 1 ,2: DIFFERENTIAL
`1
`‘L96
`V92 |I
`AMPLIFIER
`‘
`[/
`CIRCUIT
`l
`I
`l
`I
`I
`IV
`To
`l
`|
`R0 1;
`|—BIT0
`[
`'NBI
`1L
`T1
`I
`l
`R1 5;
`I—BIT1
`I
`T1,
`T3 l
`R2 ‘1
`T2
`;:
`|-—BIT2
`l
`N2
`IF ~5 FF
`I r
`I
`I4
`IVSS '
`I3
`I
`F?"
`l
`l
`1'
`|_________J
`
`R4‘:
`
`N1.
`
`.
`
`I
`
`'
`
`1 REFERENCE
`-! VOLTAGE
`j GENERATOR
`
`I1
`
`o—
`VGEN
`
`I
`OUT
`
`I
`
`-
`
`‘
`
`F l G. 2
`PRIOR ART
`
`VGEN-
`
`o Vcc = 7V
`
`0
`
`x
`
`0
`
`x
`
`A
`
`x VCC = 5V
`
`A Vcc = 4V
`
`o
`
`o
`
`o
`
`x
`
`°
`
`x
`
`x
`
`x
`
`A A
`
`A A
`
`0
`
`x
`
`A
`
`A
`
`REFERENCE VOLTAGE
`SETTING DATA
`
`7
`
`2
`
`

`
`US. Patent
`
`Aug. 28, 1990
`
`Sheet 2 of 5
`
`4,952,821
`
`F I G. 3
`
`WRITING
`VOLTAGE
`GENERATOR
`
`,
`
`51
`
`VGEN(+2OV)
`(250
`N50}:
`C51
`1:
`
`_ 50
`OUT
`
`1
`OoN-IEICMCO
`
`7 TPO
`
`TP1
`
`N11
`
`c2::
`
`TPZ "
`
`FTC-"j
`I NJDITT :
`TD
`
`‘J l
`TN |
`
`A
`
`
`
`0 N20 N1N21 N2 N22 2/ 7 ? _ IOICONSTANT-VOLTAGE
`
`
`
`
`
`
`
`I T 1 W souRcE
`REFERENCE DATA CIRCUIT» RD
`
`IREFERENCE VOLTAGE GENERATOR
`
`3
`
`

`
`US. Patent Aug. 28, 1990
`
`Sheet 3 of5
`
`4,952,821
`
`FIG.4
`
`REFERENCE DATA CIRCUIT
`
`4
`
`

`
`US. Patent Aug. 28, 1990
`
`Sheet 4 of 5
`
`4,952,821
`
`FIG.5
`
`REFERENCE DATA CIRCUIT/RD
`
`FTC-3.6
`
`N11
`
`50
`
`REFERENCE DATA CIRCUIT
`
`5
`
`

`
`US. Patent Aug. 28, 1990
`
`Sheet 5 of 5
`
`4,952,821
`
`O 1
`
`2 3
`
`4 5
`
`6 7 REFERENCE VOLTAGE
`SETTING DATA
`
`Vim
`
`Cso
`
`4 *iwléwi
`lm‘élJ :
`
`|
`
`'
`
`l
`
`IC51
`? 1.0
`
`C0
`41
`
`C1
`
`42
`
`C2
`
`_
`
`OUT
`
`TNo
`r
`
`Tm
`_
`
`TN2
`
`BITZ'
`~BIT1- .
`~BITO
`REFERENCE DATA CIRCUIT
`
`9D
`
`I
`|TD
`
`{M0
`|TN
`
`I
`|
`f‘o
`F
`
`:
`l
`__l
`
`L_ __,
`
`6
`
`

`
`1
`
`4,952,821
`
`VOLTAGE DETECTION CIRCUIT AND
`COMPARISON VOLTAGE GENERATOR
`THEREFOR
`
`2
`a constant level which may exceed the level of the
`supply voltage.
`The resistors R0, R1, and R2, which_are connected in
`series between the output node N1 and the internal node
`N2, provide a means of adjusting the reference voltage.
`The resistance values of the resistors R0, R1, and R2 are
`in the ratio 12:4. NMOS enhancement-type transistors
`T0, T1, and T2 are connected in parallel with the resis
`tors R0, R1, and R2 respectively. The gate terminals of
`the transistors T0, T1, and T2 are connected to input
`signal lines BITO, ITTI, and BIT2. High and low logic
`levels applied to the input signal lines BITO, BIT1, and
`1% switch the transistors T0, T1, and T2 on and off.
`The logic levels on the lines W) to BIT2 represent
`binary-coded data representing the value of the refer
`ence voltage.
`If the on-state resistances of the transistors T0, T1,
`and T2 are negligibly small in comparison to the resis
`tances of the resistors R0, R1, and R2, then the total
`resistance R between the nodes N1 and N2 is the sum of
`the resistances of those resistors R0, R1, and R2 for
`which the corresponding transistor T0, T1, or T2 is
`turned off.
`The node N2, in addition to being connected to the
`gate of the transistor T3, is grounded through a con
`stant-current source I4. Let VNZ be the voltage at node
`N2. Then,
`
`20
`
`25
`
`30
`
`35
`
`BACKGROUND OF THE INVENTION
`This invention relates to a voltage detection circuit
`and an adjustable comparison voltage generator which
`can be used in the voltage detection circuit.
`Certain types of semiconductor integrated circuits
`need to internally generate (i.e., within the circuit) a
`signal voltage which is higher than a power supply
`voltage. Examples of such circuits are electrically eras
`able and programmable read-only memory chips that
`need high programming or writing voltages. Such cir
`cuits require a voltage detection circuit for producing
`an internal reference voltage and for comparing a de
`tected voltage with the reference voltage. The voltage
`detection circuit also includes means for adjusting the
`reference voltage.
`A prior art reference voltage generator is shown in
`FIG. 1, which is extracted from FIG. 10, of “high-Volt
`age Regulation and Process Considerations for high
`Density 5 V-only EZPROM’S,” IEEE Journal ofSolid
`State Circuits, Vol. SC-18, No. 5, October 1983, p. 536.
`The portion enclosed in the chain line is a reference
`voltage generator 1, which provides a reference voltage
`VNl at a node N1. The voltage to be compared with the
`reference voltage V M is labeled VGEN. The comparison
`is performed by a differential ampli?er II, the output
`OUT of which can be used to regulate VGEN. The
`differential ampli?er can be a device with two output
`states that detects when VGEN exceeds the reference
`voltage and furnishes an output signal OUT that is high
`when VGEN is greater than VN1 and low when VGEN is
`less than VN1. The output OUT is connected to a cir
`cuit, not shown in the drawing, that controls VGEN,
`such as a circuit comprising a pumping circuit that
`raises VGEN while OUT is low and a switching circuit
`that suspends the pumping action when OUT becomes
`high.
`The reference voltage generator 1 includes a differen
`tial ampli?er circuit 2 comprising load resistors R3 and
`R4 connected to the supply voltage Vcc, an NMOS
`enhancement-type transistor T3, an NMOS depletion
`45
`type transistor T4, and a constant-current source 13.
`One terminal of the constant-current source 13 is con
`nected to ground; the other terminal is connected via a
`node N5 to the source terminals of the transistors T3
`and T4; the drain terminals of the transistors T3 and T4
`are respectively connected through nodes N3 and N4 to
`the load resistors R3 and R4. The gate terminal of the
`transistor T3 is connected to a node N2. The gate termi
`nal of the transistor T4 is grounded. The gate terminals
`of the transistors T3 and T4 act as the inputs of the
`differential ampli?er circuit 2.
`The differential ampli?er circuit 2 serves as an input
`stage for another differential ampli?er I2, the output of
`which is the reference voltage VNl provided at the node
`N1. The output of the differential ampli?er I2 is also
`connected through a resistor string comprising resistors
`R0, R1, and R2 to the node N2, which is an input node
`of the differential ampli?er circuit 2. Due to this circuit
`topology and to the threshold difference between the
`enhancement-type NMOS transistor T3 and the deple
`tion-type NMOS transistor T4, the differential ampli?er
`circuit 2 and the differential ampli?er I2 form a negative
`feedback loop which holds the reference voltage V M at
`
`Since the differential ampli?er circuit 2 and differential
`ampli?er I2 operate in a linear fashion,'the reference
`voltage VM should in theory be a linear function of the
`digital value applied to BITO, BIT1, and BIT2. Hence
`VGEN should be a linear function of this digital input
`value.
`As FIG. 2 shows, however, VGEN is not in fact a
`linear function of the digital input applied to FIT),
`BIT1, and BIT2. The data in FIG. 2 were derived by
`simulating the operation of the circuit in FIG. 1 on a
`computer and ?nding the value of VGEN that causes the
`output OUT of the differential ampli?er I1 to invert.
`When the output voltage of the voltage detection
`circuit is used as a control signal for a high voltage
`generator, the generated voltage VGEN is dependent on
`the power supply voltage Vcc for the internal circuit.
`The generated voltage may be used for writing in an
`EEPROM. In such a case, when the power supply
`voltage Vcc is lowered, the writing voltage VGEN is
`also lowered. This may cause a failure of the writing.
`Moreover, the linearity of the generated voltage
`VGEN with respect to the reference voltage setting data
`of the prior art circuit is poor, so that it was dif?cult to
`minutely adjust the generated voltage VGEN.
`Furthermore, it is necessary to increase the number of
`bits of the reference voltage setting data .to achieve
`minute adjustment of the generated voltage. However,
`the resistances of the resistors R0, R1 and R2 must be
`larger than the on-state resistances of the transistors T0,
`T1 and T2. It was therefore dif?cult to increase the
`number of the bits of the reference voltage setting data.
`
`SUMMARY OF THE INVENTION
`This invention is directed toward solutions to the
`above problems of nonlinearity, supply-voltage depen
`dence, and ?neness of control.
`
`60
`
`65
`
`7
`
`

`
`5
`
`4,952,821
`3
`According to one aspect of the invention, there is
`provided a voltage detection circuit comprising:
`a detected-voltage node at which a voltage to be
`detected is applied;
`a comparison voltage node;
`a plurality of reference setting means each compris
`ing:
`I
`a reference setting capacitor having a first terminal
`connected to said comparison voltage node and having
`a second terminal; and
`a switching circuit for selectively connecting said
`second terminal of said reference setting capacitor to
`one of either a ?rst potential node and a second poten
`tial node;
`a ?rst voltage detecting capacitor having a ?rst termi
`nal connected to the comparison voltage node and a
`second terminal connected to the detected voltage
`node, and a second voltage detecting capacitor having a
`?rst terminal connected to the comparison node and a
`second terminal connected to a third potential node;
`and
`a voltage comparison circuit for comparing a voltage
`on the comparison voltage node with a voltage on a
`fourth potential node to produce an output signal indi
`cating the result of the comparison.
`According to another aspect of the invention, there is
`provided a comparison voltage generator comprising:
`a comparison voltage node;
`a plurality of reference setting means each having:
`a reference setting capacitor having a ?rst terminal
`connected to said comparison voltage node and having
`a second terminal, and
`’
`a switching circuit for selectively connecting said
`second terminal of said reference setting capacitor to
`one of either a ?rst potential node and a second poten
`tial node;
`a voltage detecting means for detecting a voltage to
`be detected and producing a voltage signal indicative of
`40
`the voltage to be detected; and
`a voltage comparison circuit comparing the voltage
`signal from said voltage detecting means with a voltage
`on said comparison voltage node.
`
`4
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`The preferred embodiments of the present invention
`are described below with reference to the drawings.
`FIG. 3 is a schematic diagram of a ?rst embodiment
`of a voltage detection circuit in accordance with the
`present invention.
`The part enclosed in the dashed line is a well-known
`constant-voltage source 10 comprising an NMOS en
`hancement-type transistor TN and an NMOS depletion
`type transistor TD. The drain of the transistor TD is
`connected to the power supply voltage VCC. The
`source of the transistor TN is connected to the ground.
`The source and the gate of the transistor TD and the
`drain and the gate of the transistor TN are connected
`together. This constant-voltage source 10 produces a
`constant voltage at a node N10 even if the power supply
`voltage Vcc (+5 V) fluctuates.
`The part enclosed in the chain line is a comparison
`voltage generator 5 which in this embodiment is a refer
`ence voltage generator comprising a capacitive voltage
`divider. More speci?cally, the node N10 is connected to
`the source terminals of PMOS enhancement-type tran
`sistors TPO, TP1, and TF2. The drain terminals of the
`transistors TPO, TP1, and TP2 are connected at nodes
`N20, N21, and N22 to the drain terminals of NMOS
`enhancement-type transistors TNO, TN 1, and TN2. The
`source terminals of the transistors TNO, TNl, and TN2
`are grounded. The gate terminals of the transistors TPO
`and TNO are connected in common to the signal line
`BITO; the gate terminals of the transistors TPI and TN 1
`are connected in common to the signal line BIT]; and
`the gate terminals of the transistors TP2 and TN2 are
`connected in common to the signal line 1T2. These
`signal lines BITO to BIT2 are supplied from a reference
`data circuit RD and are bits of a binary-coded reference
`setting signal representing the reference voltage. The
`nodes N20, N21 and N22 are coupled through capaci
`tors C0, C1, and C2, respectively, to a node N11. The
`capacitance
`ratios
`of
`the
`capacitors
`are
`CU:C1:C2= 1:214.
`The illustrated circuit further comprises an NMOS
`enhancement—type transistor TN3, the drain of which is
`connected to the node N11 and the source of which is
`connected to ground and the gate of which is connected
`to an input terminal for a signal denoted W. The signal
`W is low when the reference voltage generator is
`operating, and high when it is not operating. When the
`reference voltage generator is not operating, the node
`N11 is tied through the transistor TN3 to ground level.
`When the reference voltage generator is operating, the
`node N11 is disconnected from ground and held at the
`desired reference voltage level VN11.
`The above-described reference voltage generator
`operates as follows. The node N10 is the output of the
`constant-voltage source 10, so it maintains a constant
`voltage VNlo. If BITO is high, then the transistor TPO is
`off and the transistor TNO is on, so the node N20 is
`connected to ground. If BITO is low, then the transistor
`TPO is on and the transistor TNO is off, so the node N20
`is connected to the node N10 and has the same voltage
`level VNw. The nodes N21 and N22 are controlled in a
`similar way by the inputs at T1 and BIT2, respec
`tively. The inputs at BITO, BITl, and BI_T2 thus serve
`to place each of the nodes N20, N21, and N22 at either
`the ground level or the VNm level. The voltage level at
`the node N11 can be switched among eight levels ac
`
`25
`
`in O
`
`45
`
`55
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`In the accompanying drawings:
`FIG. 1 is a schematic diagram of a prior art voltage
`detection circuit including a reference voltage genera
`tor.
`FIG. 2 is a plot of a computer simulation of the per
`formance of the circuit in FIG. 1.
`FIG. 3 is a schematic diagram of a ?rst embodiment
`of a voltage detection circuit in accordance with the
`present invention.
`FIG. 4 is a schematic diagram of a second embodi
`ment of a voltage detection circuit in accordance with
`the present invention.
`FIG. 5 is a schematic diagram of a third embodiment
`of a voltage detection circuit in accordance with the
`present invention.
`FIG. 6 is a schematic diagram of a fourth embodi
`ment of a voltage detection circuit in accordance with
`the present invention.
`FIG. 7 is a plot of a computer simulation of the per
`formance of the circuit in FIG. 6.
`FIG. 8 is a schematic diagram of a modi?cation of the
`fourth embodiment.
`
`8
`
`

`
`4,952,821
`5
`cording to the inputs at BITO, BITl, and BIT2. The
`voltage V1v11 at the node N11 can then be expressed as
`follows:
`
`Here a0, a1, and a; are dimensionless binary variables.
`When, BITO is high or low, the corresponding variable
`(10 is O or 1, respectively. Similarly, when BITl is high
`or low, the corresponding variable a; is 0 or 1. Simi
`larly, when BIT2 is high or low, the corresponding
`variable a; is O or 1. Since C1=2 C0 and C2=4.C0, this
`reduces to:
`
`15
`
`The above equation shows that the voltage VN11 at the
`node N11 does not follow the voltage variation of the
`power supply voltage Vcc. Hence the the reference
`voltage VN11 is a linear function of the binary digital
`value applied to BITO, BITl, and BIT2.
`The node N11 is connected to the negative input (—)
`of a differential ampli?er 50. The positive input (+) is
`connected to a node N50, which is coupled through a
`capacitor CS0 to ‘a generated voltage VGEN to be con
`25
`trolled, which may be a written voltage of about 20 V
`used for writing data in an EEPROM. The node N50 is
`also coupled through another capacitor CS1 to ground.
`The capacitors C50 and C51 form a capacitive voltage
`divider, the capacitive voltage divider produces a di
`vided (detected) voltage near the reference voltage
`V1v11, so the VN5Q voltage at the node N50 is a ?xed
`fraction of VGEN:
`
`35
`
`6
`connected to the drain terminals of the transistors TPO
`to TP2.
`Applied to the gate terminals of the transistors TPO to
`TP2 and TNO to TN2 are BITO to BIT2 rather than the
`inverted 1W) to I3TT2. In the circuit con?guration in
`FIG. 5, the constant voltage VNlz at the node N12 is
`applied to the voltage comparison circuit as the refer
`ence voltage. The voltage compared with VNIZ is deter
`mined from VGENand VNlg as well as BITO to BIT2 by
`a capacitive voltage divider involving the capacitors
`C50, C51, C0, C1, and C2. The inputs at BITO, BITl,
`and BIT2 adjust the voltage division ratio by switching
`the voltages provided to the capacitors C0, C1, and C2
`between V1v12 and ground. The switching circuit com
`prising the transistors TPO to TP2 and TNO to TN2 is
`identical to that shown in FIG. 3.
`An advantage of adjusting the division ratio applied
`to VGEN to produce a reference voltage and comparing
`it with a constant voltage is that the differential ampli
`?er 50 always operates at the same gain, regardless of
`the inputs at BITO, BITl, and BIT2, i.e., the value of the
`binary-coded reference-setting signal.
`FIG. 6 shows a fourth embodiment of a voltage de
`tection circuit according to the present invention. This
`embodiment is generally identical to the embodiment of
`FIG. 5. But the switching circuit is identical to that of
`FIG. 4, rather than that of FIG. 3 which is incorporated
`in the embodiment of FIG. 5. This embodiment there
`fore has the additional advange of the embodiment of
`FIG. 4.
`FIG. 7 shows the results of computer simulation of
`the operation of the circuit in FIG. 6, in which the value
`of VGEN is plotted as a function of the reference voltage
`represented by the binary-coded reference-setting data
`at BITO, BITl, and BIT2. It can be seen that the behav
`ior of this circuit is highly linear, and substantially inde
`pendent of the supply voltage.
`FIG. 8 shows a modi?cation of the embodiment of
`FIG. 6. In this embodiment, the negative input (—) of
`the differential ampli?er 50 is connected to a separate
`constant voltage source 10’ similar to the constant volt
`age source 10. It is also possible to use a voltage source
`with an adjustable voltage in place of the constant volt
`age source 10'.“
`The modi?cation shown in FIG. 8 can also be applied
`to the embodiment of FIG. 5.
`A voltage detection circuit and the reference voltage V
`circuit according to the invention permit ?ne adjust
`ment with good linearity, and the circuit operation can
`be made substantially independent of the supply volt
`age.
`An additional advantage of this invention is that it
`permits more input signal lines to be added without
`restrictions imposed by the on-state resistances of the
`transistors controlled by the signal lines. Thus ?ner
`adjustment can be achieved by adding further bits of the
`reference setting data.
`What is claimed is:
`1. A voltage detection circuit comprising:
`a detected-voltage node at which a voltage to be
`detected is applied;
`a comparison voltage node;
`a plurality of reference setting means each compris
`ing:
`a reference setting capacitor having a ?rst terminal
`connected to said comparison voltage node and
`having a second terminal; and
`
`The differential ampli?er 50 compares a detected
`voltage V1v50 with the reference voltage VN11. That is,
`the ampli?er 50 detects a detected voltage V N50 exceed
`ing the reference voltage. The ampli?er 50 thereby
`generates an output signal OUT which is used to con
`trol a writing voltage generator 6, which may comprise
`a pumping circuit to produce the writing voltage VGEN.
`FIG. 4 is a schematic diagram illustrating a second
`embodiment of this invention. Circuit elements that are
`identical to elements of the ?rst embodiment are indi
`cated with the same reference numerals, and detailed
`descriptions of them are omitted.
`The difference between this embodiment and the first
`embodiment is that this embodiment uses NMOS tran
`sistors TNO’, TNl’, and TN2’ in place of the PMOS
`transistors TPO, TF1, and TP2. The gates of the transis
`tors TNO’, TNl', and TN2’ are connected to inverters
`40, 41, and 42 which invert the signals BITO, BITl, and
`Fl?. The result is that this embodiment operates in the
`same way as the ?rst embodiment. An advantage of this
`embodiment over the ?rst embodiment is that a high
`input at BITO, BITl, or BIT2 is assured of turning off
`the transistor TNO’, TNl’, or TN2’, when the potential
`difference across the transistor TNO’, TNl' or TN2’ is
`small, close to the threshold level of the transistor.
`FIG. 5 shows a third embodiment of a voltage detec
`tion circuit according to ‘the present invention. In this
`circuit the node N50 is connected to the node N11,
`which is connected to the positive input (+) of the
`differential ampli?er 50. The negative input (—-) of the
`differential ampli?er 50 is connected via a node N12 to
`the constant-voltage source 10. The node N12 is also
`
`40
`
`45
`
`65
`
`9
`
`

`
`4,952,821
`7
`8
`a switching circuit for selectively connecting said
`a reference setting capacitor having a ?rst terminal
`second terminal of said reference setting capacitor
`connected to said comparison voltage node and
`to one of either a ?rst potential node and a second
`having a second terminal, and
`potential node;
`a switching circuit for selectively connecting said
`third and fourth potential nodes;
`second terminal of said reference setting capacitor
`a ?rst voltage detecting capacitor having a ?rst termi
`to one of either a ?rst potential node and a second
`potential node;
`nal connected to said comparison voltage node and
`a second terminal connected to said detected volt
`a voltage-detecting means for detecting a voltage to
`age node, and a second voltage detecting capacitor
`be detected and for producing a voltage signal
`having a ?rst terminal connected to said compari
`indicative of the voltage to be detected; and
`a voltage comparison circuit for comparing the volt
`son voltage node and a second terminal connected
`to said third potential node; and
`age signal from said voltage-detecting means with
`a voltage comparison circuit for comparing a voltage
`a voltage on said comparison voltage node.
`on said comparison voltage node with a voltage on
`13. A circuit according to claim 12, wherein said
`said fourth potential node to produce an output
`second potential node is arranged so as to have a ?xed
`potential.
`signal indicating the result of said comparison.
`2. A circuit according to claim 1, wherein said second
`14. A circuit according to claim 12, further compris
`potential node and said third potential node are ar
`ing a constant voltage source for producing a constant
`voltage, wherein said ?rst potential node is connected
`ranged so as to have the same potential.
`3. A circuit according to claim 2, wherein said second
`to said constant voltage source.
`potential node and said third potential node are ar
`15. A circuit according to claim 12, wherein said
`switching circuit of each of said reference setting means
`ranged so as to have a fixed potential.
`4. A circuit according to claim 1, wherein said ?rst
`comprises a first switching element for connecting,
`potential node and said fourth potential node are ar_
`when conductive, said second terminal of said refer
`ranged so as to have the same potential.
`ence-setting capacitor to said first potential node and a
`5. A circuit according to claim 4, further comprising
`second switching element for connecting, when con
`ductive, said second terminal of said reference-setting
`a constant voltage source for producing a constant
`voltage, wherein said ?rst potential node and said
`capacitor to said second potential node; and said ?rst
`and second switching elements arranged such that
`fourth potential node are connected to said constant
`when one of them is conductive the other is not conduc
`voltage source.
`.
`6. A circuit according to claim 1, wherein said
`tive.
`switching circuit of each of said reference setting means
`16. A circuit according to claim 15, wherein said
`comprises a first switching element connecting, when
`second switching element comprises an NMOS PET
`conductive, said second terminal of said reference-set
`having a gate and receiving at its gate a two-state signal,
`ting capacitor to said ?rst potential node and a second
`and said ?rst switching element comprises an NMOS
`switching element connecting, when conductive, said
`FET having a gate and receiving said two-state signal
`second terminal of said reference-setting capacitor to
`through an inverter.
`said second potential node; and wherein said ?rst and
`17. A circuit according to claim 15, wherein said
`second switching elements are arranged such that when
`second switching element comprises an NMOS FET
`one of them is conductive the other is not conductive.
`having a gate and receiving at its gate a two-state signal,
`7. A circuit according to claim 6, wherein said second
`and said ?rst switching element comprises a PMOS
`switching element comprises an NMOS FET having a
`FET having a gate receiving at its gate said two-state
`signal.
`gate and receiving at its gate a two-state signal, and
`wherein said ?rst switching element comprises an
`18. A circuit according to claim 12, wherein said
`NMOS FET having a gate and receiving said two-state
`switching circuits of said reference setting means are
`signal through an inverter.
`controlled by respective bits of a binary-coded refer
`8. A circuit according to claim 6, wherein said second
`ence setting signal, and the capacitance values of refer
`switching element comprises an NMOS FET having a
`ence-setting capacitors of said reference setting means
`gate and receiving at its gate a two-state signal, and said
`are in the ratio of consecutive integer powers of two.
`?rst switching element comprises a PMOS FET having
`19. A circuit according to claim 12, further compris
`a gate and receive at its gate said two-state signal.
`ing a reference-setting circuit which provides a binary
`coded reference-setting signal indicating the value of
`9. A circuit according to claim 1, wherein said
`switching of said reference setting means are controlled
`the reference voltage, wherein said switching circuits of
`by respective bits of a binary-coded reference setting
`said reference setting means are controlled in accor
`signal, and the capacitance values of said reference-set
`dance with the respective bits of said binary-coded
`reference-setting signal.
`ting capacitors are in the ratio of consecutive integer
`20. A reference voltage generator according to claim
`powers of two.
`10. A circuit according to claim 1, further comprising
`12, further comprising an additional switching means
`a reference-setting circuit which provides a binary
`connected between said comparison node and a ?xed
`potential node.
`coded reference-setting signal indicating a value of a
`reference voltage, wherein said switching circuits of
`21. A reference voltage generator according to claim
`20, wherein said additional switching means comprises
`said reference setting means are controlled in accor
`dance with the respective bits of said binary-coded
`an NMOS transistor having a drain which is connected
`reference-setting signal.
`to said comparison node, and having a source which is
`11. A circuit according to claim 1, wherein said volt
`connected to a ground, and having a gate which is
`age comparison circuit comprises a differential ampli
`connected to an input signal line for applying a signal
`?er.
`that is high when said reference voltage generator is
`12. A voltage detection circuit comprising:
`operating, and low when said reference voltage genera
`a comparison voltage node;
`tor is not operating.
`a plurality of reference setting means each having:
`*
`
`45
`
`*
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`*
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`*
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`35
`
`40
`
`55
`
`65
`
`10