United States Patent [19)
`Mehrotra et al.
`
`111111111111111111111111111111111111111111111111111111111111111111111111III
`US005172338A
`5,172,338
`(11) Patent Number:
`[45] Date of Patent: Dec. 15, 1992
`
`[75]
`
`[54) MULTI·STATE EEPROM READ AND WRITE
`CIRCUITS AND TECHNIQUES
`Inventors: Sanjay Mehrotra, Milpitas; Eliyahou
`Harari, Los Gatos; Winston Lee, San
`Francisco, all of Calif.
`[73] Assignee: Sun disk Corporation, Santa Clara,
`Calif.
`(21) Appl. No.: 508,273
`(22) Filed:
`Apr. 11, 1990
`
`[51]
`
`Related U.S. Application Data
`[63] Continuation-in·part of Ser. No. 337,579, Apr. 13,
`1989.
`Int. CI.s ....................... GllC 7/00; GllC 29/00;
`GIIC 16/04
`[52] U.S. CI ..................................... 365/185; 365/201;
`365/184; 365/195; 365/189.07
`[58) Field of Search ........... 365/168, 184, 185, 189.ot,
`365/189.07, 189.09, 201, 228, 104, 195;
`371/21.4
`
`[56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`4.253.059 2/1981 Bell et at. ........................... 371/21.4
`4.460.982 7/1984 Gee et at. ....................... 371121.4 X
`4,612,629 9/1986 Harari ................................. 365/185
`4.733,394 3/1988 Giebel ............................. 3651201 X
`4.752.929 6/1988 Kantz et at. .......................... 371/21
`4.779,272 10/1988 Kohda et at. ................... 3651201 X
`1/1989 Iwahashi et at. .................... 365/185
`4,799,195
`
`4,809,231 2/1989 Shannon et at. .................... 365/201
`Iwashita .............................. 365/201
`4,870,618 9/1989
`Primary Examiner-Alyssa H. Bowler
`Attorney, Agent. or Firm-Majestic, Parsons, Siebert &
`Hsue
`ABSTRACT
`[57)
`Improvements in the circuits and techniques for read,
`write and erase of EEprom memory enable non-volatile
`multi-state memory to operate with enhanced perfor(cid:173)
`mance over an extended period oftime. In the improved
`circuits for normal read, and read between write or
`erase for verification, the reading is made relative to a
`set of threshold levels as provided by a corresponding
`set of reference cells which closely track and make
`adjustment for the variations presented by the memory
`cells. In one embodiment, each Flash sector of memory
`cells has its own reference cells for reading the cells in
`the sector, and a set of reference cells also exists for the
`whole memory chip acting as a master reference. In
`another embodiment, the reading is made relative to a
`set of threshold levels simultaneously by means of a
`one-to-many current mirror circuit. In improved write
`or erase circuits, verification of the written or erased
`data is done in parallel on a group of memory cells at a
`time and a circuit selectively inhibits further write or
`erase to those cells which have been correctly verified.
`Other improvements includes programming the ground
`state after erase, independent and variable power supply
`for the control gate of EEprom memory cells.
`
`47 Claims, 21 Drawing Sbeets
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`u.s. Patent
`
`Dec. 15, 1992
`
`Sheet 1 of 21
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`5,172,338
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`Dec. 15, 1992
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`Sheet 2 of 21
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`u.s. Patent
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`Dec. 15, 1992
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`Sheet 3 of 21
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`u.s. Patent
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`Dec. 15, 1992
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`Sheet 4 of 21
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`Dec. 15, 1992
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`Dec. 15, 1992
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`u.s. Patent
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`Dec. 15, 1992
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`Sheet 7 of 21
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`u.s. Patent
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`Dec. 15, 1992
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`Sheet 8 of 21
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`u.s. Patent
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`Dec. 15, 1992
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`Sheet 9 of 21
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`
`u.s. Patent
`
`Dec. 15, 1992
`
`Sheet 10 of 21
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`5,172,338
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`u.s. Patent
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`Dec. 15, 1992
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`Sheet 11 of 21
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`u.s. Patent
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`Dec. 15, 1992
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`Sheet 12 of 21
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`
`u.s. Patent
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`Dec. 15, 1992
`
`Sheet 13 of 21
`
`5,172,338
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`APPLY A fUL'E. OF EKA~t VOLTA6E.
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`14
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`
`u.s. Patent
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`Dec. 15, 1992
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`Sheet 14 of 21
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`5,172,338
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`
`u.s. Patent
`
`Dec. 15, 1992
`
`Sheet 15 of 21
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`5,172,338
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`u.s. Patent
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`Dec. 15, 1992
`
`Sheet 16 of 21
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`5,172,338
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`17
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`

`
`u.s. Patent
`
`Dec. 15, 1992
`
`Sheet 17 of 21
`
`5,172,338
`
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`18
`
`

`
`u.s. Patent
`
`Dec. 15, 1992
`
`Sheet 18 of 21
`
`5,172,338
`
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`19
`
`

`
`u.s. Patent
`
`Dec. 15, 1992
`
`Sheet 19 of 21
`
`5,172,338
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`

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`u.s. Patent
`
`Dec. 15, 1992
`
`Sheet 20 of 21
`
`5,172,338
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`

`
`u.s. Patent
`
`Dec. 15, 1992
`
`Sheet 21 of 21
`
`5,172,338
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`
`

`
`1
`
`5,172,338
`
`MULTI·STATE EEPROM READ AND WRITE
`CIRCUITS AND TECHNIQUES
`
`2
`In the usual two-state EEprom cell, one breakpoint
`threshold level is established so as to partition the
`threshold window into two regions. The source/drain
`current is compared with the breakpoint threshold level
`5 that was used when the cell was programmed. If the
`current read is higher than that of the threshold, the cell
`is determined to be in a "zero" state, while if the current
`is less than that of the threshold, the cell is determined
`to be in the other state. Thus, such a two-state cell stores
`one bit of digital information. A current source which
`may be externally programmable is often provided as
`part of a memory system to generate the breakpoint
`threshold current.
`Thus, for a multi-state EEprom memory cell, each
`cell stores two or more bits of data. The information
`that a given EEprom array can store is thus increased
`by the multiple of number of states that each cell can
`store.
`Accordingly, it is a primary object of the present
`invention to provide a system of EEprom memory cells
`wherein the cells are utilized to store more than one bit
`of data.
`It is a further object of the present invention to pro(cid:173)
`vide improved read circuits as part of an Eprom or
`EEprom integrated circuit memory chip.
`It is also an object of the invention to provide read
`circuits which are simpler, easier to manufacture and
`have improved accuracy and reliability over an ex-
`tended period of use.
`I! is also an object of the present invention to provide
`improved program circuits as part of an Eprom or EE(cid:173)
`prom integrated circuit memory chip.
`It is also an object of the invention to provide pro(cid:173)
`gram circuits which are simpler, easier to manufacture
`and have improved accuracy and reliability over an
`extended period of use.
`It is another object of the present inv~ntion to pro(cid:173)
`vide memory read and program techniques that auto(cid:173)
`matically compensate for effects of temperature, volt(cid:173)
`age and process variations, and charge retention.
`It is yet another object of the present invention to
`provide Flash EEprom semiconductor chips that can
`replace magnetic disk storage devices in computer sys-
`tems.
`Further, it is an object of the present invention to
`provide a Flash EEprom structure capable of an in(cid:173)
`creased lifetime as measured by the number of pro(cid:173)
`gram/read cycles that the memory can endure.
`
`30
`
`BACKGROUND OF THE INVENTION
`This application is a continuation-in-part of applica(cid:173)
`tion Ser. No. 337,579 filed Apr. 13, 1989.
`This invention relates generally to semiconductor
`electrically erasable programmable read only memories \0
`(EEprom), and specifically to circuits and techniques
`for reading and programming their state.
`EEprom and electrically programmable read only
`memory (Eprom) are typically used in digital circuits
`for non-volatile storage of data or program. They can 15
`be erased and have new data written or "programmed"
`into their memory cells.
`An Eprom utilizes a floating (unconnected) conduc(cid:173)
`tive gate, in a field effect transistor structure, positioned
`over but insulated from a channel region in a semicon- 20
`ductor substrate, between source and drain regions. A
`control gate is then provided over the floating gate, but
`also insulated therefrom. The threshold voltage charac(cid:173)
`teristic of the transistor is controlled by the amount of
`charge that is retained on the floating gate. That is, the 25
`minimum amount of voltage (threshold) that must be
`applied to the control gate before the transistor is
`turned "on" to permit conduction between its source
`and drain regions is controlled by the level of charge on
`the floating gate.
`The floating gate can hold a range of charge and
`therefore an Eprom memory cell can be programmed to
`any threshold level within a threshold window. The
`size of the threshold window, delimited by the mini(cid:173)
`mum and maximum threshold levels of the device, de- 35
`pends on the device's characteristics, operating condi(cid:173)
`tions and history. Each distinct threshold level within
`the window may, in principle, be used to designate a
`definite memory state of the cell.
`For Eprom memory, the transistor serving as a mem- 40
`ory cell is programmed to one of two states by acceler(cid:173)
`ating electrons from the substrate channel region,
`through a thin gate dielectric and onto the floating gate.
`The memory states are erasable by removing the charge
`on the floating gate by ultra-violet radiation.
`An electrically erasable and programmable read only
`memory (EEprom) has a similar structure but addition(cid:173)
`ally provides a mechanism for removing charge from its
`floating gate upon application of proper voltages. An
`array of such EEprom cells is referred to as a "Flash" 50
`EEprom array when an entire array of cells, or signifi(cid:173)
`cant group of cells of the array, is erased simultaneously
`(i.e., in a flash). Once erased, a cell can then be repro(cid:173)
`grammed.
`A specific, single cell in a two-dimensional array of 55
`Eprom, EEprom cells is addressed for reading by appli(cid:173)
`cation of a source-drain voltage to source and drain
`lines in a column containing the cell being addressed,
`and application of a control gate voltage to a word line
`connected to the control gates in a row containing the 60
`cell being addressed.
`An addressed memory cell transistor's state is read by
`placing an operating voltage across its source and drain
`and on its control gate, and then detecting the level of
`current flowing between the source and drain. The 65
`level of current is proportional to the threshold level of
`the transistor, which in turn is determined by the
`amount of charge on its floating gate.
`
`45
`
`SUMMARY OF THE INVENTION
`These and additional objects are accomplished by
`improvements in EEprom array read and write circuits
`and techniques in order to provide multiple threshold
`levels that allow accurate reading and writing of more
`than two distinct states within each memory cell over
`an extended lifetime of the memory cells, so that more
`than one bit may be reliably stored in each cell.
`According to one aspect of the present invention, the
`multiple threshold breakpoint levels are provided by a
`set of memory cells which serves as master reference
`cells. The master reference cells are independently and
`externally programmable, either by the memory manu(cid:173)
`facturer or the user. This feature provides maximum
`flexibility, allowing the breakpoint thresholds to be
`individually set within the threshold window of the
`device at any time. Also, by virtue of being an identical
`device as that of the memory cells, the reference cells
`closely track the same variations due to manufacturing
`
`23
`
`

`
`5,172,338
`
`3
`processes, operating conditions and device aging. The
`independent programmability of each breakpoint
`threshold level allows optimization and fine-tuning of
`the threshold window's partitioning, critical in multi(cid:173)
`state implementation. Furthermore, it allows post- 5
`manufacture configuration for either 2-state or multi(cid:173)
`state memory from the same device, depending on user
`need or device characteristics at the time.
`According to another aspect of the present invention,
`a set of memory cells within each sector (where a sector ·10
`is a group of memory cells which are all erased at the
`same time in a Flash EEprom) are set aside as local
`reference cells. Each set of reference cells tracks the
`Flash cells in the same sector closely as they are both
`cycled through the same number of program/erase 15
`cycles. Thus, the aging that occurs in the memory cells
`of a sector after a large number of erase/reprogram
`cycles is also reflected in the local reference cells. Each
`time the sector of flash cells is erased and repro(cid:173)
`grammed, the set of individual breakpoint threshold 20
`levels are re-programmed to the associated local refer(cid:173)
`ence cells. The threshold levels read from the local
`reference cells then automatically adjust to changing
`conditions of the memory cells of the same sector. The
`threshold window's partitioning is thus optimally main- 25
`tained. This technique is also useful for a memory that
`employs only a single reference cell that is used to read
`two state (I bit) memory cells.
`According to another aspect of the present invention,
`the threshold levels rewritten at each cycle to the local 30
`reference cells are obtained from a set of master cells
`which are not cycled along with the memory cells but
`rather which retain a charge that has been externally
`programmed (or reprogrammed). Only a single set of
`master memory cells is needed for an entire memory 35
`integrated circuit.
`In one embodiment, the read operation directly uses
`the threshold levels in the local reference cells previ(cid:173)
`ously copied from the master reference cells. In another
`embodiment, the read operation indirectly uses the 40
`threshold levels in the local reference cells even though
`the reading is done relative to the master reference cells.
`It does this by first reading the local reference cells
`relative to the master reference cells. The differences
`detected are used to offset subsequent regular readings 45
`of memory cells relative to the master reference cells so
`that the biased readings are effectively relative to the
`local reference cells.
`According to another aspect of the present invention,
`a read operation on a memory cell determines which
`memory state it is in by comparing the current flowing
`therethrough with that of a set of reference currents
`corresponding to the multiple threshold breakpoint
`levels.
`In one embodiment, the current flowing through a 55
`cell being read is compared one-by-one with each of the
`threshold current levels of the reference cells.
`In another embodiment, the current flowing through
`a cell to be read is compared simultaneously with that of
`the set of reference cells. A special current mirror con- 60
`figuration reproduces the current to be read without
`degrading its signal, into mUltiple branches, one for
`each threshold current comparison.
`According to another aspect of the present invention,
`where a programmed state is obtained by repetitive 65
`steps of programming and verifying from the "erased"
`state, a circuit verifies the programmed state after each
`programming step with the intended state and selec-
`
`4
`tively'inhibits further programming of any cells in the
`chunk that have been verified to have been pro(cid:173)
`grammed correctly. This enables efficient parallel pro(cid:173)
`gramming of a chunk of data in a multi-state implemen(cid:173)
`tation.
`According to another aspect of the present invention,
`where a chunk of EEprom cells are addressed to be
`erased in parallel, an erased state is obtained by repeti(cid:173)
`tive steps of erasing and verifying from the existing state
`to the "erased" state, a circuit verifies the erased state
`after each erasing step with the "erased" state and selec(cid:173)
`tively inhibits further erasing of any cells in the chunk
`that have been verified to have been erased correctly.
`This prevents over-erasing which is stressful to the
`device and enables efficient parallel erasing of a group
`of cells.
`According to another aspect of the present invention,
`after a group of cells have been erased to the "erased"
`state, the cells are re-programmed to the state adjacent
`the "erased" state. This ensures that each erased cell
`starts from a well defined state, and also allows each cell
`to undergo similar program/erase stress.
`The subject matter herein is a further development of
`the EEprom array read techniques described in copend(cid:173)
`ing patent application Ser. No. 204,175, filed Jun. 8,
`1988, by Dr. Eliyahou Harari, particularly the disclo(cid:173)
`sure relating to FIG. He thereof. Application Ser. No.
`204,175 is hereby expressly incorporated herein by ref(cid:173)
`erence, the disclosure with respect to the embodiments
`of FIGS. 11, 12, 13 and 15 being most pertinent.
`Additional objects, features and advantages of the
`present invention will be understood from the following
`description of its preferred embodiments, which de(cid:173)
`scription should be taken in conjunction with the ac(cid:173)
`companying drawings.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a cross-sectional view of an EEprom device
`integrated circuit structure that can be used to imple(cid:173)
`ment the various aspects of the present invention;
`FIG. 2 is a view of the structure of FIG. 1 taken
`across section 2-2 thereof;
`FIG. 3 is an equivalent circuit of a single EEprom
`cell of the type illustrated in FIGS. 1 and 2;
`FIG. 4 shows an addressable array of EEprom cells;
`FIG. 5 is a block diagram of an EEprom system in
`which the various aspects of the present invention are
`implemented;
`FIG. 6 illustrates the partitioning of the threshold
`50 window of an EEprom cell which stores one bit of data;
`FIG. 7A illustrates the partitioning of the threshold
`window of an EEprom cell which stores two bits of
`data;
`FIG. 7B illustrates the partitioning of the source(cid:173)
`drain conduction current threshold window of the EE(cid:173)
`prom cell of FIG. 7A;
`FIGS. 8A and 8B are curves that illustrate the
`changes and characteristics of a typical EEprom after a
`period of use;
`FIG. 9A illustrates read and program circuits for a
`master reference cell and an addressed memory cell
`according to the present invention;
`FIG. 9B illustrates multi-state read circuits with ref(cid:173)
`erence cells according to the present invention;
`FIGS. 9C(1)-9C(8) illustrate the timing for multi(cid:173)
`state read for the circuits of FIG. 9B;
`FIG. 9D illustrates one embodiment of a multi-state
`read circuit in which the memory state of an address
`
`24
`
`

`
`5,172,338
`
`5
`cell is sensed relative to a set of reference current levels
`simultaneously;
`FIG. 9E illustrates one embodiment of an IREF cir(cid:173)
`cuit shown in FIG. 9D as an EEprom cell programmed
`with a reference current;
`FIG. 9F illustrates a preferred implementation of the
`embodiment in FIG. 9D in which each IREF circuit is
`provided by a current source reproducing a reference
`current programmed in the EEprom cell;
`FIG. 9G illustrates another embodiment of an IREF \0
`circuit shown in FIG. 9D in which a reference current
`is provided in each branch by the conduction of a tran(cid:173)
`sistor of predetermined size;
`FIG. 9H illustrates another embodiment of a multi(cid:173)
`state read circuit in which the memory state of an ad- 15
`dress cell is sensed relative to a set of reference current
`levels simultaneously;
`FIG. 91 illustrates yet another embodiment ofa multi(cid:173)
`state read circuit in which the memory state of an ad(cid:173)
`dress cell is sensed relative to a set of reference current 20
`levels simultaneously;
`FIG. 10 illustrates a specific memory organization
`according to the present invention;
`FIG. 11 shows an algorithm for programming a set of 25
`local reference cells according to the present invention;
`FIG. 12A shows one embodiment of a read circuit
`using local reference cells directly;
`FIG. 12B shows a read algorithm for the embodiment
`of FIG. 12A;
`FIG. 13A shows an alternative embodiment of a read
`circuit using local reference cells indirectly;
`FIG. 13B is a programmable circuit for the biased
`reading of the master reference cells according the
`alternative embodiment;
`FIG. 13C is a detail circuit diagram for the program(cid:173)
`mable biasing circuit of FIG. 13B;
`FIG. 13D shows a read algorithm for the embodi(cid:173)
`ment of FIG. 13A;
`FIG. 14 illustrates the read/program data paths for a 40
`chunk of cell in parallel;
`FIG. 15 shows an on chip program/verify algorithm
`according to the present invention;
`FIG. 16 is a circuit diagram for the compare circuit
`according to the present invention;
`FIG. 17 is a circuit diagram for the program circuit
`with inhibit according to the present invention;
`FIGS. 18 and 19 show Tables 1 and 2 which list
`typical examples of operating voltages for the EEprom
`cell of the present invention.
`
`6
`and the drain of an adjacent cell, and similarly for an(cid:173)
`other n-doped region 21.
`Each of the memory cells 11 and 13 contains respec(cid:173)
`tive conductive floating gates 23 and 25, generally made
`5 of polysilicon material. Each of these floating gates is
`surrounded by dielectric material so as to be insulated
`from each other and any other conductive elements of
`the structure. A control gate 27 extends across both of
`the cells 11 and 13 in a manner to be insulated from the
`floating gates and the substrate itself. As shown in FIG.
`2, conductive strips 29 and 31 are additionally provided
`to be insulated from each other and other conductive
`elements of the structure, serving as erase gates. A pair
`of such erase gates surrounds the floating gate of each
`memory cell and are separated from it by an erase di(cid:173)
`electric layer. The cells are isolated by thick field oxide
`regions, such as regions 33, 35, and 37, shown in the
`cross-section of FIG. 1, and regions 39 and 41 shown in
`the view of FIG. 2.
`The memory cell is programmed by transferring elec(cid:173)
`trons from the substrate 15 to a floating gate, such as the
`floating gate 25 of the memory cell 13. The charge on
`the floating gate 25 is increased by electrons travelling
`across the dielectric from a heavily p-doped region 43
`and onto the floating gate. Charge is removed from the
`floating gate through the dielectric between it and the
`erase gates 29 and 31. This preferred EEprom structure,
`and a process for manufacturing it, are described in
`detail in copending patent application Ser. No. 323,779
`of Jack H. Yuan and Eliyahou Harari, filed Mar. 15,
`1989, which is expressly incorporated herein by refer-
`ence.
`The EEprom structure illustrated in FIGS. 1 and 2 is
`a "split-channel" type. Each cell may be viewed as a
`composite transistor consisting of two transistor Tl and
`T2 in series as shown in FIG. 3. The Tl transistor 110
`is formed along the length Ll of the channel of the cell
`11 of FIG. 1. It has a variable threshold voltage V n- In
`series with the Tl transistor 110 is the T2 transistor 11b
`that is formed in a p