Active Pixel Sensors: Are CCD's Dinosaurs?
`
`Eric R. Fossum
`
`Jet Propulsion Laboratory, California Institute of Technology
`4800 Oak Grove Drive, Pasadena, California 91 109 USA
`
`ABSTRACT
`
`Charge-coupled devices (CCD's) are presently the technology of choice for most imaging applications. In the 23 years since
`their invention in 1970, they have evolved to a sophisticated level of performance. However, as with all technologies, we
`can be certain that they will be supplanted someday. In this paper, the Active Pixel Sensor (APS) technology is explored as
`a possible successor to the CCD.
`
`An active pixel is defined as a detector array technology that has at least one active transistor within the pixel unit cell. The
`APS eliminates the need for nearly perfect charge transfer --the Achilles' heel of CCDs. This perfect charge transfer makes
`CCD's radiation "soft," difficult to use under low light conditions, difficult to manufacture in large array sizes, difficult to
`integrate with on-chip electronics, difficult to use at low temperatures, difficult to use at high frame rates, and difficult to
`manufacture in non-silicon materials that extend wavelength response. With the active pixel, the signal is driven from the
`pixel over metallic wires rather than being physically transported in the semiconductor.
`
`This paper makes a case for the development of APS technology. The state of the art is reviewed and the application of
`APS technology to future space-based scientific sensor systems is addressed.
`
`1. INTRODUCTION
`
`The charge-coupled device (CCD), while presently the imager technology of choice in scientific applications, is a dinosaur
`doomed to extinction. The likely successor to CCD technology is the Active Pixel Sensor (APS) technology, just emerging
`in the most advanced imager laboratories in Japan for application to high-definition television (HDTV) and electronic still
`cameras. While APS technology is still in its infancy, it is easy to extrapolate to the demise of CCDs. The APS technology
`preserves all the desirable features of CCDs, yet circumvents the major weaknesses of CCD technology.
`
`The Achilles' heel of CCD technology is fundamental to its operation --the need for the perfect transfer of charge across
`macroscopic distances through a semiconductor. Although CCDs have become a technology of choice for present-day
`implementation of imaging and spectroscopic instruments due to their high sensitivity, high quantum efficiency, and large
`format, it is well-known that they are a particularly difficult technology to master. The need for near-perfect charge transfer
`efficiency makes CCDs (1) radiation "soft," (2) difficult to reproducibly manufacture in large array sizes, (3) incompatible
`with the on-chip electronics integration requirements of miniature instruments, (4) difficult to extend the spectral
`responsivity range through the use of alternative materials, and (5)limited in their readout rate. A new imaging sensor
`technology that preserves the positive attributes ofthe CCD yet eliminates the need for charge transfer could quickly eclipse
`the CCD.
`
`Continued advancement in microlithography feature size reduction for the production of semiconductor circuits such as
`DRAMs and microprocessors since the invention of the CCD in 1970 enables the consideration of a new image sensor
`technology, called the Active Pixel Sensor (APS). In the new APS concept, one or more active transistors are integrated
`into the pixel of an imaging detector array, and buffer the photosignal as well as drive the readout lines. At any instant,
`only one row is active, so that power dissipation in the APS is less than that of the CCD. The physical fill-factor of the APS
`can be approximately 50% or higher, and the use of on-chip microlenses or binary optics can increase the effective fill-
`factor to over 80%. Sensitivity, read noise, and dynamic range are similar to the CCD. Thus, the APS preserves the high
`performance of the CCD but eliminates the need for charge transfer.
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`2 I'PIE Vol. 1900
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`The APS concept represents a significant revolution in scientific image acquisition. Since CCDs are used ubiquitously in
`imaging and spectroscopic instruments, the benefits of a technology not susceptible to the shortcomings of CCDs described
`above can be immense. This technology can enable a large step in the miniaturization of instrument systems by allowing a
`high degree of electronics integration on the focal-plane. Since the APS technology allows random-access (window-of-
`interest) capability, new guidance and navigation sensors can be envisioned.
`
`This paper explores APS technology. The limitations of CCDs due to the requirement for nearly perfect charge transfer are
`discussed. Related technologies to APS such as photodiode arrays, charge-injection devices, and hybrid infrared focal-plane
`arrays are also discussed. The APS concept is then introduced. Both lateral and vertical configurations are described. The
`advantages of APS technology are summarized. The state of the art of APS technology development is then addressed.
`CMD, BCMD, SIT, and other device structures are reviewed. Finally, applications of APS technology to projected NASA
`mission needs are described.
`
`2.1 What's wrong with CCDs
`
`2. BACKGROUND
`
`The charge-coupled device (CCD), an electronic analog shift register, was invented in 1970. In the intervening 23 years,
`the CCD has become the primary technology used in scientific image sensors. The details of CCD technology are complex,
`even for students of semiconductor device physics. It is not possible to provide a complete description of CCD operation in
`this paper, but the interested reader is referred to texts such as that by Yang1 or Tompseu2. The virtues of the CCD include
`its high sensitivity, high fill-factor, and large formats. The high sensitivity arises from a high net quantum efficiency of the
`order of 40%, the high fidelity of reading out the CCD, and the low noise output amplifier. Typical output amplifier noise
`is of the order of 5 electrons r.m.s. due to the low capacitance of the output sensing node. The high fill-factor of a CCD
`pixel (80%-100%) is due to the fact that the MOS photodetector is also used for the readout of the signal. The large format
`of CCDs (typically 1024x1024, and as high as 4096x40963) has been enabled by the concurrent drive of the semiconductor
`memory business to improve silicon wafer quality and fabrication yield.
`
`Even as the scientific CCD has become the baseline detector technology for visible imaging and spectrometer systems, its
`weaknesses have also gained in importance and driven the development of alternative imaging technologies, with the high
`performance CCD as a benchmark.
`
`The Achilles' heel oJCCDs isfundamental to the CCD operating principle -- the needjor nearly perfect charge transfer.
`The CCD relies on the transfer of charge (usually electrons) from under one MOS electrode to the next through sequencing
`of voltages on the electrodes. The electrons are transported through the bulk silicon material macroscopic distances (e.g.,
`centimeters) before they reach the output sense node. A typical CCD has three electrodes per pixel, so that in a 1024x1024
`imager, the electrons may be shifted, on the average, several thousand times. The ratio of electrons successfully transferred
`to number left behind per electrode is the charge transfer efficiency (CTh). The CTh needs to be as close as possible to
`perfect to enable scientifically acceptable performance of the CCD. If the CTE is given by i, the net fraction of signal
`transferred after m transfers is simply 1m• As shown in the table below, the CTE must be very high.
`
`Table 1. CCD Fidelity vs. CTE
`
`ARRAY
`SIZE
`
`1024x1024
`
`2048x2048
`4096x4096
`8192x8192
`
`CTE
`
`•
`
`FRACTION
`AT OUTPUT
`
`0.999
`0.9999
`0.99999
`0.99999
`0.99999
`0.99999
`
`0.128
`0.815
`0.980
`0.960
`0.921
`0.849
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`SPIE Vol. 1900/3
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`Typical scientific CCDs have a CTE of 0.99999 and a representative number of electrons in a scientific CCD signal packet
`is 1,000. For a CTE of 0.99999, this means only one electron can be lost every 100 transfers! Since a single broken bond
`in the silicon crystal can (and usually will) capture a signal electron, the need for perfect silicon crystal quality is the major
`weakness of the CCD.
`
`The need for perfect transfer efficiency has a great impact on the viability of CCDs for future space missions. The five
`major issues are (1) the radiation softness of CCDs, (2) a difficulty to achieve large array sizes, (3) an incompatibility of
`CCDs with the requirements for instrument miniaturization, (4) difficulty in increasing the spectral responsivity range of
`CCDs, and (5) difficulty in increasing the readout rate of CCDs. These issues are described below.
`
`Radiation softness
`
`CCDs suffer from both ionizing and displacement damage. Ionizing damage affects the oxide, and is not considered critical
`since processes that harden the oxide against ionization damage are well known. On the other hand, displacement damage
`caused by high energyparticles andphotons is deadly to CCDs. Particularly damaging are protons in the few hundred keV
`range. A single 250 keV proton causes an average of 10 silicon lattice displacements4, though higher and lower energy
`protons can be less damaging. If all radiation consisted of 250 keV protons, then 1 krad corresponds to a fluence of
`approximately 125,000 protons/cm2, or for a 1024x1024 CCD with 20 micron pixels, approximately 5 electron traps per
`pixel. Fortunately, only a fraction of the (jost-shielding) protons fall in this maximum damage regime, so that the actual
`dose tolerance of a 1024x1024 CCD is about 10 krads. For future orbiter missions around Jupiter and Saturn, the use of
`CCD technology is tenuous at best. Certain earth-observing orbits can also result in high dose rates. Future spacecraft with
`nuclear propulsion systems are expected to generate high radiation dose rate environments. It should be noted that the
`radiation tolerance of a CCD gets worse as the sensor format gets larger since more transfers are required to deliver the
`signal electrons to the output amplffier.
`
`Difficulty to achieve large array sizes
`
`Since the net transfer efficiency goes exponentially with number of transfers (1ffl),it is obvious that as CCD array sizes
`grow larger, the requirement on transfer efficiency becomes more stringent. To compensate, readout rate must be
`decreased, but scientific CCDs are already slow to read out (50 kpixels/sec, or 20 seconds per frame for a 1024x1024 CCD).
`The radiation dose tolerance decreases with increased array size as described above. The manufacturing yield decreases as
`the array size grows, particularly since CCDs are highly vulnerable to single point defects that can block an entire column.
`This is why only one or two 4096x4096 CCD ICs have actually been demonstrated, and they had numerous defects. The
`drive power requirement for CCDs also grows with array size since CCDs are capacitive in nature, and the entire CCD must
`be driven to achieve the output of a single pixel.
`
`Incompatibility with miniature instrument requirements
`
`Instrument miniaturization will require highly integrated, low-power sensor electronics. This will, in turn, require on-chip
`timing and driver electronics, as well as on-chip signal chains and perhaps analog-to-digital conversion for the image
`sensor. The CCD device structure is not easily integratable with CMOS. Furthermore, CCDs typically require high and
`varied voltages, also incompatible with low-power CMOS electronics. Operating on-chip devices with high voltages can
`cause emission of infrared radiation that is detected by the imager, contaminating the image. While it is possible that first-
`generation miniature instruments may utilize CCDs with off-chip electronics, the future of smart miniature imaging and
`spectrometry instruments will require a more tractable technology.
`
`Extension of spectral range
`
`Future astrophysics and planetary instruments will benefit from large, monolithic detector arrays that extend the nominal
`0.4 - 1.0 micron spectral range of CCDs. Increasing the spectral responsivity range of CCDs requires the utilization of
`materials other than silicon, and/or the removal of structures integral to CCD operation. Blue, ultraviolet and soft x-ray
`response requires the elimination of overlying electrodes that absorb higher energy photons. Backside illumination has
`been used on the ground with some success but the long term stability of backside illuminated CCD structures for UV
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`response has prevented their widespread use in space instruments (an exception is the WFIPC instrument in HST and it
`required significant modification to apply a last minute, expensive, (albeit successful) Rube Goldberg-like remedy). Low-
`QE, low-MiT, down-converting phosphors (lumogen) deposited on the front-side of CCDs will be used on WFIPC II.
`Pinned photodiode inter-line transfer CCDs have been developed by Kodak5 and used with some success to overcome these
`problems. Infrared response of silicon CCDs requires integration of infrared absorbing materials such as platinum suicide6
`or SiGe junctions7'8. These devices suffer from very low QE and incomplete reset resulting in large kTC noise. Large
`format scientific CCDs in non-silicon materials (e.g., GaAs, InGaAs, Ge, diamond) are unlikely to be achieved due to the
`relative immaturity of these materials compared to silicon. Non-CCD structures will be required to achieve monolithic,
`large format, scientific performance.
`
`Limited readout rate
`
`For many present and future applications, the readout rate of scientific CCDs (50kpixels/sec) is nearly too slow for practical
`use. Examples include star trackers and fine guidance sensors, astrophysics and material analysis instruments requiring
`photon position and energy information (energy is proportional to the number of photoelectrons), and imaging systems
`supporting microgravity materials processing experiments on Space Station Freedom. Three to five orders of magnitude
`improvement in detector array readout rate is required. While some high speed, large format CCDs are being developed for
`HDTV (1900x1 120 at 70 Mpixels/s), the performance of these CCDs is inferior to the competing APS technology, and not
`suitable for most scientffic applications. This is because charge transfer efficiency degrades rapidly with increasing transfer
`rate.
`
`Other well-known problems stenmüng from charge-transfer in CCDs includes low temperature performance degradation
`due to the onset of carrier freeze-out (e.g. an on-focal plane SIRTF fine guidance sensor operating at 4K could not use a
`CCD, or the MIT Lincoln Laboratory infrared BIP-CCD performance limited by low temperature CCD CTE8), and spurious
`charge generation in virtual phase CCDs.
`
`In essence then, nearly all the problems with CCDs stem from the need to efficiently transfer electrons through macroscopic
`distances of semiconductors. If the need to transfer the signal can be eliminated, detector array performance can be
`significantly be enhanced.
`
`2.2 Related Image Sensor Technologies
`
`Photodiode Arrays
`
`Imaging photodiode arrays predate CCDs by a few years9. Pixels contain a p-n junction, an integrating capacitor (often the
`p-n junction itself) and MOS selection transistors. The photodiodes on a single row are typically bussed together on an
`output line with a column selection transistor connecting a single photodiode at a time to the bus. The photodiode array
`(the reticon) was one of the first solid-state imaging devices and had large advantages over its vacuum tube predecessors.
`Compared to the CCD, however, the photodiode array was more complex since selection transistors had to be fabricated
`within each pixel, and some on-chip multiplexer circuits had to be fabricated as well. Later, the noise of the photodiode
`array also became a limitation to its performance compared to the CCD since the photodiode readout bus capacitance results
`in an increase in noise level. Correlated double-sampling (CDS)'° cannot be readily employed with a photodiode array
`without external memory.
`
`Recently, a photodiode array configured for random accessibility with on-chip CMOS circuitry was reported1 . This 80x80
`prototype array was designed for random accessibility and included an in-pixel source-follower to minimize bus capacitance
`effects (making it an active pixel sensor as described below.) The pixel size using 3 im CMOS design rules was 144 jtm x
`144 tm with a fill-factor of 6%. An estimated input referred noise level of approximately 250 electrons r.m.s. was reported.
`This noise was dominated by (kTC)1"2 processes inherent in photodiode arrays. The architecture also is susceptible to
`significant fixed-pattern noise and 1/f noise since CDS cannot be readily applied.
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`SPIEVo!. 1900/5
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`Charge Injection Devices
`
`The charge injection device (CD) was invented in the early 1970's, a few years after the invention of the CCD12. The CD,
`unlike the CCD, requires only a single, intra-pixel charge transfer. The charge is shifted under a floating sense gate and the
`induced voltage change is the output signal. Thus, CJDs are immune to the deleterious effects of imperfect charge transfer
`and have been used in high radiation environments. CIDs also feature random accessibility of the pixels, high fill-factor,
`and good bluefEJV response. Unfortunately, the CD, like the photodiode and MOS imager, suffers from high bus
`capacitance since the sense gates of all pixels on a given row are tied in parallel. In a recent paper, a high performance
`5 12x5 12 CD imager was reported to have a single-read input-referred noise level of 220 electrons r.m.s. 13 The CD,
`however, can be operated in non-destructive readout mode so that multiple reads of the same signal can be performed and
`averaged together. Multiple sampling results in a nearly (1/N)"2 reduction in read-noise level where N is the number of
`reads so that the input-referred read-noise level after 100 reads is reported to be 26 electrons r.m.s. The drawback of
`multiple reads is an N-fold increase in readout time and a need to reduce dark current14.
`
`Hybrid JR FPAs
`
`Hybrid infrared focal-plane arrays typically consist of a detector array chip bump-bonded to a silicon readout
`multiplexer'56. Each detector pixel has an associated unit cell in the multiplexer that contains an integrating capacitor,
`selection transistors, and usually some preamplifier of varying sophistication. For example, a capacitive transimpedance
`amplifier (CTIA) can be integrated within the unit cell to maintain constant bias on the detector and reduce low RoA
`effects. The separation of detector and unit cell electronics allows for separate optimization of each, and enables detector
`pixels with nearly 100% fill factor. Read noise is typically in the 30-50 electron r.m.s. range, though multiple sampling can
`17 The major difficulty associated with hybrid JR EPA technology is the manufacturability of the
`help reduce the noise
`hybrid. A second difficulty is that when the detector and readout multiplexer are made of differing materials, stress is
`induced by the difference in thermal expansion coefficients when the hybrid assembly is cooled. The stress can lead to
`reliability concerns regarding the structure's integrity.
`
`3. ACTiVE PIXEL SENSOR CONCEPT
`
`The active pixel sensor (APS) technology preserves the desirable attributes of CCDs such as high sensitivity, high signal
`fidelity and large array formats. The recent invention of the on-chip microlense or binary optics allows the nominal 50%
`fill-factor of the APS to approach to 80-90% fill factor of the CCD. The APS approach does not require charge-transfer
`across macroscopic distances and thus eliminates the five negative major issues associated with CCD detector arrays
`described above.
`
`(S
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`An active pixel sensor (APS) is defined as a sensor with one or more active transistors located within each pixel. The in-
`pixel active transistors can provide both gain and buffering functions. Twenty years ago, an active pixel sensor with a
`practical pixel size was not possible due to the state-of-the-art
`of microlithography in the early 1970's. The technological
`of
`has
`driven
`the
`semiconductor
`industry
`push
`microlithography to the sub-micron regime, and 1.25 micron
`CMOS is practically an industry standard. It is in the shadow
`of this progress that the fundamental advantage CCDs had over
`any other imaging technology has been eclipsed. CCDs in the
`1970's were attractive because only three electrodes were
`required per pixel to make them operate. A 30 micron pixel
`was thus possible. However, pixel size is determined more by
`in the 1990's
`than by
`scientific imaging optics
`microlithography constraints. Thus, there is a new window of
`opporturnty to take advantage of the advances in
`microlithography as it continues its inevitable evolution driven
`by the digital microelectronics industry.
`
`1985
`YEAR
`Fig. 1 . Evolution of photolithographic feature size vs.
`pixel size.
`
`1990
`
`1995
`
`2000
`
`

`
`3.1 Lateral APS
`
`A lateral APS structure is defined as one that has part of the pixel area used for photodetection and signal storage, and the
`other part is used for the active transistor(s). The advantage of this approach, compared to a vertically integrated APS, is
`that the fabrication process is simpler, and is highly compatible with state-of-the-art CMOS and CCD device processes. A
`simple example of a lateral APS device compatible with CMOS is shown below in Fig. 2.
`
`In this device, charge is integrated under the photogate PG. Prior to
`readout, the output floating diffusion node is reset using the in-pixel
`reset transistor R. For readout, in-pixel selection transistor S is
`selected, connecting the in-pixel source-follower to a column bus
`line. To reduce noise, the voltage of the floating diffusion node can
`be sensed and later used for CDS. The photosignal is then
`transferred from PG to into the floating diffusion node. This simple
`output amp. intra-pixel transfer is similar to that required for CII) operation.
`However, unlike the CD, the capacitance represented by the floating
`diffusion node is very small, like that found in a CCD output
`amplifier, so that the charge to voltage conversion can be of the order
`of 10 V/electron. Since this structure allows CDS, kTC and 1/f
`noise can be suppressed. CDS also removes threshold voltage fixed-
`pattern noise. A sample layout of this simple APS pixel is shown below in Fig. 3.
`
`Fig.2. Schematic of a simple, CMOS-compatible
`active pixel.
`
`When implemented in commercially available 0.8 m CMOS, the pixel
`size shown is 16 m x 16 j.m with a fill factor of over 50%. With a
`microlens placed over the cell (as illustrated in Fig. 4), one might
`anticipate a fill factor increase to over 80%. The spectral response of the
`cell shown will be approximately that of a standard double-poly CCD
`image sensor. The noise level anticipated for this device is similar to that
`obtained for CCDs (3-5 electrons r.m.s.) if a buried-channel CMOS
`process is used.
`
`3.2 Vertical APS
`
`PG
`
`TX
`
`A vertical APS structure increases fill-factor (or reduces pixel size) by
`storing the signal charge under the output transistor. Both field-effect
`vertical APS structures (CMD, FGA, BCMD) and bipolar (BASIS) APS
`structures have been developed, as described below. In the field-effect
`structure, the signal charge acts as a backgate bias on a lateral MOS (or
`WET) transistor at the surface. In the bipolar structure, the signal
`changes the
`hv
`charge
`base-emitter bias of a
`bipolar transistor. The vertical configuration trades plan-view complexity
`for vertical structure complexity.
`
`v+
`VOUT
`Fig. 3. Layout of a simple CMOS-compatible
`APS pixel.
`
`R
`S
`
`— 'Dead" region
`
`Photosensitive region
`
`Fig. 4. Schematic illustration of on-chip
`microlens array to increase effective fill-factor.
`
`3.3 Advantages of the APS
`
`Since APS technology requires intra-pixel transfer, at most, the
`consequences of CCD charge transfer are ameliorated. Thus, APS
`imagers can be expected to be radiation hard, operate well at lower
`temperatures, be fabricated in large array sizes, and be more compatible
`with advanced materials. It is noted that the readout of APS can involve
`either lateral transistors or vertical transistors. Vertical output has the
`advantage of requiring one less surface contact and enables smaller pixels.
`
`SPIEVo!. 1900/7
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`

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`However, it also implies a common (substrate) connection to all output amplifiers and thus may restrict imager architecture.
`
`4. STATE-OF-THE-ART
`
`In the past few years, several innovative APS technologies have been proposed and explored. Most of these activities are
`centered in Japan for the development of HDTV video cameras and electronic still cameras. Most of the actual fabrication
`activities of Texas Instruments takes place in Japan as well. There are no activities known to the author in the United States
`or Europe at this time in the APS area except for some recent work at JPL.
`
`IG
`
`IG
`
`Double-gate floating surface transistor (Toshiba)
`
`PG
`
`DGO
`
`A lateral APS technology has been under development by
`Toshiba'8. Termed the "double-gate floating surface
`transistor," it utilizes a readout transistor evolved from the
`low noise CCD outout amplifier proposed by Brewer19 and
`refined by hi21 . Shown schematically in Fig. 5, the
`pixel consists of a buried-channel MOS photogate (PG)
`region that integrates and stores optically generated
`electrons. The output amplifier is a surface p-channel
`MOSFET. The electron signal charge is transferred under
`the conductive p-channel to an n-doped confinement region
`(DG). The electrons are confined vertically by a p-well
`between the storage area and the n-substrate. The electron
`signal charge acts as a back gate on the p-MOSFET.
`Readout of the Toshiba sensor is accomplished a row at a
`time using a charge-domain "line potential modulation"
`technique that provides charge gain and reduces the readout
`bandwidth requirements on individual in-pixel transistors.
`A sensitivity of 200 V/e- and a charge gain of 1, 100 was
`repoited. Readout noise was reported to be 880 holes
`corresponding to an input-referred noise of 0.8 electrons
`r.m.s. The readout is non-destructive and, in principle,
`multiple reads could be performed to reduce white noise. The most serious problem currently facing this technology is dark
`fixed pattern noise (FPN) due to detection transistor potential variations. The 10 % FPN may, in principle, be reduced by
`reading the output amplifier twice, once following charge transfer, and once following charge ejection. The difference
`signal might reduce FPN and the expense of signal readout time.
`
`DG
`0
`— U: PG__j:;-lI-..:l
`___________
`n ••
`
`p-well
`___________________
`
`n-sub
`
`Fig. 5. Schematic illustration of Toshiba floating-surface
`transistor. Upper left is plan view. Upper right is a cut
`through output transistor. Lower right is potential in
`transistor. Lower left is lateral cut through plan view.
`
`4.2. Charge Modulation Device (CMD) (Olympus)
`
`PG
`
`Fig. 6. Schematic illustration of Olympus CMD
`pixel
`
`8/SPIE Vol. 1900
`
`The charge modulation device (CMD) ima&er has been under
`development by Olympus for several years22'23'24'25. It is a vertical
`APS and involves no charge transfer. The optically-generated-hole
`signal charge is integrated at the MOS surface. A buried n-channel
`MOSFET in a concentric ring configuration surrounds the collection
`region. The pixel size has been reduced to 7.3 m x 7.6 .tm. The
`presence of the surface hole charge modulates the buried n-channel
`MOSFET current when the transistor is selected for readout. The
`current is sensed by a transimpedance amplifier and converted to a
`voltage. The conversion gain was recently reported as 250 pA/hole.
`Dark current was 4 fA/pixel or of the order of 10 nA/cm2, possibly
`reflective of the unaccumulated Si-Si02 surface. The shot noise of the
`high dark current has significant impact on total input-referred noise.
`Input-referred noise is estimated to be 400 holes r.m.s., but can be
`
`

`
`reduced by suppressing dark current through cooling. Fixed pattern noise is also high, corresponding to approximately
`1,360 holes r.m.s. and is attributed to geometric variations. Other noise sources in the output amplffier (e.g. 1/f) and FPN,
`in principle, could be suppressed by resampling the output immediately following readout and reset.
`4.3. Bulk Charge Modulation Device (Texas Instruments)
`
`_________
`
`The bulk charge modulated device (BCMD) has evolved from an initial JFET floating-gate array (FGA) sensor at Texas
`Instruments26. The JFET, while allowing high blue response, has some problems related to reset. The BCMD is an
`improved photosite structure and is similar in concept the CMD device described above, but is more complex and has
`higher performance27. The BCM1) consists of a buried p-
`PG
`channel readout transistor that is backgated by signal
`I
`electrons in an n-type confinement region below the
`readout transistor. The confinement region is fully
`depleted by a vertical reset operation that dumps any
`signal electrons over a deeper p-type barrier into the n+
`substrate. Optically generated electrons are collected and
`integrated in the confinement region. The vertical APS
`with its complex vertical layer structure has the advantage
`that a low-noise buried p-channel MOSFET is used for
`readout. Also, surface generated dark current is collected
`by the FET source and drain and repelled from the
`confinement region. However, experimental dark current
`was anomalously high (1.5 nA/cm2). The readout is
`voltage mode where the potential of the confinement
`region is translated into a source-follower output voltage.
`Fig. 7. Schematic illustration Texas Instruments' BCMD
`Conversion was reported to be 15 j.V/e- with a 15 electron
`pixel.
`r.m.s. input referred noise level likely dominated by dark
`current shot noise. Readout is row-at-a-time into a bank of storage capacitors later scanned for serial output. The image
`sensor was configured as a hexagonally-packed array with on-chip color filters.
`
`4.4. Base-Stored Image Sensor (BASIS) (Canon)
`
`The base-stored image sensor (BASIS) has been under development by
`Canon28'29'30. This vertical bipolar transistor-based device consists
`of a p-type base layer sandwiched between an n+ emitter and a n+
`collector (substrate). The base is reset to a voltage level using a clamp
`transistor chain and followed by capacitively coupling of the base-
`emitter junction into forward bias for a short period of time. Since the
`base is not fully depleted, its reset voltage is susceptible to kTC noise.
`Optically generated holes flow to the p-type base where they are
`integrated. During readout, the final base voltage is readout using the
`bipolar transistor in an emitter-follower mode onto a capacitor at the
`end of the column line. The cell is then reset and the reset level is
`sampled and stored on a second capacitor. The output signal is the
`difference in voltage on these two capacitors. While this operation
`does not reduce kTC noise, it does suppress FPN to a very low level.
`
`4.5. Static Induction Transistor (SIT) (Olympus)
`
`cL
`L!:
`I
`
`Emitter
`
`__j [p+L.]
`n-
`
`n+ substrate
`
`Collector
`
`Fig. 8. Bipolar image sensor (BASIS) developed
`by Canon.
`
`In addition to the CMD device described above, Olympus has also been developing a static induction transistor (SIT) image
`sensor3 1,32 The SIT utilizes vertical electron current flow between the surface and substrate. Unlike diffusion transport in
`the base of a bipolar transistor, the electron current is controlled by a surrounding p+ field-effect gate that electrostatically
`controls the barrier to vertical current flow. The floating p+ gate is reset by forward biasing the p+-n junction. Since the
`
`SPIE Vol. 1900/9
`
`

`
`Gte
`
`gate is not fully depleted, kTC noise is introduced in its reset operation
`and the device is also susceptible to image lag. Image lag is
`significant without bias light. After reset, optically generated holes
`flow to the gate and change its potential. During readout, the gate is
`capacitively coupled to a read line and is bootstrapped to a less
`negative potential, thereby turning on the SIT. The SIT readout is in
`source-follower voltage mode, row-at-a-time, onto holding capacitors.
`The voltage in the holding capacitors is then scanned for serial
`readout. The SIT image sensor readout is non-destructive, thereby
`allowing, in principle, multiple reads to reduce white noise33. A reset
`gate could also be added to improve lag, but at the expense of pixel
`size.
`
`Fig. 9. Olympus SIT pixel.
`4.6. JPL Activity
`
`ABDABG
`
`PG
`
`RH
`
`TX
`
`c'ii