EXHIBIT 1032
`
`U.S. PATENT NO. 4,011,442 TO ENGELER
`
`(“ENGELER”)
`
`
`
`
`
`
`TRW Automotive U.S. LLC: EXHIBIT 1032
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NUMBER 8,599,001
`IPR2015-00436
`
`

`
`United States Patent
`
`[,9]
`
`Engeler
`
`1541
`
`1751
`[731
`
`[22]
`
`[21]
`152]
`
`1511
`[58]
`
`[56]
`
`APPARATUS FOR SENSING OPTICAL
`SIGNALS
`
`Inventor: William E. Engeler, Scotia, N.Y.
`
`Assignee:
`
`Filed:
`
`General Electric Company,
`Schenectady, N.Y.
`Dec. 22, 1975
`
`Appl. No.: 643,539
`U.S. c1. .......................... .. 235/193; 250/211 1;
`307/221 D; 340/173 LS; 358/213
`Int. CL? .................... .. G06G 7/12; H04N 3/14
`Field of Search ................ .. 235/193, 156, 152-,
`178/7.1, DIG. 3, DIG. 12; 250/211 J, 211 R,
`578; 357/24, 30, 32; 340/173 LS; 307/221 C,
`221 1)
`
`References Cited
`
`UNITED STATES PATENTS
`
`3,717,770
`3,801,820
`3,856,989
`3,904,818
`
`................... .. 250/211 J
`Dyck et al.
`2/1973
`Eichelberger et al.
`....... .. 250/211 J
`4/1974
`12/1974 Weimer ............................. .. 178/71
`9/1975
`Kovac ............................... .. 178/7.1
`
`[11]
`
`[45]
`
`4,011,442
`
`Mar. 8, 1977
`
`3,919,468
`
`11/1975 Weimer ............................ .. 178/7.1
`
`OTHER PUBLICATIONS
`
`Pratt et al.-—“Hadamard Transform Image Coding”—-
`Proceedings of the IEEE, vol. 57, No. 1, Jan. 1969, pp.
`58-68.
`‘
`
`Primary Examiner—JOseph F. Ruggiero
`Attorney, Agent, or Firm—Julius J. Zaskalicky; Joseph
`T. Cohen; Jerome C. Squillaro
`
`[571
`
`I ABSTRACT
`
`In optical imaging apparatus a semiconductor substrate
`in which a pattern of charge is produced in a plurality
`of charge storage sites therein in accordance with a
`spatial pattern of radiation, output means are provided
`for deriving an output comprising signals proportional
`to the algebraic sums of selected combinations of the
`charge in the plurality of charge storage sites.
`
`12 Claims, 28 Drawing Figures
`
`c/ecu/r 1
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`1032-001
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`U.S. Patent Mar. 8, 1977
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`Sheet 1 of 8
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`U..S. Patent Mar. 3, 1977
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`U..S. Patent Mar. 8, 1977
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`U.S. Patent Mar. 8, 1977
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`2
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`APPARATUS FOR SENSING OPTICAL SIGNALS .
`
`The present invention relates to apparatus utilizing
`arrays of semiconductor imaging devices for sensing
`optical signals.
`In arrays of semiconductor imaging devices an opti-
`cal signal in the form of a spatial pattern of radiation is
`imaged on the array and produces in charge storage
`sites of the devices a pattern of charge carriers propor-
`tional to the spatial pattern of radiation. The charge
`storage at each site is individually addressed in various
`ways. One way is by transporting it over a long distance
`in large arrays of sites to an output device where it is
`sensed to obtain signals
`representing the charges
`stored. When small quantities of charge are involved
`the attenuation occurring in the transport process
`makes it difficult to provide high sensitivity in such
`arrays. Another way is by sensing the charge storage at
`the charge storage site. In large arrays large capaci-
`tances are associated with the sensing circuits and ac-
`cordingly small signal sensing becomes difficult if not
`impossible.
`The present invention is directed to overcoming the
`limitations such as pointed out above in prior art meth-
`ods and apparatus for reading out point intensity sig-
`nals in semiconductor imaging arrays.
`An object of the present invention is to provide im-
`provements in semiconductor imaging devices and in
`the method and apparatus for the operation thereof.
`Another object of the present invention is to directly
`read out image transform information from solid state
`imaging apparatus.
`Another object of the present invention is to provide
`semiconductor imaging devices of simple construction
`and high sensitivity.
`Another object of the present invention is to provide
`method and apparatus for reading out imaging arrays
`with improved signal to noise ratio.
`‘
`«
`A further object of the present invention is to provide
`apparatus for readout of imaging arrays of semiconduc-
`tor devices rapidly and efficiently.
`.
`In carrying out the invention in an illustrative em-
`bodiment there is provided a substrate of one conduc-
`tivity type having a major surface. Means. are provided ’
`for forming a plurality of charge storage sites for oppo-
`site type carriers adjacent the major surface of the
`substrate. Means are provided for exposing the sub-
`strate to a spatial pattern of radiation to produce a
`pattern of opposite type carriers of variable quantity in
`the plurality of storage sites in each of which the quan-
`tity of opposite type carriers is proportional
`to the
`spatial pattern of radiation. Output means are provided
`in the form of electrodes insulatingly overlying the
`substrate for deriving an output comprising signals
`proportional to the algebraic sum of selected combina-
`tions of the charge in the first plurality of charge stor-
`age sites.
`The features which are believed to be characteristic
`of the present invention are set forth with particularity
`in the appended claims. The invention itself, both as to
`its organization and method of operation , together with
`further objects and advantages thereof may best be
`understood by reference to the following description
`taken in connection with the accompanying drawings
`in which:
`FIG. 1 shows a block diagram of imaging apparatus in
`accordance with the present invention.
`
`65
`
`FIG. 2 is a block diagram of the charge storage and
`readout apparatus of FIG. 1.
`.
`FIG. 3 is a graph of integrated stored charge in the
`charge storage and readout apparatus in response to a
`pattern of radiation incident on the apparatus.
`FIG. 4 is a sectional view of a charge storage device
`of the apparatus of FIG. 2, showing two potential well
`diagrams useful in explaining the operation of the de-
`vice.
`
`FIG. 5 shows a sectional view of another charge stor-
`age device which can be used in the apparatus of FIG.
`2.
`‘
`FIG. 6 is a sectional view of still another charge stor-
`age device which can be used in the apparatus of FIG.
`2.
`
`in explaining the
`FIG. 7 shows three tables useful
`operation of the present invention. Table I shows a
`Hadamard matrix of the fourth order. Table 2 repre-
`sents four equations each including the same indepen-
`dent variables which are algebraically summed accord-
`ing to the code represented by a respective row of the
`matrix of Table 1. Each ofthe variables represents a
`signal corresponding to the charge stored in a respec-
`tive device of the apparatus of FIG. 2. Table 3 shows
`four equations in which the independent variables are
`the four sums of Table 2. The independent variables
`are summed in accordance with the Hadamard matrix
`
`of Table l to obtain four sums each proportional to a
`respective one of the independent variables of Table 2.
`FIG. 8 shows a plan view of imaging apparatus utiliz-
`ing "a two dimensional array of charge storage devices
`in accordancelwith the present invention.
`FIG. 9 shows imaging apparatus utilizing a linear
`array of imaging devices in accordance with the present
`invention.
`FIG. 10 is a sectional view of the device of FIG. 9
`taken along section lines 10-10 of FIG. 9.
`FIG. 11 is a sectional view of the imaging device of
`FIG. 9 taken along section lines 11-11 of FIG. 9.
`FIG. 12 shows a sectional View of the device of FIG.
`9 similar to the sectional view of FIG. 10 and also in-
`
`cludes a diagram of semiconductor surface potential
`versus distance along the semiconductor surface under-
`lying the electrodes of the device useful in explaining
`one mode of operation of the device in accordance
`with the present invention.
`_
`FIGS.
`l3A—l3I are diagrams of voltage waveforms
`useful in explaining the operation of the imaging appa-
`ratus of FIG. 9 of the present invention.
`FIG. 14 is a diagram of voltage versus time of the
`summation} signals of FIG. 13H reconstructed into a
`video signal by transformation of the summation sig-
`nals.
`
`FIG. 15 shows a plan view of a portion of a large two
`dimensional array utilizing devices similar to the de-
`vices of the linear array of the apparatus of FIG. 9.
`FIG. 16 is a sectional view of the apparatus of FIG.
`15 taken along the section lines l6—— 16 of FIG. 15.
`FIG. 17 is a sectional view of the apparatus of FIG.
`15 taken along section lines 17-17 of FIG. 15.
`FIG. 18 shows a plan view of a portion of another
`embodiment of imaging apparatus in accordance with
`the present invention.
`FIG. 19 is a sectional view of the apparatus of FIG.
`18 taken along section lines 19——l9 of FIG. 18.
`FIG. 20 is a sectional View of the apparatus of FIG.
`18 taken along section lines 20-20 of FIG. 20.
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`tion site underlying electrode 24a and back again by
`control of the relative potentials on the two electrodes.
`The charge in a device may be repeatedly transferred
`between sites in the device without commingling the
`charge. with charge in other devices of the apparatus.
`FIG. 4 shows a sectional view of the device 15 and
`also shows a potential well 25 with portion 25b thereof
`underlying the storage electrode 22 being deeper than
`the portion 25a thereof underlying the summation elec-
`trode 25a, as a larger negative voltage is applied to the
`storage electrode 22 than to the summation electrode
`24a. Charge 26 is shown as stored in the storage site
`underlying the storage electrode. The arrow indicates
`that with the potential well underlying the storage elec-
`trode deeper than the potential well underlying the
`summation electrode, charge would flow from a stor-
`age site underlying the summation electrode to the site
`underlying the storage electrode. FIG. 4 also shows
`another potential well 28 in which the potential on the
`storage electrode 22 has been reduced in absolute mag-
`nitude and the potential on the summation electrode
`24a has remained fixed. Thus, any charge stored in the
`potential well or storage site underlying the storage
`electrode 22 now flows into the potential well or stor-
`age site underlying the summation electrode 24a as
`indicated by the arrow. Accordingly, by switching the
`potential of the storage electrode'22 above and below
`the potential of the summation electrode 24a charge
`may be transferred into and out of the storage site
`underlying the summation electrode 24a.
`Each of the storage electrodes 22 of FIG. 2 are con-
`nected to a respective one of the terminals of the stor-
`age electrode selector circuit 30 which is controlled by
`the clock pulse generator 31 and which provides the
`bias voltage for establishing the storage sites underlying
`the electrodes 22 and for providing the potentials on
`the electrodes 22 for the selective transfer of charge
`from the storage sites underlying electrode 22 to a
`coupled storage site underlying a corresponding sum-
`mation electrode 24a and back again. The common
`summation line 24 connects all of the summation elec-
`trodes 24a of the devices together and to a charge
`sensing circuit 32. The charge sensing circuit 32 pro-
`vides an output proportional to the difference in the
`sum of the charges transferred from the storage sites
`underlying the storage electrodes 22 to the storage sites
`underlying the summation electrodes 24a and the-sum
`of the charges transferred from the storage sites under-
`lying the summation electrodes to the storage sites
`underlying the storage electrodes, i.e., an output pro-
`portional to the net transfer of charge in the sites un-
`derlying the summation line 24. The charge sensing
`circuit 32 includes a high gain differential amplifier 33
`having an inverting terminal 34, a non-inverting termi-
`nal 35, and an output terminal 36. A change in voltage
`at the inverting terminal in one direction in relation to
`a reference potential produces a change in voltage at
`the output tenninal in the opposite direction in relation
`to the reference potential. A change in voltage at the
`non-inverting terminal in one direction in relation to a
`reference potential produces a change in voltage at the
`output terminal in the same direction in relation to the
`‘reference potential. The inverting terminal 34 is con-
`nected to the summation line 24, the non-inverting
`terminal 35 is connected to the negative terminal of a
`bias source 37, the positive terminal of which is con-
`-nected to ground. A feedbackicapacitor C“; is con-
`nected between the output tenninal 36 and the invert-
`
`3
`1 and 2 which shows
`Reference is made to FIGS.
`image sensing apparatus 10 including means for provid-
`ing a spatial pattern of radiation 13, means for providig
`a corresponding pattern of charge 11 and a charge
`collection, storage and readout apparatus 12 in accor-
`dance with the present invention. The spatial pattern of
`charge 11 is produced by the action of the radiation 13
`focused onto the apparatus 10. The source of the spa-
`tial pattern of radiation 12 may, for example, be the
`radiation from an illuminated object imaged onto the
`image sensing apparatus 10 by means of a lens system.
`The spatial pattern of radiation 13 produces a corre-
`sponding pattern of charge 11 which is collected and
`stored in the charge collection, storage and readout
`apparatus 12.
`The charge storage and readout apparatus 12 in-
`cludes a plurality of charge storage and summation
`devices 15, only four of which are shown for reasons of
`simplicity in describing the structure and explaining the
`operation thereof‘. The devices 15 are formed on a 20
`common substrate 16 of, for example, N-type conduc-
`tivity silicon of suitable resistivity and having a major
`surface 17. A layer of thick insulation 18 which may
`conveniently be silicon dioxide is provided overlying
`the major surface 17 (FIG. 4) of the substrate. A plu-
`rality of generally rectangular recesses 19 are provided
`in the thick insulating member 18, each corresponding
`to the location of a respective image sensing device 15.
`Each of the recesses 19 extends to within a short dis-
`tance of the major surface of the semiconductor sub-
`strate to provide a region 21 of thin insulation lying
`thereover. A plurality of storage electrodes 22 are pro-
`vided, each in a respective recess 19. Preferably the
`electrodes 22 are transparent to radiation in order to
`pennit incident radiation to be transmitted to the sub-
`strate. Radiation may also be imaged onto the substrate
`from the rear surface thereof. Also overlying the thick
`and thin portions of the insulator member 18 and ex-
`tending generally perpendicular to the long dimension
`of the recesses is a conductive member or a storage line
`24. The portions of the the storage line lying in the
`recesses 19 constitutes a plurality of summation elec-
`trodes 24a, each forming a part of a respective imaging
`device 15. Each of the summation electrodes 24a is
`adjacent a respective one of the charge storage elec-
`trodes 22.
`‘
`The application of suitable potentials to the storage
`electrodes 22 and to the summation electrodes 24a, for
`example, in the case of an N-type semiconductor sub-
`strate, the application of negative potentials of appro-
`priate magnitudes to these electrodes with respect to
`the substrate 16, will produce depletion regions under-
`lying the electrodes in which minority carriers gener-
`ated in response to incident radiation are stored. The
`generated charge is dependent on the intensity of the
`incident radiation and on the duration thereof. FIG. 3
`shows a graph of arbitrary values of integrated stored
`charge for the four devices of the apparatus 12 and
`represents a pattern of charge produced in the appara-
`tus in response to an arbitrary pattern of radiation
`incident on the apparatus. The charge storage elec-
`trode 22 and the summation electrode 24a of each of
`the devices are closely coupled so that the depletion
`regions or potential wells formed under the electrodes
`in the semiconductor substrate are also closely coupled
`and that charge may not only be stored in each of the
`depletion regions or sites but may be transferred from
`a storage site underlying an electrode 22 to a summa-
`
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`ing terminal 34 of the high gain differential amplifier.
`The feedback capacitor C H; is shunted by a reset switch
`38 in the form of a MOSFET transistor, the gate of
`which is driven by the integrator reset circuit 39 which
`is controlled by the clock pulse generator 31. As the
`potential of the inverting terminal 34 follows the poten-
`tial of the non-inverting terminal 35 of high gain differ-
`ential amplifier, when the reset switch is closed, voltage
`on the inverting terminal 34 and hence the summation
`line is the same as on the non—inverting terminal 35.
`The potential of the source 37 thus sets the potential of
`the bottom of the potential well of each of the storage
`sites underlying the summation electrodes 24a. To
`obtain a signal proportional to the sum of the charges in
`selected sites underlying the storage electrodes 22, the
`reset switch 38 is initially closed to set the potential of
`the storage sites underlying the summation electrodes
`24a to a reference value. The reset switch 38 is then
`
`10
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`15
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`opened and the storage electrodes 22 overlying the
`selected sites which are selected for summation are
`raised in potential to effect the transfer of charge in
`those sites to corresponding summation sites. This
`transfer of charge from storage sites to coupled summa-
`tion sites causes an opposing charge to be induced on
`the summation line 24 which is proportional to the
`transferred charge. This induced charge is in response
`to amplifier action in which the feedback capacitance
`C“; functions to drive the inverting terminal 34 of the
`amplifier 33 to maintain zero difference in voltage
`between its potential and the potential of the non-
`inverting terminal 35 connected to the source 35. The
`change in output voltage appearing at the output tenni-
`nal 36 of the differential amplifier is equal to the charge
`delivered to the summation line 24 divided by the feed-
`back capacitance C”. Accordingly, the voltage devel-
`oped across the feedback capacitor C“; and hence at
`the output terminal 36 of the differential amplifier is
`proportional to the sum of the charges stored in the
`selected storage sites and transferred to the coupled
`summation sites underlying the summation electrode.
`The algebraic summation (i.e. a summation with a
`pattern or code of both plus and minus signs) of the
`charge stored in the storage sites underlying the elec-
`trodes may also be obtained in the apparatus of FIG. 2.
`To achieve this result the charges to be summed with
`positive sign are stored in the storage sites underlying
`the storage electrodes 22. The charges to be summed
`with negative sign are transferred to the storage sites
`underlying the summation electrodes 24a by raising the 50
`electrode potential on the coupled storage electrodes.
`After resetting the summation line to the potential of
`source 37 by the reset circuit as described above the
`charges stored under the storage electrodes 22 and to
`be summed with a positive sign are transferred to the
`storage sites underlying the summation electrodes 24a
`by raising the potential on the corresponding storage
`electrodes. Simultaneously, the charges stored under
`the summation electrodes 24a and to be summed with
`a negative sign are transferred to the storage sites un-
`derlying the storage electrodes 22 by lowering the po-
`tential on the corresponding storage electrodes. Ac-
`cordingly, a net charge is induced on the summation
`line and an output voltage appears on terminal 36
`which represents the algebraic sum of the charges
`stored in the devices. Charge sensing in the manner
`described above is also described and claimed in co-
`pending application Ser. No. 591,636, filed June 30,
`
`1975, and assigned to the assignee of the present inven-
`tion.
`
`The operation of the apparatus of FIG. 2 will be
`described with reference to Tables 1-3 of FIG. 7. Table
`1 shows a Hadamard matrix of the fourth order having
`four rows designated A, B, C and D and having four
`columns designated 1, 2, 3 and 4. Table 2 shows four
`equations in which the independent variables are sig-
`nals E1 thru E4 corresponding to charge stored in de-
`vices 1 thru 4, respectively, of the apparatus of FIG. 2.
`The sums EA, 23, EC and ED represent, respectively,
`algebraic sums of the signals Elthru E4 in accordance
`with the signsset forth in the respective rows A through
`D of Table -1. In accordance with the present invention
`the summation signals 2,, thru Spare obtained at the
`output of the apparatus of FIG. 2 by the application of
`control voltages from the storage electrode selector 30
`to the storage electrodes of the four devices 15.
`To obtain the sum EA, initially charge in all of the
`devices is stored in the storage sites underlying elec-
`trodes 22. Next, the potential on the summation line is
`set to the potential of the source 37 by action of the
`reset switch 38 in resetting the amplifier 33. Charge is
`then transferred from all of the storage sites underlying
`electrodes 22 to the summation sites underlying all of
`the electrodes 24a by raising the potential of storage
`electrodes in relation to the summation electrodes. The
`output appearing at terminal 36 of the differential am-
`plifier is a signal 2,, proportional to the sum of trans-
`ferred charge. To obtain the sum 23,
`initially the
`charge in the first and second devices and to be
`summed with positive sign is stored in the storage sites
`underlying storage electrodes 22 thereof. The charge in
`the third and fourth devices and to be summed with
`
`negative sign is stored in the summation sites underly-
`ing summation electrodes 24a thereof. After resetting
`the amplifier 33 and the potential on the summation
`line by action of the reset switch 38, charge is trans-
`ferred from the storage sites to the summation sites of
`first and second devices by raising the potential of the
`storage electrodes thereof and simultaneously charge is
`transferred from the summation sites to the storage
`sites of the third and fourth devices by lowering the
`potential of the storage electrodes thereof. Thus, the
`output appearing at terminal 36 of the differential am-
`plifier is a signal 23 proportional to the net sum of
`transferred charge. The sum EC is obtained by initially
`storing the charge in the first and fourth devices in the
`storage sites thereof and storing the charge in the sec-
`ond and third devices in the summation sites thereof,
`and then effecting a simultaneous transfer of charge in
`the devices, as explained above, to obtain the output
`signal EC. Finally, the sum 2,, is obtained by initially
`stonng the charge in the first and third devices in the
`storage sites thereof and storing the charge in the sec-
`ond and fourth devices in the summation sites thereof
`and then effecting a simultaneous transfer of charge in
`the devices to obtain the output signal ED. If it is as-
`. sumed that the relative magnitude of charges stored in
`devices 1 through 4 and hence E1 through E4, are re-
`spectively 1,3,2 and 4 as shown in FIG. 3 the sum sig-
`nals EA, 2;, EC, and 2,, are respectively 10, -2, 0, and
`-4. Substituting these values in the equations of Table
`3 recovers the values of E1 through E4.
`The summation signals obtained from the apparatus
`could be utilized directly for such applications as pat-
`tern recognition and bandwidth compression. If de-
`sired, the summation signals could be reconstructed by
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`a signal reconstruction circuit 40 into signals represent-
`ing the charge stored in each of the devices of the
`apparatus. This reconstruction is accomplished . by
`transforming the four equations of Table 2 into the four
`equations of Table 3 in which each of the tenns E., E2,
`E3 and E4 is expressed as a respective algebraic sum of
`the terms 2,4, 23, EC and 20. The summation set forth in
`Table 3 could be obtained by any apparatus which is
`capable of performing the algebraic summations set
`forth in Table 3 of FIG. 7. Signal reconstruction circuit
`40 of FIG. 2 connected to the output of charge sensing
`circuit 32 is such apparatus. A particular advantage of
`simultaneously reading out a summation signal from a
`plurality of devices in accordance with the present
`invention is that the signal to noise ratio of the output
`is enhanced over individual device readout by a factor
`dependent on the number of devices simultaneously
`read out as is apparent from the equation of Table 3.
`The apparatus of FIG. 2 may be operated in a mode
`in which radiation is continuously received and stored
`by the devices 15 of the apparatus. The time for per-
`forming the algebraic summations of the charges stored
`in the devices and obtaining readout is relatively short
`compared to the integration time during which charge
`is being generated and stored in the devices and the
`charge stored in the devices does not change signifi-
`cantly during the readout time. In another mode of
`operation integration of the generated charge would
`take place over a period of time after which radiation
`would be blocked from the devices and readout would
`occur. After readout had taken place, charge would be
`removed by any of a variety of means, for example, by
`raising the potentials of the charge electrodes and the
`summation electrodes to substrate potential to inject
`the stored charge into the substrate and thereafter
`dropping the potential of these electrodes to appropri-
`ate values for storage of radiation generated charge for
`the next cycle of operation of the apparatus.
`Reference is made to FIG. 5 which shows a cross—sec-
`tional view of a single device 42 suitable for substitu-
`tion for the device 15 of FIG. 2. The device of FIG. 5
`is identical to the device shown in FIG. 4 except that
`each of the summation electrodes 43a insulatingly
`overlaps a respective storage electrode 22 to provide
`close coupling between the depletion regions thereof.
`Reference is made to FIG. 6 which shows a sectional
`view of another storage device,45 which may be substi-
`tuted for the storage device 15 of FIG. 2. The device 45 .
`of FIG. 6 is identical to the device of FIG. 4 except that
`the storage electrode and the summation electrode are
`spaced apart and transfer electrode 46 is provided to
`control the transfer of charge between the storage and
`summation sites thereunder. FIG. 6 also shows poten-
`tial wells 47 and 48 produced by the application of
`operating potentials to the electrodes of the device 45.
`In potential well 47 charge is shown as having been
`transferred from the portion 47a of the potential well
`underlying the summation electrode 24a to the portion
`4717 of the potential well underlying the storage elec-
`trode 22 with the potential applied to the transfer elec-
`trode 46 producing a surface potential in the barrier
`region 49 between the summation site and the storge
`site lower than the potential of the bottom of the poten-
`tial well under the summation electrode 24a. In poten-
`tial well 48 charge is shown as having been transferred
`from the portion 48b of the potential well underlying
`the storage electrode to the portion 48a underlying the
`summation electrode 24a with the potential applied to
`
`5
`
`20
`
`30
`
`35
`
`55
`
`60
`
`8
`the transfer electrode 46 producing a surface potential
`491: in the barrier region 49 lower than the potential of
`the bottom of the potential well underlying the storage
`electrode 48b. Thus, by switching both the storage
`electrode and the transfer electrode potentials of the
`device above and below the potential of the summation
`electrode, charge may be transferred into and out of
`the storage site underlying the summation electrode.
`Use of the transfer gate electrode allows an additional
`control on the timing of the transfer of charge into and
`out of the summation storage site.
`While the boundaries between the thick and thin
`insulation portions of the apparatus of FIGS. 2-6 has
`been shown as defining boundary edges of the various
`charge storage sites, it is apparent that such boundary
`edges may be provided by regions in the substrate of
`the same conductivity type as the semiconductor sub-
`strate, but of greater conductivity. These regions may
`be formed by such means as ion implantation or diffu-
`sion and are commonly referred to in the art as channel
`stops.
`Reference is now made to FIG. 8 which shows appa-
`ratus 52 in accordance with the present invention uti-
`lizing a two—dimensional array 53 of devices 15 in
`which plurality of linear arrays of devices 15 such as
`shown in FIG. 2 are arranged on a common semicon-
`ductor substrate into a plurality of rows with like num-
`bered or positioned devices 15 of a row lying in a col-
`umn. The summation lines of the rows of devices are
`
`designated X,—X.. Storage electrodes of the devices
`lying in a column are connected to a respective one of
`the column lines Y,—Y4. Each of the column lines
`Y,—Y., are connected to respective terminal point on a
`column selector 54, functionally identical to the stor-
`age electrode selector of FIG. 2. A row selector 55 is
`provided having input
`terminals connected to rows
`lines X,—-X4, respectively. The row selector 55 synchro-
`nized with the clock pulse generator 56 enables selec-
`tive connection of the row lines to the signal processor
`57 which includes circuits such as sensing circuit 32 of
`FIG. 2. Each of the row lines X,—X., may be connected
`under operation of the row selector 55 to the signal
`processor 57 in sequence or simultaneously, as desired,
`depending upon the nature and the order of summation
`of signals representing algebraic sums of the charges in
`each of the rows of devices is desired. Both the column
`selector 54 and the signal processor 57 are under the
`control of the clock pulse generator 56. Operation of
`the system of FIG. 8 will be explained in connection
`with the Tables of FIG. 7. The apparatus 52 may be
`operated in any one of three modes for obtaining l-Iada-
`mard transfonns of the charge stored in each of the
`rows of devices in accordance with the code of Table 1.
`
`In one mode of operation the sum of the charges stored
`in the first row of devices in accordance with the code
`of row A of Table l is obtained by connecting row line
`X,
`to signal processor 57 and applying appropriate
`transfer signals to outputs 1, 2, 3 and 4 of the column
`selector 54, as explained above in connection with the
`apparatus of FIG. 2. Thereafter the same summation is
`similarly obtained for rows 2-4 by connecting in se-
`quence row lines X2, X3 and X4 to the signal processor
`and applying appropriate transfer signals to the column
`_lines Y1—Y4. Thereafter the summation indicated in row
`B of Table 1 is performed for each row of devices. This
`is followed by the summation of rows C and D of Table
`l for each of the rows of devices. The signal processor
`57 assembles the information into four complete sets of
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`one-dimensional Hadamard transforms of rows of de-
`vices. The complete Hadamard transform f