EXHIBIT 1030
`
`U.S. PATENT NO. 3,949,162 TO MALUEG
`
`(“MALUEG”)
`
`
`
`
`
`TRW Automotive U.S. LLC: EXHIBIT 1030
`PETITION FOR INTER PARTES REVIEW
`OF U.S. PATENT NUMBER 8,599,001
`IPR2015-00436
`
`

`
`United States Patent
`
`1191
`
`Malueg
`
`[54] DETECTOR ARRAY FIXED-PATTERN
`NOISE COMPENSATION
`
`[75]
`
`Inventor: Richard M. Malueg, Glendora,
`Calif.
`
`[73] Assignee: Actron Industries, Inc., Monrovia, _
`Calif..
`
`[22] Filed:
`
`Feb. 25, 1974
`
`[21] Appl. No.: 445,802
`
`[52] U.S. C1.......................... .. 178/7.1; 178/DIG. 12
`[51]
`Int. Cl.2 ..................... .. H04N 5/30; H04N 5/21
`[58] Field of Search .............. .. 178/7.1, 7.2, DIG. 12
`
`[5 6]
`
`3,584,146
`3,629,499
`3,790,705
`3,800,079
`3,814,847
`
`References Cited
`UNITED STATES PATENTS
`
`Catt et al. .......................... .. 178/7.1
`6/1971
`Carlson ...................... .. 178/DIG. 12
`12/1971
`2/1974 Kamin ..................... .. 178/7.1
`3/1974 McNei1et al
`178/7.1
`6/1974
`Longuet ............................. .. 178/7.1
`
`[11]
`
`3,949,162
`
`1451 Apr. 6, 1976
`
`3,830,972
`
`8/1974
`
`Slverling et al. ................... .. 178/7.1
`
`Primary Examiner—Robert L. Richardson
`Attorney, Agent, or Firm——Marvin H. Kleinberg
`
`[57]
`
`ABSTRACT
`
`Fixed pattern noise compensation is provided for an
`array of detectors by premeasuring output signals of
`the detectors under a low (preferably at virtually abso-
`lute zero) level of uniform incident energy, converting
`the measured signal level of each detector to digital
`signals, and storing the digital signals in a memory for
`reading out in synchronism with scanning outputs of
`the detectors during normal system operation. The
`digital compensation signals are converted to analog
`form and subtracted from the output signals of the re-
`spective detectors during each successive scan cycle
`of the system operation. To eliminate error from ran-
`dom noise, several noise measurements may be aver-
`aged to produce the fixed pattern noise compensation
`signals.
`'
`
`14 Claims, 6 Drawing Figures
`
`REMOVABLE CAP
`OPTICAL
`SCAN
`
`29
`
`SAMPLE
`
`.
`
`SIGNAL
`GENERATOR
`
`DISPLAY
`AND OR
`RECORD
`
`1030-001
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`1030-001
`
`

`
`US. Patent
`
`April 6, 1976
`
`Sheet 1 of 3
`
`3,949,162
`
`REMOVABLE
`
`CAP
`
`PICAL SCAN
`SYSTEM
`
`:'
`§
`
`MEMORY SHIFT REGISTER CLOCK
`
`sHn=1'
`
`:
`
`REGISTER‘
`
`MEMORY j:
`
`"'
`
`,
`
`SIGNAL
`
`I GENERATOR
`
`1030-002
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`1030-002
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`

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`U.S. Patent
`
`April 6, 1976
`
`Sheet 2 of3
`
`3,949,162
`
`A.
`
`A‘ ARRAY CLOCK __
`(START A/D
`;
`CONVERSION
`I
`e. RESET INTEG.
`
`WT
`
`I I
`
`B~ CHARGE AMP
`
`OUTPUT
`
`I
`
`I I I I
`
`: I
`
`0-
`
`INTEGRATOR
`OUTPUT
`
`»
`
`D-
`
`SAMPLE &———\
`HOLD OUTPUT
`
`E. MEMORY SHIFT
`REG. CLOCK
`(LOAD MEMORY )
`
`r-
`
`sA~n=Le J
`
`HOLD
`
`PERIOD
`
`FIG. 3..
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`1030-003
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`1030-003
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`

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`U.S. Patent
`
`April 6, 1976
`
`Sheet 3 of 3
`
`3,949,162
`
`BIT
`4
`COUNTER
`
`I
`
`V
`
`FIG. 5a.
`
`UNCOMPENSATED
`OUTPUTS
`
`COMPENSATED
`
`OUTPUTS
`
`ILLUMINATION
`
`UNCOMPENSATED
`
`%' OUTPUTS
`
`FIG. 5b.
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`COMPENSATED
`OUTPUTS
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`ILLUMINATION
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`1030-004
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`I-
`..
`I'-
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`D0
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`DO OI
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`JJ
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`O >
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`VIDEOOUTPUT
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`1030-004
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`

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`3,949,162
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`1
`
`DETECTOR ARRAYFIXED-PATTERN NOISE
`COMPENSATION T
`v
`
`BACKGROUNDOF THE INVENTION
`
`This invention relates .to detector array systems and
`more particularly to an array of detectors which tends
`to have a fixed pattern noise -in additionto random
`noise associated with signal outputs from the detectors.
`There is an ever-increasing interest . in solid-state
`imaging systems. These solid-state systemseliminate
`the need for a target electrode in conventional vidicon
`tubes, thus -increasing basic resolution and speed capa-
`bility. Upon being exposed to alight image, the typical
`photodetector collects the released photocharge in. a 15
`p-n junction capacitance. The charge pattern can be
`read out without a scanning electron. beam. Advantages.
`are higher geometric accuracy,.high sensitivity, higher
`scan rates, small size, low voltage, low power and solid-
`state ruggedness and reliability. Electronic circuits
`needed to scan the array can be formed on the silicon
`wafer. while the array of p-n junction photodetectors is
`being formed using the most advanced integrated cir-
`cuit technology. Such arrays are commercially avail-
`able in both linear and rectangular configurations-
`A typical, array consists of p-n-junction vdiodes pro-
`duced in a silicon wafer as an integrated circuit with a
`quartz window.. Each diode has inherent capacitance
`and an area which varies by as much as five percent, or
`more, from diode to diode. Each diode is connected to
`an output video line by an access switch, made from an
`MOS field-effect transistor. A shift register is provided
`to sequentially tum.on the access switches. In the case
`of a rectangular array, a second shift register can be
`employed to switch the output of thefirst shift register
`from one row of access switches to‘ the next as the array
`is scanned row by row.
`~
`.
`.
`.
`.
`X
`*
`v
`As eachaccess switch: is turned on,.the inherent ca-
`pacitance of its associated diode is recharged back to-
`the video. output
`line’ potential,
`thus replacing the
`charge displaced by the photocharge. The replaced
`charge is amplified by a. charge (trans-impedance)
`amplifier. Once the addressing switch. is again turned
`off, the diode capacitance will begin to discharge due
`to further photocurrent. The amount of discharge is
`proportional to the intensity of the light impinging the
`diode during the entire period before the access switch
`is again tumed_ on. The resulting signal» at the video
`output is a.train of pulses, each pulse having an ampli-
`tude proportional to the integrated light flux impinging
`the diode.
`:
`~
`..
`-
`.
`.
`=
`—
`
`The recording and/ordisplay of the video output is
`conventional for such discrete sampling systems. Typi-
`cally, a sarnple—an,d-hold circuit is employed to hold the
`amplitude of each pulse in successionto provide conti-
`nuity from pulse to pulse. In practice, it is. desirable to
`provide an integrator between the charge amplifier and
`the sample-and-hold circuit, and. to then quantize the
`sample for digital control of the recording or display
`device.
`’
`.
`.
`..
`-
`,
`-
`Pulses driving the linear-array addressing register are
`used to synchronize the recording or display device. In
`the case of a rectangular array, the output.-of a second
`register may be employed to synchronize the display or
`recording of successive rows. When all the rows have
`been displayed side by side, the entirecycle is repeated.
`To provide for an area image with a linear array, the
`optics focusing the image onto the array are turned at
`
`2
`just the proper rate to match up successive lineirnages.
`This basic drive relationship is then used to generate
`signals for a display device, such as a cathode-ray tube
`or further to generate a speed command for a film
`recording system.
`,
`It has been found thus far thatsuch solid-state imag-
`ing systems produce an image which is just comparable
`to conventional vidicon tubes. The reason is that the
`
`area under each video pulse is indicative of the amount
`of integrated photocurrent augmented by the random
`noise present in the. diode and the clock noise intro-
`duced by switching the access switch on.
`‘
`"The switching noise is the most serious contributing
`factor to distortion of the video output because the
`MOS transistor has associated with it junction capaci-
`tance between the gate and source electrodes. Such
`capacitance will couple a subsstantial’ charge from the
`switching control signal
`into the video output line.
`Other switching devices,'such as junction transistors,
`could have an even greater problem. There are circuit
`techniques which may be employed. to decrease this
`error, .but such techniques will only provide a first
`order correction.,That is because_such techniques rely,
`on introducing a compensating cha_rge,—but the junction
`capacitance is not the same for every switch and diode
`combination so there will be some residual error-in the.
`compensation of most diodes. The combined effects of
`variations in the (1) switch capacitance and‘(2) clock
`noise of the diodesin the array present a fixed pattern
`noise problem.
`-»
`SUMMARY OF THE INVENTION
`In-accordance with the present invention, a detector
`array is provided with conventional means for sequen-
`tially switching discrete detectors to an outputterminal
`in a fixed patteml The" fixed pattern noise inherent in
`the combination of the array and theswitching means is
`compensated by ‘first operating the switching means "to
`scan the array through one fixed pattern cycle, and
`measuring the output signal derived from each detector
`under a low, uniformjlevel of incident energy,‘ and
`preferably with" no energy incident on the detectors.
`‘ This may be done by simply capping the ‘system em-
`ployed to focus the ‘energy onto the array while switch-
`ing all detectors of the array ‘to an output terminal‘ in
`sequence during one raster cycle. The noise «signals,
`thus sampled from successive detectors are converted
`to digital fonn and stored in a fixed pattern of digital
`memory means. "To eliminate error from random noise,
`a‘ number of noise measurements may be made and
`averaged to produce the fixed noise pattern compensa-
`tion signals. During normal system operation, the cap is
`removed and asthe array is continually scanned in the
`fixed pattern, the corresponding digital noise signal of
`each detector is read from memory, converted to ana-
`log form and subtracted from the output signal then
`being derived from the detector.
`While an exemplary embodiment will be described
`with reference to an array of photodetectors, and spe-
`cifically an array of p-n junction diodes, it is recognized
`that the same problem is experienced with other types
`of detectors, such as particle detectors, sonic detectors,
`radiation detectors, and the like. Hence,
`the novel
`features that are considered characteristic of this in-
`vention will be set forth with particularity in the ap-
`pended claims.
`.
`~
`
`1030-005
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`1030-005
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`

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`3
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`3,949,162
`
`VBHRIEF DESCRIPTION or THE DRAWINGS
`FIG. 1 is a block diagram illustrating the principlesof
`the present invention in a-linear array photodiode im-
`aging system.
`FIG. .2 is a system timing diagram helpful.in under-
`standing the generalorganization of an exemplary em-
`bodiment.
`-
`,
`’
`.
`j
`.
`_
`,
`FIG. 3 is, a timing diagramtof the main video signal
`channel of the photodiode imaging system of FIG. 1;
`FIG. 4 is a block diagram of a system for obtaining a
`plurality of dark-noise signal measurements and storing
`an average of the measurements fortfixed-pattern com-
`pensation.
`»
`'
`'
`'
`'
`FIGS. 5a and 5b are graphs of video output as a func-
`tionof illumination intensity for a pair of photodiodes
`before and after fixed-pattern noise _compensation.
`7
`‘DESCRIPTION OF ‘THE PREFERRED
`.
`.
`: EMBODIMENTS .
`V
`—‘
`
`.
`
`5
`
`15
`
`Referring "to" the drawings, an imaging‘ system em-
`bodying the present ‘invention is illustrated in FIG. 1.
`The system _i'nclu'des a‘ linear‘ array 10 of photodetec-
`tors; which are shown by way of e'x‘am'p'le‘and not by
`way of limitation to be p-n junction diodes, D,’ through
`DN'and an optical scanning system’ 11 for focusing;a
`light image in the plane of the array and deflecting the
`focused “image ‘over the array. This’ optical‘s'<j:anning
`system includes a-table whichrotates at a uniform-rate
`synchronized with‘ the scanning cycles of the array.
`A linear array has been selected to illustrate the prin-
`ciples of the presentjnvention because, as will become
`apparent from the following description, the principles
`"are fully-demonstrated with just a linear array. Those
`principles are directly applicable to.a rectangular array
`since in bothscases the-xtrain of video.~pulses on a com-
`mon: output linevare derived from diodes.repeatedly
`scanned in a fixed-pattem.
`--
`.
`~
`.
`.~ In- series with, each photodiode D, through DN is.an
`MOS-type field-effect transistor having its drain con-
`nected to the anode of the diode and its source con-
`nected to a common video output line 12. That line is
`connected to the summing junction 13 of a transimped-.
`an_ce (charge,..or current) amplifier comprised_ of an
`opera_tional_,amplifIer :14 having a feedback__ resistor
`Whenpower is first applied to the system and the first
`scan is performed; the diode junction capacitancesare,
`charg_ed‘.to +5V,by.the_amplifier 14, the su_m_ming’ju_nc-.
`tionof which is at virtual ground. Al,l_dio_d_es are thus‘
`expected_to_be initially, charged to +5V, cathode-to-
`anode, and each diode will begin to dischargein re-
`sponsettoy photocurrent from one scan cycle to the next,"
`i.e., the anode potential will begin to increase from
`ground ftoward +5V.
`,
`’
`-~
`~
`'.
`_‘_
`'
`_
`'
`A shift register 16 receives an initial ‘START pulse
`from a flip-flop in a timing signal generator 17 to set up",
`an input ‘bit '1' Vwhichis shifted into the first stage of the
`shift’ register by an array clock. The START and
`ARRAY CLOCK pulses are shown in waveforms Aand
`B of FIG. 2. The ARRAY CLOCK pulses are.'also
`shown in waveform A of FIG. 3. The trailing edges of
`the array clock pulses shift the one bit in the register 16
`through successive stages to turn the access (commu-
`tating) switches Q, through QN on in sequence during
`one lineariscan cycle.
`'
`"
`'_
`As I the diodes -are continually scanned,
`the video"
`output pulse of each diode will appear at the output of
`the amplifier 14 as shown in waveform B of FIG. 3. The
`
`4
`area under each negative video output pulse is propor-
`tionalpto the _intensity of ‘therlight on the diode during
`the last scan cycle; To obtain“a signal proportional in
`amplitude to the intensity of the light, the video pulses
`are integrated in an integrator comprised of an opera-
`tional amplifier 21 and feedback capacitor 22. The
`output of that integrator, shown in waveform C of FIG.
`3, is-then sampled at the end of the integration period
`and held-as shown in waveform D until the next mem-
`ory shift register clock pulse shown in waveform E of -
`FIG. 3.‘ Waveform F of FIG. 3 showsrthe SAMPLE
`pulse that is applied by the generator -17 to a sample-
`and-hold circuit 23. The ARRAY CLOCK pulses trans-
`mitted by the timing signal generator are also applied to
`the shift register 16 to advance the »video scan to the
`next diode and to a ‘transistor switch OR, to reset the
`integrator. . Consequently,
`immediately after each
`SAMPLE pulse,‘ the integrator is reset.»
`‘
`The output of the sample-and—h,old circuit is applied
`to the displayiand/or record system 20 through a sca-
`ling differential amplifier comprised of an operational
`amplifier 24 having a differential input stage and feed-
`back’ resistor 25. A fixed pattern noise compensation
`signal read from a shift register memory 26 is converted
`to analog form in a digital-to-analog (D/A)’ converter
`27 and subtracted from the video output signal by the
`differential amplifier 24. The preferred manner in
`which the fixed pattern noise is measured and stored in
`the memory 26 will now be described.
`_
`-
`‘
`Firsta cap 29 is placed over the optical scan lens
`system 11. That provides a uniform low level of illumi-
`nation for all diodes that is virtually at absolute zero.
`Then a switch 30 is placed in a calibrate position to set
`a-flip-flop,‘ RQ, in the timing signal generator 17. Re-
`calling that the'shift‘register 16 is‘ operating continu-
`ously after an initial START pulse (which in turn may
`be initiated by a start button being momentarily de-
`pressed once power is turned on)“ the purpose of this
`RQ flip-flop is to simply request a calibration scan
`cycle to begin with the next START pulse. Conse-
`quently, theRQ flip-flop is reset by the next START
`pulse. At the same timethe RQ flip-flop is reset, a
`calibrate flip-flop, CLB, is set by the.START pulse. The
`output signals RQ and "CLB of those ;‘~flip-flops"are
`shown in‘ waveforms C and D of FIG. 2.
`I
`*
`
`The signal CLB enables an analog-to-digital ‘con-
`verter 31 coupled to thesample-and-hold=circuit 23 by
`an operational amplifier 32 having a fixed gain set by‘
`the.ratio’ of a feedback resistor -33 to an input resistor
`34 to‘ scale the signal to the converter 31. as may be
`required. It also enables the shift register memory 26 to
`store the output of the converter»31—in successive mem-
`’ ory locations starting-with‘ the first merriory location
`and proceeding to successive memory locations’ in re-
`sponse to memory shift register clock pulses. That
`START'pulse for a calibration scan’ is, of course,’ the
`one thatsets the CLB flip-flop. The next'S'I_‘ART pulse
`resets the CLB flip-flopto terminate‘-th'e store"mode of
`operation for the memory 26. In that manner, the mem-
`‘ory 26 will ‘store the video output of each diode in
`digital form as the diodes are scanned once insequence
`from D. through=DN.
`'
`»
`’
`‘
`‘
`‘
`When «the CLB flip-flop-is reset, all-operation of the
`memory -26 is stoppeduntil another calibrate operation
`is ‘requested by’ operating the switch 30 to a STOP
`position andreturning it to the CAL position, or until
`theswitch 30'is placed in an operate (OP) position.
`Placing the switch 30 in" the OP position will also set the
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`3,949,162
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`5
`RQ flip-flop to enable the next START pulse to set an
`operate flip-flop, OPT. The OPT flip—flop remains set
`until manually reset, as by turning the switch 30 to the
`STOP position, but not until the next START pulse.
`The waveform for the CLB flip-flop is also used in FIG.
`2 to illustrate the output of the OPT flip-flop because it
`functions the same except for the way it is reset. How-
`ever, the output signal of the OPT flip-flop is used
`differently. It sets the memory 26 to a read mode of
`operation so that as its memory locations are continu-
`ally addressed in synchronism with successive scanning
`cycles of the diode array, the fixed pattern noise of
`each diode is read out once during each array scanning
`cycle.
`The digital-to-analog converter 27 automatically
`converts the digital output of each successive memory
`location to analog form for subtraction from the video
`output of the corresponding diode. In that regard, it
`should be noted from the timing waveforms of FIG. 3
`that the video output to the amplifier 24 from a given
`diode is not available until the memory shift register
`clock pulse occurs because the clock pulse period de-
`voted to that diode is used for integrating the video
`pulse from the charge amplifier 14. Consequently, op-
`eration of the memory 26 is delayed virtually one clock
`pulse.
`The actual read operation during an operate mode is
`timed by the SAMPLE pulse, but delayed for the pe-
`riod of the SAMPLE pulse less the inherent delay in the
`converter 27. In that manner fixed pattern noise signals
`are presented to the amplifier 24 in synchronism with
`video signals from the corresponding diodes via the
`sample-and-hold circuit 23. The necessary delay may
`be introduced by an adjustable monostable multivibra-
`tor at the read control input of the memory. The mem-
`ory is advanced by the memory shift register clock
`(waveform E of FIG. 3) so that the memory is ready in
`time to have a noise compensation value read out.
`During a calibrate mode of operation, i.e.,‘during a-
`write mode of operation for the memory, the write
`operation is delayed for a period of one clock time after
`a SAMPLE pulse, which is sufficient delay for a sample
`to be converted by the analog-to-digital converter 31.
`That converter begins operation when the array clock
`pulse occurs immediately following a SAMPLE pulse.
`The memory 26 employed in this exemplary embodi-
`ment consists of a conventional recirculating memory
`comprised of a plurality of N-stage shift registers, one
`shift register for each bit of the converter output, oper-
`ating in synchronism with the first N stages of the array
`shift register. In that case the recirculating memory
`operates in open loop during the calibrate mode of
`operation and in closed loop during the operate mode
`of operation. However,
`in other embodiments the
`memory may consist of a random access memory hav-
`ing memory locations addressed in sequence by an
`addressing shift register driven by the shift register
`clock pulses just as the shift register memory 26 is
`driven. In either case, the memory can be expanded for
`a rectangular array of diodes.
`To expand the memory 26 for a rectangular array,
`one possibility is to provide N independent memories,
`one for each row of the diode array, each having N
`memory locations, and providing a counter responsive
`to START pulses to count the number of lines scanned.
`The output of the line counter would then advance the
`read, or write, operation from one memory to the next.
`The output of that line counter would be transmitted to
`
`6
`the display and/or record system to advance the display
`and/or record control along from one line position to
`the next after each line scanned. One would also need
`
`an end-of-frame (EOF) pulse derived from the carry
`output of the line counter to synchronize the frames of
`the display and/or record system for repeated display,
`or to stop the entire scanning process in_ case the video
`display and/or record is for a single frame. In either
`case, display control
`in a direction normal
`to the
`scanned lines being displayed can be derived from the
`line counter.
`,
`In operation, the exemplary system of FIG. 1 is used
`as a still camera. The switch 30 is first placed in the
`CAL position. Then after sufficient time for calibration
`has been allowed (which could be indicated by_ a lamp
`energized by the CLB signal being extinguished), the
`system would be stopped by placing the switch 30 in
`the STOP position. That stops everything except for
`continuing to apply array clock pulses to the register
`16. Thereafter, upon moving the switch to the OP posi-
`tion, the taking of the picture is begun. The memory
`read operation would begin_with the next START pulse
`in a manner strictly analogous to the way calibration is
`started. For that reason the same, waveform is used_ in
`FIG. 2 for OPT as for CLB, as noted hereinbefore. The
`display and/or record system would then also begin
`with the next START pulse after the signal OPT. is
`applied to it. A linkage, or its electrical equivalent,
`returns the switch 30 to the STOP position once the full
`arc specified has been scanned by the optical scan
`system. The entire operation could then be repeated
`for another picture, with or without recalibration, tak-
`ing care to manually reset the lens system. If another
`picture is not taken for some time, it would be desirable
`to recalibrate.
`I
`Referring now to FIG. 4, a modification of the system
`of FIG. 1 will be described. The modification is for
`averaging a number of calibration scanning cycles in
`order to eliminate from the fixed pattern noise any
`random noise. An accumulator 40 is connected be-
`tween the output of the analog-to-digital converter 31
`and the memory 26 of FIG. 1. The output of the accu-
`mulator is connected to the memory through a bank of
`AND gates 41 which are enabled by the output of the
`last stage of a binary counter 42. Assuming that 16 scan
`cycles are to be averaged, the counter 42 is a 4-bit
`counter incremented by START pulses from the shift
`register 16. When 16 scan cycles have been completed,
`the counter 42 then sets a flip-flop FF which enables
`the AND gates 41 and disables a bank of AND gates 43
`that connect the input terminals of the accumulator 40
`to the analog-to-digital converter 31. After one addi-
`tional array scan cycle the flip-flop is reset via the AND
`gate 44 which transmits a stop calibrate signal (STOP ,
`CLB) to the timing signal generator 17 that turns off
`the calibrate signal CLB which enables the counter 42.
`The accumulator 40 is a conventional accumulator
`comprised of a plurality of recirculating registers oper-
`ating in parallel, one recirculating ‘register for each bit.
`Assuming 16 bits for the accumulator, there would be
`16 shift registers,» all of which recirculate in parallel
`through a parallel binary adder to-which the AND gates,
`43 are connected. Assuming the analog-to-digital con-
`verter is provided with a 12-bit output, the AND gates
`43 are connected to bit positions 2° through 2“ of the
`adder at the addend inputs of the accumulator. The
`remaining addend inputs are wired to provide bit zeros
`at positions 2” through.2‘5. The augend inputs to the
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`1'0
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`7
`adder are connected to the outputs of the shift registers
`at bit positions 2“ through 2”’.
`In response to each
`SAMPLE pulse, applied through a suitable delay multi-
`vibrator, the shift registers are advanced, thus entering
`accumulated sums of diode noise measurements in the
`recirculatingregisters until a carry output appears from
`the last stage of the counter 42. The gates 43 are then
`disabled and the gates 41 are enabled, as noted herein-
`before, duringthe next scan cycle to gate into the mem-
`ory the accumulated sums divided by l6 for storage as 10
`though that were the single calibration cycle of the
`system of FIG. 1. The next start pulse is then transmit-
`ted by the AND gate 44 as a STOP CLB signal to the
`timing signal generator 17 to stop the calibration mode
`of operation. The operate mode may then be initiated
`as before.
`
`The step of dividing by 16 is carried out automati-
`cally by taking the 12-bit output for storage in memory
`from the twelve most significant bit positions 24
`through 2”. If a larger number of samples is to be aver-
`aged, a larger accumulator and a larger counter would
`belprovided, and the outputs would still be taken from
`the 12 most significant bits. The only restriction on the
`number N of samples that may be averaged in this way
`is that N be some power of 2. Otherwise some more
`sophisticated system must be provided for adding and
`dividing by a number other than some power of 2.
`However, such more sophisticated systems are known,
`and if integrated circuit technology is used, such sys-
`tems are economically feasible as well.
`As indicated hereinbefore, the preferred way of mak-
`ing the ‘fixed pattern noise measurements is with the
`optical scan system capped. The measurement at each
`diode is then of what is commonly referred to as “dark
`noise”. As the dark noise of each diode is subtracted
`
`from its signal during normal operation for imaging, the
`video output of each diode has an amplitude that is a
`function of light intensity. A graph of that function with
`dark noise for two diodes D1 and D” is shown with solid
`lines in FIG. 5a. The corrected function, is then shown
`in dotted lines.
`
`This fixed pattern dark noise compensation assures
`that the video output function for every diode will pass
`through the origin. Each may have a slightly different
`slope, as shown, due to a difference in the sensitivities
`of the diodes, but that may also be compensated in
`accordance with the teachings of a copending applica-
`tion filed concurrently by Richard M. Malueg and Mi-
`chael .I. Meir, titled PHOTODIODE ARRAY GAIN
`COMPENSATION, and assigned to the assignee of this
`application.
`The fixed pattern noise measurement may also‘ be
`made at a selected low level I of illumination as illus-
`trated in FIG. 5b for the same diodes D, and DN. This is
`less desirable than making dark noise measurements
`because all output for the array below the level I is then
`masked by the noise compensation since the resulting
`video output would be negative, as shown, below the
`illumination level I. Also for all levels above the level I,
`the video output levels will be proportionately lower as
`may be readily appreciated by comparison of FIGS. 5a
`and 5b. However, for some applications that may be
`acceptable.
`‘Although particular embodiments of the invention
`have been described, it is recognized that other modifi-
`cations and variations may readily occur to those
`skilledin the art. In particular, it is recognized that the
`concept of the present invention is applicable to arrays
`
`8
`of detectors of all types, and not just to arrays of photo-
`detectors. Consequently, it is intended that the inven-
`tion be interpreted to include such and other modifica-
`tions and variations, and that its scope be determined in
`accordance with the following claims.
`What is claimed is:
`1. A method for fixed-pattern noise compensation of
`a system employing an arrayof detectors, said method
`comprising the steps of
`I
`measuring the output signal level of each detector
`under a’ uniformly low level of incident energy,
`storing the low-level signal value thus measured for
`each detector, and
`'
`during a subsequent normal system operation, sub-
`tracting the stored low-level signal of each detector
`from the signal output of the respective detectors
`each time the detectors are addressed.
`
`2. A method as defined in claim 1 wherein said signal
`level measurement of each detector made under a uni-
`formly low level of incident energy is an average of a
`plurality of signal level measurements made under the
`same condition of incident energy. '
`3. A method as defined in claim‘ 1 wherein said low
`
`level of incident energy is virtually atabsolute zero.
`4. A method as defined in claim 3 wherein said signal
`level measurement of each detector made under a uni-
`
`formly low level of incident energy is an average of a
`plurality of signal level measurements made under the
`same condition of incident energy.
`7
`5. A method as defined in claim 1 wherein said detec-
`tors are photodetectors and said incident energy is
`light.
`A
`6. A method as defined in claim 5 wherein said pho-
`todetectors are p-n junction diodes.
`7. Apparatus for compensation of fixed-pattern noise
`in a system employing an array of detectors, a system
`for focusing incident energy on said array, and switch-
`ing devices for sequentially connecting said detectors
`to a common array output junction, comprising
`means for producing an output signal for each detec-
`tor as each detector is connected to said common
`array output junction,
`means for providing a uniformly low level of incident
`energy to all detectors of said array,
`means for measuring the output signal of each detec-
`tor during a calibration operation of said array
`under said uniformly low level of incident energy,
`means for storing as a compensation value the output
`signal value thus measured for each detector, and
`means for subtracting said stored compensation val-
`ues from output signals of respective detectors
`each time the detectors are connected to said com-
`
`mon junction during a subsequent normal system
`operation.
`8. Apparatus as defined in claim 7 wherein said mea-
`suring means includes means for averaging a number of
`output signal measurements of each detector during
`said calibration operation, and producing said average
`for storage in said storing means as the compensation
`value of each detector.
`9. Apparatus as defined in claim 7 wherein said low
`level of incident energy is provided by capping said lens
`system,
`thereby producing a uniformly low level of
`incident energy for said array at virtually absolute zero.
`10. Apparatus as defined in claim 9 wherein said
`measuring means includes means for averaging a num-
`ber of output signal measurements of each detector
`during said calibration‘ operation. and producing said
`
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`9
`average for storage in said storing means as the com-
`pensation value of each detector.
`11. Apparatus for compensation of fixed-pattern
`noise in an imaging system employing an array of pho-
`todetectors comprising
`means in place for providing a low-level of illumina-
`tion uniformly incident on all photodetectors of
`said array,
`means for operating said array through at least one
`calibration cycle to obtain a separate video output
`signal
`from each photodetector with said first
`named means in place,
`means for converting each separate video output
`signal from each photodetector to digital form,
`means for storing each video output signal thus con-
`verted to digital form in a different electronic
`memory location, each memory location being
`associated with a separate one of said photodetec-
`tors,
`means for operating said imaging system in a normal
`manner with said means in place not in place to
`permit light images to reach said array,
`means for nondestructively reading out of said mem-
`ory each of said stored digital video signals asso-
`ciated with each of said photodetectors from said
`associated memory locations as said array is oper-
`ated in a normal manner,
`means for converting the digital signals as read from
`said memory to analog form to provide a compen-
`sation signal, and
`
`10
`means for subtracting each compensation signal thus
`obtained for each photodetector from each video
`output signal obtained therefrom during said nor-
`mal operation.
`12. Apparatus of claim 11 including means for oper-
`ating said array through a plurality of calibration cycles
`with said first named means in place and wherein each
`video output signal produced during said plurality of
`calibration cycles is converted to a digital form and
`averaged with all video output signals obtained from
`the same photodetectors dur