United States Patent
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`4
`
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`
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`USOOS4-42282A
`
`[11]
`
`Patent Number:
`
`5,442,282
`
`Rostoker et al.
`Date of Patent:
`[45]
`Aug. 15, 1995
`
`[75]
`
`I
`
`I 1
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`[54] TESTING AND EXERCISING INDIVIDUAL,
`I
`UNSINGULATED DIES ON A WAFER
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`Inventors: Michael D. Rostoker; Carlos
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`Dangelo; James Koford, all of San
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`“519156:
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`[2;] Appl. No.: 903,687
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`................................... GOIR 31/28
`Int. C16
`[51]
`[52] us. Cl. ................................ 324/158.1; 324/73.1;
`340/825.07
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`[58] Field of Search .............. 324/158 R, 73.1, 158 F,
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`324/158 P; 437/8; 257/48; 340/825.07
`References Cited
`
`[56]
`
`~ ~
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`~
`
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`II
`I
`5,053,700 10/1991 Parrish ..................... 324/ 158 R
`I
`5,059,899 10/1991 Farnworth et a1.
`..... 324/ 158 R
`I ~
`
`I
`I
`~
`I: ~ I
`5,081,601
`1/1992 Eirikasson ................ 364/578
`~ ~
`
`5,149,662 9/1992 Eichelberger ............... 437/8
`
`5,159,752 11/1992 Mahant—Shetti et al.
`. ............ 29/846
`FOREIGN PATENT DOCUMENTS
`~ 0
`~ ~ -. '. ~
`................ 31/28
`0212208 7/1986 European Pat. Off.
`I
`0223714
`5/1987 European Pat. Off. ......... 31/28
`~
`'. ~
`~
`
`I 'lie a
`~ a-.
`0290066 11/1988 European Pat. Off. ......... 31/28
`2203977 5/1974 France .................................... 31/26
`OTHER PUBLICATIONS
`,
`,
`,
`_
`s
`~
`Dynamic Bum-1n 0f Integrated. Circmt Chips {Kt The
`- I
`~
`Wafer Level”, IBM Technical Disclosure Bulletin, vol.
`~
`29, NO- 5, NOV- 1986-
`~
`~
`~
`Primary Examiner—Vinh Nguyen
`Attorney, Agent, or Firm—Gerald E. Linden
`
`~
`
`“
`
`~
`
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`
`U.S. PATENT DOCUMENTS
`~ ~
`
`[57]
`
`ABSTRACr
`
`~
`
`~
`
`~
`
`~
`
`~
`
`~
`
`~
`
`
`.. 340/1725
`3,806,891
`4/1974 Eichelberger et a1.
`.
`3,849,872 11/1974 Hubacher .......................... 29/574
`' ~ ' ~ I
`
`3,969,670 7/1976 Wu ...............
`324/73 PC
`
`~
`3/1931 011110 8t 31-
`4,255,677-
`------
`307/455
`~
`
`~ . ~
`I
`4,293,913 10/1981 Dasgupta ct 3L
`"""" 364/716
`'I '
`2,3353; 1323::
`:mnlg """""""""""""""""""" 33:2:
`': ~
`I ~
`
`4,486,705 12/1984 S3111):e;"""""""""""""""""324/73 1
`I
`~ ~ ~
`4:511:914 4/1985 Remedi etal....... 357/45
`' ~
`
`.. 324/73 R
`4,714,876 12/1987 Gay et a1.
`...... 324/73
`4,749,947
`6/1988 Gheewala
`
`8/1989 Weber ............... 437/8
`4,855,253
`
`4,884,118 11/1989 Hui et a1. ............... 357/42
`~ ~ I
`
`4:937’87-6 6/1990 Gheewala Ct 31
`------- 371/22-1
`~ ~ I
`~ ~ I
`419261502 3/1990 P1111511 -----------
`324/158 R
`' ~
`~ ~ I
`I
`
`$36,173:: $238 1612::anetal““““““323%;}:
`~ ~ I
`4:968:931 11/1990 Littlebury et al.
`............. 324/158 R
`4,975,640 12/1990 Lipp .................... 324/158 R
`~ I
`
`4,985,988
`1/1991 Littlebury
`.......... 29/827
`~
`9/1991 Smith et al.
`..................... 324/ 158 R
`5,047,711
`
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`Signals (including probCS) from an external System 2#6
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`selectively connected to a plurality of unsingulated d1es
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`on a semiconductor wafer with a minimum number of
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`US. Patent
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`Aug. 15, 1995
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`U. S. Patent
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`

`U. S. Patent
`
`Aug. 15, 1995
`
`Sheet 27 of 27
`
`PRlQR ART
`Flg. 118
`
`33
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`DATA
`CLOCK OUTPUT
`PARALLEL/
`SERIAL CONTRQL
`
`Fig. 11b
`
`PRlOR ART
`
`

`

`TESTING AND EXERCISING INDIVIDUAL,
`UNSINGULATED DIES ON A WAFER
`
`TECHNICAL FIELD OF THE INVENTION
`This invention
`relates to integrated circuit (IC) semi-
`conductor devices and, more particularly
`to the power-
`testing and burning-in of such devices (dies).
`ing-up,
`BACKGROUND OF THE INVENTION
`Modern integrated circuits are generally produced by
`creating several identical integrated circuit dies (usually
`square or rectangular areas) in an area on a single (usu-
`ally round) semiconductor wafer,
`then scribing and
`slicing the wafer to separate
`(singulate, dice) the dies
`(chips) from one another. An orthogonal grid of "scribe
`line" (kerf) areas extends between adjacent dies, and
`for evaluating
`sometimes contain
`test structures,
`the
`fabrication process . These scribe lines areas, and any-
`thing contained within
`them, will be destroyed when
`the dies are singulated
`from the wafer. The singulated
`(separated) dies are then
`individually
`packaged, and
`may be tested after packaging.
`Under ordinary circumstances, pressure to maximize
`the useful, or productive area of a wafer dictates that
`scribe line area be kept as small as possible. Dies are laid
`out on a wafer in a pattern
`that is packed as tightly as
`possible. Scribe line widths are only large enough
`to
`ensure that the dies can be separated without damage to
`the area of the dies.
`Circuits and active elements on the dies are created
`while the dies are still together
`on the
`(un-singulated)
`wafer by ion deposition,
`electron beam
`lithography,
`plasma etching, mechanical polishing,
`sputtering,
`and
`other methods which are well known
`numerous
`to
`in the art of semiconductor
`those skilled
`fabrication.
`These processes are highly developed and are capable
`of producing extremely complicated circuits on the dies
`low cost.
`at a relatively
`The complexity of integrated circuits
`is limited,
`in
`part, by the purity of the semiconductor wafers avail-
`able. These wafers contain minuscule defects which
`may be distributed
`the wafer,
`randomly
`throughout
`especially the surface where integrated circuit elements
`are fabricated. The larger the integrated circuit (i. e. , the
`greater its "die size"), the greater the probability
`that it
`will be affected by such a defect. Integrated circuits
`which intersect a defect on the semiconductor wafer are
`rendered non-functional,
`generally
`and therefore use-
`less. Improvements
`in the wafer production process are
`yielding purer wafers with smaller defect sizes and
`densities.
`the size of individual
`By reducing
`circuit elements,
`e. g. transistors,
`it has become possible
`to place more
`circuitry
`in the same area (e. g. , die site) which would
`previously have been occupied by larger circuit ele-
`ments of lesser complexity. However,
`the same size
`reductions which enable greater circuit complexity also
`render
`the resulting
`smaller circuits more sensitive
`to
`more minuscule defects in the semiconductor wafer.
`Trade-offs between circuit complexity
`(i. e. , number
`of transistors and circuit area) and anticipated yield (i. e. ,
`the number of "good" circuits per wafer) are made by
`based upon a number
`integrated circuit manufacturers
`of factors. The higher the yield, the less a circuit costs
`to produce, permitting a lower market
`the manufacturer
`price.
`
`5
`
`15
`
`can
`
`Among the problems faced by integrated circuit man-
`ufacturers are packaged chips (dies) which fail in final
`test and, even worse, chips which pass final
`test but
`flaws due to an inability
`which have undetected
`to test
`them completely. The inability
`to test an integrated
`circuit completely arises from the fact that while circuit
`density and complexity has increased dramatically,
`the
`number of Input/Output
`(I/O) pads which can feasibly
`be disposed to a chip has not increased correspondingly.
`10 Generally, pads are much larger than individual circuit
`elements. This creates serious
`since
`testing problems,
`amounts of test information must be
`ever-increasing
`the use of a relatively
`obtained
`through
`limited number
`of I/O pads (test points).
`"Burn-in" is a process whereby a chip (die) is either
`simply powered up ("static" burn-in), or is powered up
`and has signals exercising to some degree the function-
`ality of the chip ("dynamic" burn-in).
`In both cases,
`burn-in
`at an elevated
`is typically performed
`tem-
`20 perature — the object being to detect chips that are de-
`fective. Burn-in
`is usually performed on a die-by-die
`basis, after the dies are separated (diced) from the wafer.
`Another technique for burning-in dies, prior to dicing
`(on the wafer), is to mechanically place test probes or
`25 bond ~ires on each die, or on pads associated with each
`individual die and located in the scribe lines between
`the dies.
`Another technique for burning-in dies, prior to dicing
`is to provide a common network of
`(on the wafer),
`30 power and ground conductors
`in the scribe lines, the
`lines connected to all of the dies on
`power and ground
`a wafer. Generally,
`the power and ground
`lines simply
`power up the device for static burn-in, but built-in self
`test (self-starting,
`circuitry on the
`signal-generating)
`35 chip can also provide signals on power up to exercise
`some of the functionality of the chip. This is discussed in
`copending, commonly-owned U. S. Patent Application
`No.
`(Docket No. LLC2087/LSI1P006),
`entitled
`METHODS FOR DIE BURN-IN, filed by Rostoker
`40 and Dell'Oca.
`It should be noted that where "power and ground"
`to herein, any and all power connections
`are referred
`are included. Recent trends in technology have tended
`the design of semiconductor
`to push
`devices
`in the
`45 direction of single voltage supplies, and this terminol-
`ogy reflects
`trend. However, herein,
`this
`the
`term
`"power and ground" refers to all required power supply
`voltages.
`Another
`for die burn-in, on the wafer,
`technique
`is
`in the aforementioned
`50 discussed
`copending, commonly-
`owned U. S. Patent Application No. (Docket No. LLC-
`2087/LSI1P006). This
`technique
`involves
`bonding
`wires to the wafer either (1) to bond pads on each die,
`or (2) to bond pads for each die in adjacent scribe lines.
`for either burn-in or testing, difficulties
`Generally,
`arise in a few areas:
`1) Traditional methods of testing do not provide
`adequate fault coverage to guarantee
`that the dies iden-
`tified as functional ("good") are indeed fully functional;
`2) A large number of test points is generally required,
`necessitating
`cumbersome
`to in-
`expensive equipment
`terface with the wafer for testing; and
`for signal interconnections
`3) Routing channels
`require a great deal of surface area.
`In recent years, a number of schemes have arisen to
`address the testability problems of large, complex inte-
`grated circuits. Some examples of these techniques are
`testing" (ref T. W.
`known as SCAN or "Scan-path
`
`55
`
`60
`
`65
`
`

`

`5, 442, 282
`Williams and K. P. Parker, "Design for Testability — A
`survey" Proc. IEEE, Vol. 71, pp. 98-112, January,
`1983), BIST or "Built-in Self-Test" (ref. E. B. Eichel-
`berger and T. W. Williams, "A logic Design Structure
`for LSI Testing" Proc. 14th Design Automation Conf. , 5
`June, 1977, 77CH1216-1C, pp. 462-468; also, E. J.
`McClusky, "Built-In Self-Test Techniques" and "Built-
`In Self-Test Structures" IEEE Design and Test, Vol. 2,
`No. 2, pp. 437-452, April, 1985). These techniques deal
`with testing large integrated circuit structures by incor- 10
`porating on-chip test facilities (structures) which allow
`to portions of the circuit and re-
`to be applied
`stimuli
`sponses to be readily read back and observed. SCAN
`and BIST testing are based on providing a means for
`the storage elements of a sequential circuit 15
`accessing
`(e. g. flip-flops) and using
`them to control and/or ob-
`serve various portions of the integrated circuit to which
`they are applied.
`U. S. Pat. Nos. 3, 806, 891; 4, 293, 919; and 4, 513, 418
`to the IBM Corporation) describe methods 20
`(assigned
`the flip-flops of a circuit may be used as test
`whereby
`them into a serial chain (shift-
`points by re-configuring
`register) and used to shift in test data and to shift out test
`results.
`U. S. Pat. No. 4, 340, 857 (Fasang) describes the use of 25
`linear feedback shift registers (LFSRs) for generating
`test patterns and for compacting
`test results.
`U. S. Pat. No. 4, 423, 509 (Feisel) describes yet another
`use of the flip-flops of an integrated
`circuit as test
`points.
`to a broader range of
`Another
`technique applicable
`in U. S. Pat. No. 4, 749, 947
`test problems
`is described
`(Gheewala), entitled "Grid-Based,
`'Cross-Check' Test
`Structure for Testing Integrated Circuits" incorporated
`by reference herein The patent is directed to providing 35
`a grid of externally — as well as individually-accessible
`probe lines and sense lines with electronic switches at
`the crossings of these probe and sense lines. One end of
`each switch is connected to a test point on a die, which
`to be monitored or controlled 40
`test point
`is intended
`during a testing
`regimen, and the other end of each
`switch is connected to an associated sense line. The ON
`or OFF state of each switch is governed by a control
`input from a probe line. The probe and sense lines are
`connected to external
`test electronics. By excitation of 45
`an appropriate probe line, and monitoring
`(or exciting)
`an appropriate sense line, test signals present at any one
`of the test points can be monitored
`(or controlled).
`lines per die are required: power,
`four
`Generally,
`ground, a plurality of probe lines, and a plurality of 50
`sense lines. (In the case of a die requiring multiple sup-
`ply voltages,
`U. S. Pat. No. 4, 749, 947 also suggests the possibility of
`cross-checking multiple ICs on a wafer. FIG. 7 therein
`shows a grid of numerous probe and sense lines criss- 55
`ICs. FIGS. 9a and 9b therein also
`crossing multiple
`show many ICs being cross-checked on a wafer. In
`FIG. 9a, the usually unused "kerf area" (scribe line)
`lying between adjacent ICs is used to place probe points
`for the probe and sense lines. In FIG. 9b, it is suggested 60
`that I/O pads on "other" (typically adjacent) ICs can be
`used as probe points for cross check testing a particular
`ICs, when the "other" ICs are not being cross checked.
`U. S. Pat. No. 4, 937, 826 (Gheewala, et al. ), entitled
`"Method and Apparatus
`for Sensing Defects in Inte- 65
`grated Circuit Elements"
`incorporated
`by reference
`to the technique of
`herein, describes an improvement
`the aforementioned U. S. Pat. No. 4, 749, 947, involving
`
`30
`
`the sense lines to adjust detection
`pre-charging
`levels.
`The patent also discloses a method of reducing
`test
`to Boolean expressions, using "path sensitiza-
`patterns
`tion".
`U. S. Pat. No. 4, 975, 640 (Lipp), entitled "Method for
`Operating a Linear Feedback Shift Register as a Serial
`Shift Register with a Crosscheck Grid Structure" incor-
`porated by reference herein, describes a further
`im-
`the aforementioned U. S. Pat. No.
`to
`provement
`4, 749, 947, whereby
`a linear
`feedback
`register
`shift
`(LFSR) may be used in combination with the grid based
`the number of logic
`cross check structure
`to reduce
`to shift data out serially, and to
`structures
`required
`increased controllability over the cross check
`provide
`structure with compaction of the test result data while
`the number of I/O points re-
`dramatically
`reducing
`quired to accomplish
`the testing.
`The techniques of testing, particularly
`cross-check
`testing described above are largely per-die-oriented,
`with little or no teaching of efficient implementation
`at
`wafer level.
`the techniques of static or dynamic burn-
`Similarly,
`ing-in, described above, fail to show efficient implemen-
`tation at wafer level.
`What is needed is efficient techniques for implement-
`ing cross-checking
`(testing) and dynamic burning-in at
`level. For example, with regard
`wafer
`to the cross-
`check techniques,
`in order to efficiently
`test numerous
`dies on a wafer, it would be desirable
`to dramatically
`reduce the number of probe and sense lines required. A
`reduction on the order of "n"/2:1 where "n" is the
`number of dies on the wafer is this kind of "dramatic"
`reduction (i. e. , a reduction
`in the number of probe and
`sense lines of 50:1 for a wafer with 100 dies on it is a
`"dramatic" reduction over known cross-check
`tech-
`niques.
`
`DISCLOSURE OF THE INVENTION
`It is therefore one object of the present invention
`to
`provide a technique
`for electrically accessing
`individ-
`dies on a wafer, for the purpose of
`ual, unsingulated
`powering-up, providing signals from an external source
`to, and/or
`testing the dies individually or in groups.
`It is a further object of the present invention
`to pro-
`vide a technique
`for testing
`individual,
`unsingulated
`semiconductor dies, prior to the dies being diced (sin-
`gulated) from the wafer, with a minimum number (rela-
`tively few compared with the number of dies) of "test
`points" (probe and sense lines) required on the wafer.
`It is a further object of the present invention
`to pro-
`vide substantially 100% fault coverage (testing) for all
`of the dies on a wafer.
`It is a further object of the present invention
`to pro-
`vide a technique for burning-in
`individual dies, prior to
`the dies being diced (singulated)
`from the wafer, with a
`minimum number of lines.
`It is a further object of the present
`to pro-
`invention
`for selecting and isolating
`vide a technique
`individual
`dies on a wafer.
`It is a further object of the present
`to ac-
`invention
`the above mentioned
`complish
`testing with the same
`physical and/or electrical interface for all of the dies on
`a given wafer, even though the dies may be of different
`size and may perform different functions.
`According to the invention,
`these and other objects
`are achieved by implementing
`a technique for electroni-
`cally (rather
`"walking around" a
`than mechanically)
`wafer to provide power to and/or
`to stimulate and/or
`
`

`

`to monitor (probe) individual dies on a selectable basis,
`either for cross-check-type or similar
`testing or for
`burn-in, especially dynamic burn-in. For the purposes of
`the term "individual dies" means either:
`the invention,
`1) a single die; or 2) a number of dies significantly
`less
`the total number of dies on the wafer. That is,
`then
`"electronically selecting a small number (relative to the
`total number of dies, such as a row, a column, or any
`other small group of dies) of dies on a wafer", and "elec-
`tronically selecting a single die on a wafer" are both &0
`described by the phrase "electronically selecting
`indi-
`vidual dies on a wafer". The invention
`further makes
`use of "normal" die sites, "mutant" die sites, and scribe
`line area, defined hereinbelow. Suitable
`implementa-
`involve one or more of the fol- t5
`tions of the technique
`lowing:
`I. Placing an appropriate, minimum number of con-
`ductors in the scribe line areas on a wafer, including:
`a. At least one power line and at least one ground line
`for powering up the dies for testing and for burn- 20
`ing-in.
`b. A plurality of probe lines and a plurality of sense
`lines for implementing
`a cross-check
`type testing
`methodology.
`c. Preferably,
`redundant power and ground
`lines are
`to provide coverage
`in the event of an
`provided,
`open line.
`2. Providing
`a means of isolating
`short circuits,
`whether
`these shorts occur on a particular die (more 30
`likely) or in the conductors
`(especially power and
`in the scribe lines (less likely). This is accom-
`ground)
`plished by:
`a. Fabricating diodes at the interface of the power
`lines to the individual dies. This will 35
`and ground
`prevent a faulty (e. g. , shorted) die from interfering
`with the powering up of other (good) dies.
`b. Fabricating diodes at strategic locations along the
`paths of the scribe line power and ground conduc-
`tors, such as a pair of diodes for each row and 40
`column of power and ground conductors.
`c. Alternatively
`(or additionally),
`providing
`fusible
`connections
`in the power and ground conductor
`lines.
`3. Providing a mechanism for implementing die selec- 45
`tion, such
`a. multiplexers
`(muxes);
`b. shift registers;
`c. steppers; or
`d. a separate electron beam probe apparatus.
`4. Providing an electronic mechanism
`in an area of
`the wafer for selecting individual dies for testing and/or
`burn in by either:
`a. Using mutant die-sites for the die select mechanism
`(muxes, semiconductor
`switches, and the like).
`b. Using one or more otherwise "good" die sites,
`for the die select mechanism
`sacrificially,
`(muxes
`and the like), rather than for fabricating devices to
`be used after dicing.
`c. Providing at least a portion of the cross-check type 60
`testing electronics on the wafer, either in the scribe
`line areas, or at particular die sites.
`d. by forming a discrete structure on and overlying
`the wafer.
`e. In any case, preferably,
`leaving sufficient electron- 65
`ics on each chip, so that
`dies can be
`individual
`tested after dicing or packaging, as well as on the
`wafer.
`
`50
`
`5. Providing a unique address for each die, on the die,
`by either:
`a. Providing on-die circuitry responsive
`to a unique
`binary parallel or serial pattern (which would re-
`a "merging" of die-location-independent
`quire
`standard die electronics with die-location-depend-
`ent circuitry at or prior to fabrication
`time).
`b. Providing circuitry for detecting unique die ad-
`dresses in the area of the scribe lines.
`6. Rather than placing the power and ground, and/or
`the probe and sense lines in the scribe lines, or through
`or on adjacent dies, providing
`the power, ground, probe
`in a grid of overlying metal
`and sense
`lines
`lines,
`~hereby:
`a. Vias are provided from the grid of overlying metal
`lines to the individual dies;
`b. The overlying grid of lines also provides for elec-
`tromagnetic (EM) shielding of the devices (dies) on
`the wafer;
`c. The overlying grid of metal lines can also be used
`to subsequently
`interconnect dies;
`d. The overlying grid of metal lines can also be subse-
`quently polished away, and re-worked
`(if defec-
`tive) or reformed
`in a different configuration
`to
`interconnect "good" dies.
`7. Integrating signal exercising circuits, signal genera-
`tors, power-on
`reset circuits, or self-starting
`self-test
`circuits onto the wafer for generating
`signals for dy-
`thereby avoiding a plurality of dynamic-
`namic burn-in,
`burn-in
`lines, permitting
`signal
`automatic power-on
`initialization of dies and test circuitry, and minimizing
`the number of physical probe points required to control
`elaborate test sequences. This circuitry may be placed in
`mutant die sites, normal die sites, in the scribe line area,
`or any combination of these.
`8. Using a separate E-beam tool to:
`a. insert signals for testing and/or dynamic burn-in, or
`b. alternatively or additionally,
`latching
`providing
`and/or
`toggling circuits specifically for use in con-
`junction with
`such an E-beam
`tool, providing
`"touch switches" that an E-beam tool may "touch"
`once to generate a signal which will remain after
`the E-beam tool has moved on to another point on
`the wafer.
`9. Mounting
`the wafer, such as by a vacuum chuck to
`a heating platform,
`to elevate
`the temperature of the
`dies on the wafer for burn-in.
`10. Providing
`die selection circuitry
`redundant
`in
`conjunction with appropriate
`(e. g.
`isolation circuitry
`links) to minimize
`fusible
`the likelihood
`that a flawed
`selection circuitry will prevent testing and burning
`in of
`dies prior to dicing.
`By testing and burning-in unsingulated
`dies prior to
`dicing them from the wafer, using electronic die selec-
`the "slew" time
`tion
`techniques,
`from die-to-die
`is
`reduced vis-a-vis any type of hard wiring
`greatly
`to
`individual dies (" flying wire"), mechanical probing or
`test-after-dice methodology.
`A further advantage of electronically
`(versus me-
`chanically) selecting individual dies on a wafer for test-
`ing and/or burning-in
`is that integrated circuit Input-
`(I/O) pads are shrinking
`/Output
`to the point where
`they are simply becoming difficult
`to mechanically
`probe. By being able electronically
`to "walk around"
`the wafer, any pad size is a non-problem.
`A further advantage of the present invention, namely
`testing and especially burning-in at wafer level, is that
`test sockets and burn-in boards are expensive accesso-
`
`

`

`5, 442, 282
`
`the overall cost of fabrication which
`ries increasing
`must be amortized.
`Other objects, features and advantages of the inven-
`in light of the following
`tion will become apparent
`thereof.
`description
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1a is a diagram of the prior art showing various
`features of a wafer, including normal dies, mutant dies,
`and scribe lines.
`FIG. lb is a diagram of the prior art illustrating
`"pinch points" and the peripheral area of a wafer.
`FIGS. 2a and 2b are sections of a wafer.
`FIG. 3a — 3c are diagrams of a section a wafer showing
`a die selection mechanism of the present mechanism.
`FIGS. 4a-4b are simplified
`schematics of selector
`switches as they relate to the present invention.
`FIGS. 5a-5h are schematics of various
`selector
`of selector
`switch circuits suitable for implementation
`switches of the type shown in FIGS. 4a-4d.
`FIGS. 6a — 6f are diagrams of die selection employing
`the techniques of the present invention.
`FIGS. 7a-7f illustrate various methods of diode and
`fuse isolation of die selection lines.
`FIGS. 8a — 8c illustrate
`for blowing
`techniques
`fuses
`on fuse-isolated die selection lines as they relate to the
`present invention.
`FIGS. 9a and 9b show an auxiliary circuit for use
`with E-beam probing as it relates to the present inven-
`tion.
`FIG. 10a-10e illustrate various techniques
`for reduc-
`ing the number of external interface points required for
`wafer-level burning and testing.
`FIGS. 11a and lib are schematic view of a prior art
`for implementing
`testing on a
`cross-check
`technique
`die. The view of FIG. lla is a "magnified" view of a
`selected portion of FIG. 11b. More particularly,
`the
`in FIG. 11b at the intersection of
`circled area shown
`lines S5 and Pi is shown in greate