United States Patent
`Ekstedt et al.
`
`[19]
`
`[54] CONTROL SYSTEM FOR AUTOMATED
`PARAMETRIC TEST EQUIPMENT
`Thomas W. Ekstedt, Palo Alto; Mary
`[75] Inventors:
`L. Dryden, Mountain View; Ulrich
`Kaempf, Los Altos; Richard R. Clark,
`Redwood City, all of Calif.
`[73] Assignee: Hewlett-Packard Company, Palo
`Alto, Calif.
`[21] Appl. No. : 570, 998
`[22] Filed:
`Aug. 21, 1990
`
`[56]
`
`Related U. S. Application Data
`[63] Continuation of Ser. No. 195, 667, May 18, 1988, aban-
`doned.
`[51] Int. Cl. 5 . . . . . . . . . . . . . . . . . . . . . . . G01R 31/28; G06F 11/22
`[52] U. S. Cl. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324/73. 1; 324/158 R;
`371/15. 1; 371/22. 1
`[58] Field of Search . . . . . . . . . . . . . . 324/158 F, 158 R, 73. 1;
`371/15. 1, 22. 1, 22. 4, 20. 1; 437/8
`References Cited
`U. S. PATENT DOCUMENTS
`Fergason et al. .
`3, 996, 517
`12/1976
`Bove et al. . . . . . . . .
`7/1977
`4, 038, 599
`8/1978
`4, 108, 358
`Niemaszyk ei al.
`. . . . . . . . . . . .
`9/1979
`4, 168, 527
`Winkler
`Michel et al. . . . . .
`10/1982
`4, 354, 268
`Steiner . . . . . . . . . . . . . .
`4, 380, 070
`4/1983
`Petrich et al. . . . .
`4, 517, 512
`5/1985
`. . . . . . . . . . . .
`5/1986
`4, 590, 422
`Milligml
`Krug . . . . . . . . . . . . . . . . .
`10/1990
`4, 961, 053
`OTHER PUBLICATIONS
`H. D. Schnurmann, R. M. Peters and L. J. Vidunas, "A
`System for Testing LSI Multi-Chip Modules Using
`Through-the-Pins Testing", Proceeding of the Interna-
`
`. . 324/158 P
`. . . 324/158 P
`. . . . . 371/22. 1
`. . . . 371/20 X
`. . . . . 371/22. 1
`324/73 R X
`. . . . . 371/22. 1
`. . 324/158 P
`. . . . . . . . . . 437/8
`
`IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
`US005206582A
`[1 1] Patent Number:
`[45] Date of Patent:
`
`5, 206, 582
`Apr. 27, 1993
`
`tional Conference on Circuits and Computers, New
`York, 28 Sep. -l Oct. 1982, pp. 334-340, IEEE, New
`York.
`Stephen J. Peterson, "A High Level Test Program
`Generator for Electronics Manufacturing Test", Elec-
`tro 1988 Conference Record, vol. 13, 10-12 May 1988,
`pp. (45/2) 1-6, Los Angeles, Calif. , US.
`Reinhard Winkler, "Flexible Testing is the Best Test-
`ing", Elektronik, vol. 36, No. 21, Oct. 1987, pp. 70-74,
`(English Translation).
`Munich, Germany,
`Primary Examiner — Vinh Nguyen
`ABSTRACT
`[57]
`Disclosed is a control system and methodology used for
`test sequences using
`defining and executing parametric
`test equipment. The control system
`is di-
`automated
`vided into components which separate fixed, reusable
`from information which is specific to par-
`information
`tests. One component
`ticular
`reference data
`contains
`the configuration of the wafer being
`which describes
`tested as well as specifications for the tests to be carried
`out. Another component contains a set of measurement
`tests to be per-
`that describe
`algorithms
`individual
`formed on generic types of devices or parametric
`test
`structures. Execution of a test is carried out by a general
`test program which retrieves stored reference and test
`it to the measure-
`definition
`information
`and supplies
`to enable
`them to perform measure-
`ment algorithms
`ments on specific devices in the user specified sequence.
`The general
`test program additionally
`routes the mea-
`to data
`from the algorithms
`surement
`results obtained
`files and/or networks, and summarizes
`in a
`the results
`report format.
`standardized
`
`14 Claims, 10 Drawing Sheets
`
`WAFER
`TEST
`SPEC'S
`
`TEST
`MASK
`
`INFO
`
`54
`
`= — — CRT REPORT
`
`RUN-T IME
`
`WAFER
`SIRNARY
`REPORT
`
`OFFL INE
`DATA BASE/
`
`DATA ANALYSIS
`
`OPERATOR
`
`I
`
`I
`
`caIIAIIS I
`
`TEST DEF.
`FILES
`
`REF.
`INFO
`FILES
`
`GENERALIZED
`TEST PROGRAM
`
`I%AS PARAIIS.
`DEVICE
`INFO
`
`I%AS
`RESULTS
`
`I
`
`I
`
`DEVICE
`POSITION
`
`Vtex Delto
`
`Io ~ Dleok
`I NSTRIAKNTX WIKASURED
`/DATA
`II
`CONTROL
`
`I
`IKAsl I
`ALGS+
`
`I3
`
`INSTR
`PROBER LKNTS
`
`IO
`
`

`

`U. S. Patent
`US. Patent
`
`Apr. 27, 1993
`Apr. 27, 1993
`
`Sheet 1 of 10
`Sheet 1 of 10
`
`5, 206, 582
`5,206,582
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`U. S. Patent
`US. Patent
`
`Apr. 27, 1993
`Apr. 27, 1993
`
`Sheet 2 of 10
`Sheet 2 of 10
`
`5, 206, 582
`5,206,582
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`U. S. Patent
`
`Apr. 27, 1993
`
`Sheet 3 of 10
`
`5, 206, 582
`
`26
`
`28
`
`WAFER
`
`28
`
`DIE
`
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`
`DEVICE
`
`

`

`U. S. Patent
`
`Apr. 27, 1993
`
`Sheet 4 of 10
`
`5, 206, 582
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`

`

`U. S. Patent
`US. Patent
`
`Apr. 27, 1993
`.Apr.27,1993
`
`Sheet 5 of 10
`Sheet 5 of 10
`
`5, 206, 582
`5,206,582
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`

`U. S. Patent
`
`Apr. 27, 1993
`
`Sheet 7 of 10
`
`5, 206, 582
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`

`

`US. Patent
`
`Apr. 27, 1993
`
`Sheet 3 of 10
`
`5,206,582
`
`INITIALIZATION
`
`
`DISPLAY Ist SCREEN
`
`
`
`GET TEST NAME
`READ CONFIG FILES
`~
`~
`
`
`BUILD ARRAYS
`
`6C)
`
`ALLOW USER TO PERFORM EDIT
`~
`~
`OF PARAMETERS AND CONSTANTS
`0
`~
`
`6
`
`6
`
`INITIALIZE PROBER
`DISPLAY ALIGNMENT INFO
`~
`OPERATOR OR EQUIPMENT ALIGNS WAFER
`~
`~
`~
`
`
`
`INITIALIZE DATA STORAGE PACKAGE
`
`68
`
`74
`
`76
`
`
`
`
`
`
`
`PROBE AND MEAS:
`-GET WAFER
`
`—GET TEST PAIR
`
`-GET DIE
`
`
`t ~
`-GET MODULE
`-GET DEVICE
`
`
`-GET MEASUREMENT
`
`-GET ALGORITHM
`CALL ALGORITHM
`
`STUFF MEASURED DATA
`
`
`
`
`
`
`
`
`
`
`
`-NEXT ALGORITHM
`-NEXT MEASUREMENT
`-NEXT DEVICE
`~ I
`-NEXT MODULE
`~
`-NEXT STORE DATA ON DISK OR LINK
`~
`~
`~
`
`
`NEXT DIE
`-NEXT TEST PAIR
`
`-NEXT WAFER
`
` '78
`
`DISPLAY FINAL SCREEN
`
`v
`
`
`
`
`
`
`YES
`
`PRINT FINAL
`REPORT
`
`EIID
`
`FIGS
`
`

`

`U. S. Patent
`
`Apr. 27, 1993
`
`Sheet 9 of 10
`
`5, 206, 582
`
`GET NEXT WAFER
`
`I
`
`I
`
`I
`
`GET NEXT DIE
`f
`IGET NEXT MODULE
`r — -g
`GET NEXT DEV I CE
`r
`IGET NEXT MEASUREMENT
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
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`
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`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`GET NEX ALGORITHM
`
`ALGORITHM
`
`TEST THE DEVICE
`
`MEASURED
`
`DESIRED
`LIMIT ?
`
`NO
`
`SET TEST SEQUENCE
`INDICATOR (tsi)
`8F SKIP TO DESIRED
`LEVEL
`
`YES
`GOOD DEVICE
`SET tsi~ CONTINUE
`TESTING NORMALLY
`
`I
`
`I
`
`x
`IR
`Iz
`
`I»
`
`x
`
`CHECK VALUE OF tsi
`
`tsi~ NORMAL
`
`YES
`
`STORE TEST RESULT
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`DETERMINE PATH
`DEPENDING ON
`VALUE OF TEST
`SEQUENCE
`INDICATOR
`
`

`

`U. S. Patent
`
`Apr. 27, 1993
`
`Sheet 10 of 10
`
`5, 206, 582
`
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`

`

`1
`
`5, 206, 582
`
`CONTROL SYSTEM FOR AUTOMATED
`PARAMETIUC TEST EQUIPMENT
`
`Cross Reference to Related Applications
`This is a continuation of copending application Ser
`No. 07/195, 667 filed on 5/18/88, now abandoned.
`BACKGROUND OF THE INVENTION
`The present invention
`relates to automatic
`test equip-
`to automated parametric
`ment, and more particularly
`the characteristics of inte-
`test systems for determining
`grated circuits during the development of processes for
`such circuits. More specifically,
`manufacturing
`the
`is concerned with a system for con-
`invention
`present
`testers in a manner which
`troHing automated parametric
`the development of tests and improves
`facilitates
`the
`reusability and maintainability of pro-
`documentation,
`grams for performing
`testing routines.
`In the development of processes for manufacturing
`integrated circuits, it is necessary to frequently conduct
`tests on wafers manufactured by the process, to deter-
`mine whether
`structures on the wafers meet desired
`specifications. Accordingly, once a process
`is devel-
`oped, a sample of wafers is manufactured
`in accordance
`with the process and parametric
`tests are performed on
`to determine
`the wafers
`the effects the process may
`characteristics of circuit devices
`have on operating
`the wafer. For example,
`to
`it may be necessary
`within
`the gate leakage current of an MOS transistor
`determine
`or the breakdown voltage of a capacitor. During a typi-
`cal process development cycle, it may be necessary
`to
`create several different parametric
`to fre-
`tests and
`to test results and
`them
`in response
`quently modify
`other ongoing developments. Once the development of
`the process is completed,
`further parametric
`is
`testing
`occasionally carried out to monitor the process.
`In the past, the programs for controlling
`the paramet-
`ric testing equipment
`to carry out specific tests on a
`wafer have been custom designed for each new applica-
`the design of
`tion. In other words, 'details concerning
`to be tested and the specific tests to be
`the structure
`performed on that structure were hard-coded
`into the
`program. These two different types of information were
`the program. For every new
`intertwined
`throughout
`wafer design or device that was to be tested, or for each
`new series of tests that were to be performed on a wafer,
`an entirely new program had to be written. Even if the
`same type of structure was to be tested but in a different
`location from a previously
`tested structure, new code
`had to be written to describe the new test.
`As integrated circuit processes become more com-
`plex and expensive, increasingly more sophisticated and
`tests are being performed
`comprehensive parametric
`in
`an effort to maxitnize
`the information
`that is obtained
`from each lot of wafers. Due to the practice of custom
`designing a control program for each new application,
`the development of the
`the turnaround
`time between
`new process and the receipt of feedback
`information
`relating to that process is becoming unacceptably
`long.
`it might take months for each new program
`Typically,
`to be written and checked for correctness, and hence
`information provided by the results of that program can
`not be obtained
`in the meantime.
`is specifically de-
`Further, because each program
`signed for a particular application,
`there is generally not
`much reuse of individual programs. As such, there is
`to document
`the programs as they
`very little tendency
`
`2
`are being written, and hence they become difficult to
`maintain.
`BRIEF STATEMENT OF THE INVENTION
`to provide an environ-
`it is desirable
`Accordingly,
`tests to be more efficiently
`ment that enables parametric
`created and modified,
`reduce
`the turn-
`thereby
`and
`time for test development.
`In accordance with
`around
`such a capability
`the present
`is provided by
`invention,
`means of a test shell in which different functional as-
`pects of the parametric
`test operation are divided
`into
`that can be
`separate components containing
`information
`to carry out any desired
`test.
`referred
`to, as needed,
`in the test shell: (1) a con-
`There are three components
`file library consisting of reference
`informa-
`figuration
`(2) a measurement
`tion and test-definition
`information,
`test program. The
`library and (3) a general
`algorithm
`is data; the second two components are
`first component
`~ programs and subroutines. One subcomponent,
`the ref-
`erence information, contains fixed information
`relating
`to the configuration of a wafer to be tested, as well as
`relating to the test equipment. Since this
`specifications
`information does not change over time, it only needs to
`25 be entered into the system once and can be subsequently
`referred to as necessary to carry out test procedures.
`Another
`the measurement
`component,
`algorithm
`library contains the subroutines which perform each of
`the possible types of measurements
`that can be carried
`type of device. Again, these sub-
`3p out on each available
`fixed from one wafer to another, and
`routines
`remain
`into the system once.
`thus need only be programmed
`Since all of the reference information
`relating to the
`configuration of structures and the procedures for per-
`tests are stored
`35 forming
`in the system,
`the
`individual
`to define a specific parametric
`effort required
`test se-
`quence is reduced to an identification of the individual
`devices to be tested and the measurements
`to be per-
`formed on each such device. This information,
`called
`4p the test definition
`. can be directly provided
`information,
`to the system by the process engineer, and is conve-
`niently entered by means of a suitable worksheet, either
`on paper or by means of a video display. Once the de-
`sired tests have been entered, a general
`test program,
`45 the third component,
`retrieves the appropriate
`informa-
`tion from the individual components
`regarding specific
`test procedures and the location of the devices on which
`the tests are to be performed, and controls the testing
`to carry out these tests.
`equipment
`Since much of the stored information
`is generic to a
`number of different
`types of tests, rather
`than being
`reuse of the infor-
`dedicated to a specific test, substantial
`is possible. Such reuse cou-
`in the components
`mation
`55 pled with the fact that this information can be directly
`entered by the process engineer, rather than a program-
`ming specialist, results in a significantly
`reduced devel-
`time. A three-to-tenfold
`opment
`in turn-
`improvement
`around time for test development has been experienced
`6p with the approach of the present invention. Further, the
`separation of the details of a parametric
`test from the
`program code and the organization of that information
`into a hierarchy
`results in self documentating
`tests and
`reliable code, making
`the control system much more
`than custom written
`test programs.
`65 maintainable
`features of the present
`Further
`the
`invention
`and
`advantages offered thereby are explained
`in detail here-
`inafter with reference to a preferred embodiment
`and
`
`

`

`selec-
`
`a
`illustrating
`for a quality
`
`illustration of the test sequence
`
`illustrative examples
`nying drawings.
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIG. 1 is a block diagram
`representation of a para-
`metric test system;
`FIG. 2 is a schematic
`illustration of the
`functional
`basic components of a control system
`implemented
`in
`accordance with the present
`invention;
`FIG. 3 is a pictorial and schematic
`illustration of the
`hierarchy of reference
`to the lay-
`information
`relating
`out of a wafer;
`FIG. 4 is a schematic
`hierarchy;
`FIG. 5 is an example of a die selection matrix;
`FIG. 6 is an example of a device/measurement
`tion matrix;
`FIG. 7 is a schematic circuit diagram
`MOSFET circuit device as configured
`check measurement;
`FIG. 8 is a schematic
`illustration of the operation of
`the general
`test program;
`FIG. 9 is a flow chart of the operation of the general
`test program;
`FIG. 10 is a flow chart of the test sequence alteration
`routine; and
`FIG. 11 is a flow chart of the routine for retrieving
`reference and test definition
`information and construct-
`ing the data arrays.
`DESCRIPTION OF THE ILLUSTRATED
`EMBODIMENTS
`To facilitate an understanding
`of the present
`inven-
`test system will be described
`tion, a typical parametric
`and the operation of the invention will be illustrated
`in
`the context of that system, where appropriate. It will be
`appreciated, however,
`that the invention
`is not limited
`type of parametric
`to the particular
`test system de-
`scribed herein. Rather, the concepts which underlie
`the
`to other types of
`invention may be equally applicable
`test systems.
`A typical parametric
`test system is illustrated
`in block
`diagram form in FIG. 1. Referring thereto, the paramet-
`ric test system includes a set of automated measurement
`instruments 10 which generate
`the appropriate voltage
`and current signals to be applied to devices on a wafer
`the signals generated by the devices
`and measure
`in
`terminals of the mea-
`response. The input and output
`to a relay matrix
`are connected
`surement
`instruments
`12. The matrix selectively applies
`the output
`signals
`instruments 10 to appropriate
`from the measurement
`probe pins in a wafer prober 13. These pins are located
`on a probe card 14 and engage contact pads on the
`wafer 15 being tested. The wafer is positioned
`relative
`to the pins by means of a suitable X- Y positioning mech-
`anism 17. The responding
`signals generated by the de-
`vices on the tested wafer appear at the same or other
`to
`pins on the wafer prober, and are similarly applied
`instruments 10 by means of the relay
`the measurement
`matrix 12.
`The particular output signals
`that are generated by
`and the probe pins to
`the measurement
`instruments,
`which these signals are connected by the relay matrix
`12, are selected by a controller 16. In addition,
`the con-
`the positioning of the pins in the
`troller 16 controls
`wafer prober to place them at a desired location on the
`tested wafer. The controller 16 can be a suitable desktop
`computer, for example, which executes a test program
`
`5, 206, 582
`
`that are depicted
`
`in the accompa-
`
`stored in its memory such as that provided by the pres-
`device 18 can be used to
`ent invention. An input/output
`enter reference and test definition
`information
`into files,
`serve as the operator interface during test execution and
`to the response of the tested
`reports relating
`5 display
`wafer.
`Referring to FIG. 2, a control program stored in the
`memory of the controller 16 for controlling a system of
`in FIG. 1 in accordance with the
`the type illustrated
`is comprised of three
`10 principles of the present invention
`major components which can be divided into two func-
`the defini-
`tional subsystems. One subsystem
`involves
`tion of tests, and is comprised of a configuration
`file
`library 22. The
`library 20 and a measurement
`algorithm
`relates to test execution, and is com-
`15 other subsystem
`prised of a general test program 24.
`The configuration
`file library 20 contains
`two basic
`types of information,
`reference
`test
`information
`and
`information. The reference
`in-
`definition
`information
`20 volves a complete description of the devices on a wafer
`to be tested and the equipment which
`the
`implements
`tests. Since the structure of the wafer and the equipment
`fixed after it has been produced,
`this informa-
`remains
`tion need only be entered
`into the configuration
`file
`25 library once, and can be shared by all of the process
`engineers who desire to perform different
`tests on the
`wafer. Test definition
`that is also stored in
`information
`file library 20 describes the individual
`the configuration
`tests that are to be performed on specific devices on the
`30 wafer. These tests can be different for each engineer
`who accesses the system.
`library 22 consists of a
`The measurement
`algorithm
`set of subroutines. The main purpose of each of these
`is to perform specific device measurements,
`subroutines
`35 but they are not limited to that function. For example,
`one subroutine may describe the sequence of steps nec-
`essary to measure the threshold voltage of an FET, and
`another subroutine may describe the test procedure for
`measuring diode leakage current. Other measurement
`to print special
`can be written
`subroutines
`40 algorithm
`reports, plot test data to the video screen or perform
`calculations on the data such as linear regressions.
`The general
`test program 24 interprets
`the informa-
`file library 20 and calls
`tion stored in the configuration
`from the measurement
`library 22
`45 subroutines
`algorithm
`to perform actual wafer testing. This program contains
`versions of all administrative
`standardized
`functions
`to each test, such as hardware
`common
`initialization,
`operator interface, measurement
`sequencing, data rout-
`50 ing and storage, etc. In response to the test information
`entered
`into the configuration
`file library by the user,
`test program 24 positions
`the general
`the wafer prober
`14 and accesses
`the appropriate measurement
`algo-
`rithms which switch the relay matrix 12 and control the
`55 actuation of the measurement
`to carry out
`instruments
`the desired testing. The general test program also gener-
`ates appropriate
`reports on the input/output
`output
`device 18.
`to conduct
`the information necessary
`By separating
`60 the tests into separate components
`in this manner, each
`engineer need only be concerned with that aspect of the
`program which pertains to his particular area of exper-
`tise. For example,
`the process engineer who
`is only
`in the results of certain tests does not have to
`interested
`layout of the
`the overall
`65 be generally
`familiar with
`in order to obtain
`the information
`wafer
`he desires.
`Rather, the layout information can be entered
`into the
`program by the mask engineer who
`is most familiar
`
`

`

`5, 206, 582
`
`to FIG. 3, the layout of a wafer is
`with it. Referring
`in a hierarchical form. Each wafer 26 consists
`illustrated
`of a twoMimensional
`array of dice 28. Generally,
`a
`wafer might contain 100-200 dice. Typically, every die
`on a wafer will be the same, although
`it is possible to 5
`have the dice vary from one another. Each die consists
`of an arrangement of modules 30, which can be the
`same or different from one another. A module is defined
`as the largest area that can be covered by the set of
`probe pins in the wafer prober. Each module consists of 10
`one or more devices 32, e. g. transistors, diodes, resis-
`tors, etc. having
`to contact pads
`terminals connected
`the module.
`within
`As a convenient means to enter information
`into the
`file library, the mask engineer can fill out 15
`configuration
`a series of worksheets
`(either on paper or directly into
`computer memory by means of a video display) that are
`related to the tiers of the hierarchy shown
`respectively
`in FIG. 3. One worksheet, referred to as a wafer layout
`worksheet, can describe information
`such as the wafer 20
`dimension, die-to-die distances, and die outlines. Thus,
`the specific location of each
`this worksheet
`identifies
`die relative to a reference position defined by the user.
`This reference position can be on the wafer itself, or at
`a location that is not on the wafer but is fixed relative 25
`thereto. For convenience,
`the positions of the dice, and
`more particularly a specific point on each die such as a
`corner, can be specified by means of a first set of X-Y
`to
`coordinates whose origin
`is the reference position,
`thereby accommodate non-uniform die spacing on the 30
`wafer.
`A second type of worksheet,
`the die layout work-
`the arrangement of modules within
`sheet, can define
`each type of die. In conjunction with this worksheet, a
`to de- 35
`module coordinate worksheet can be employed
`scribe the location of each module within
`the die. In
`the number of
`this worksheet can describe
`addition,
`contact pads,
`their dimensions,
`relative arrangement
`and the distances between contact pads. A precise loca-
`tion on one of the pads, such as its center, can also be 40
`identified for reference purposes. Preferably,
`this loca-
`tion is identified using a second X-Y coordinate designa-
`tor. The origin of this coordinate system could be the
`specific point on the die, e. g. a corner, that is identified
`by means of the first coordinate pair described previ- 45
`ously. Thus, any point on the wafer can be specified by
`means of two vectors,
`the first of which points to a
`particular die and the second of which
`identifies
`the
`the die.
`point within
`Finally, a module design worksheet can be employed 50
`to describe the arrangement and construction of devices
`that are located within each type of module. Each de-
`the module can be labeled, and each of its
`vice within
`to one of the pads in a previ-
`terminals can be assigned
`layout for the module.
`ously defined pad pattern
`In addition to the information describing
`the makeup
`of the wafer, other information describing
`the pin ar-
`rangement for each type of probe card used in the wafer
`in the reference data portion of
`prober can be contained
`file library. For example, each pad in 60
`the configuration
`a given pad pattern can be correlated with one of the
`pins on the probe card as well as its associated contact
`the relay matrix.
`point within
`An advantage of the methodology of the worksheet
`to enter informa- 65
`layout is that it enables the engineers
`to
`that are familiar
`tion and construct
`tests in terms
`them. The engineers can write the reference and test
`either on paper worksheets or
`definition
`information
`
`55
`
`directly onto the video display "worksheet". Once all of
`the worksheets/screens
`have been completed by the
`the information contained
`in them is stored in
`engineers,
`file library 20.
`structured
`the configuration
`files within
`in a manner
`the worksheets are organized
`Preferably,
`to the format of the files in the li-
`which corresponds
`brary. This approach reduces the level of skill required
`to store the information
`in the files in case paper work-
`sheets are used.
`the lay-
`Besides the reference information describing
`out of the wafer and characteristics of the testing equip-
`file library 20 contains test defi-
`ment, the configuration
`nitions or specifications. These specifications define the
`selection of dice and devices where
`is to be
`testing
`carried out, the type of measurements
`to be performed,
`the test conditions for these measurements,
`the format
`for the output
`information and the desired information
`for operator entry. Similar to the reference information,
`the test definitions can be provided by means of suitable
`to the reference
`In contrast
`worksheets.
`information,
`however,
`the test information
`is not provided by the
`it is entered by the device or
`mask designer. Rather,
`process engineer who requires
`the information
`pro-
`vided by the tests to monitor and/or refine the manufac-
`turing process. Each engineer can give each test se-
`quence which he defines a unique name that later ena-
`bles an operator to call up the test as desired.
`Similar to the configuration of the wafer,
`the test
`in a hierarchi-
`is also laid out by the engineer
`sequence
`cal format. The levels of the hierarchy are shown
`in
`FIG. 4, and each can have a corresponding worksheet
`to define the test sequence.
`testing it is not necessary to
`in parametric
`Typically,
`tests on every die within
`the wafer. Rather,
`perform
`testing need only be performed on selected dice at vari-
`to determine
`ous locations within
`the wafer
`certain
`characteristics of the manufacturing process. Therefore,
`a first step in the definition of the test specifications
`is to
`testing is to
`describe those die sites at which parametric
`be carried out. FIG. 5 illustrates an example of a work-
`sheet that is marked to identify the particular dice in the
`wafer that are to be tested. The outline of all of the dice
`is indicated by the solid line 36, and the individual dice
`are defined by the dotted-line
`this out-
`squares within
`line. The selection of the dice to be tested can be indi-
`cated by placing an "X" or similar checkmark within
`In such a case, the
`each desired die on the worksheet.
`dice would be sequentially
`in a predetermined
`tested
`pattern. For example, the wafer prober might start with
`corner of the wafer,
`the die in the upper
`right-hand
`proceed horizontally across the row, step down to the
`next row, and continue along such a path, stopping at
`each selected die in order as it is reached.
`The test shell approach of the present invention offers
`a much greater degree of flexibility
`in the die test se-
`quence, however. Rather than being confined to a lim-
`ited set of predetermined patterns, the dice can be tested
`in any random order. As shown in FIG. 5, each selected
`die to be tested can be sequentially numbered
`in accor-
`dance with any desired test pattern. Thus, it is possible
`to begin the test procedure with dice in the center of the
`wafer, and then proceed to other dice located at the
`periphery of the wafer, for example.
`Once the dice to be tested have been selected,
`the
`specific devices as well as the types of measurements
`that are to be performed on each device within a die are
`in the third and fourth levels of
`specified, as illustrated
`the hierarchy shown in FIG. 4. Basically, each type of
`
`

`

`5, 206,
`582
`
`7
`can be assigned an arbitrary name by the
`measurement
`device engineer, and the devices to which each such
`is to be applied can be indicated on a
`measurement
`suitable worksheet.
`in FIG. 6.
`An example of such a worksheet
`is shown
`The labels of all devices to be tested are listed in a col-
`umn 38 along the left-hand side of the worksheet. These
`labels are preferably specific to a single device on each
`die. A row 40 along the top of the worksheet contains
`the name of each different
`type of measurement
`to be &p
`performed, e. g. gate leakage, drain current, etc. The
`application of a particular measurement
`to a specific
`device can thereby be easily identified by placing an
`"X" at the appropriate
`location in the matrix 42 defined
`by the worksheet. The engineer also selects the order of
`test using this matrix. The specified tests, designated by
`"X", are processed top left to bottom right by rows. All
`tests on the first device in the top row are performed
`before proceeding
`to the next device. This minimizes
`pad contact and prober movement while at the same
`the engineer a high degree of flexibility
`time allows
`unavailable
`the
`in standard probing patterns. Thus,
`task to define a test sequence
`process engineer's
`is not
`in that the device/measurement
`only greatly simplified
`matrix provides a compact overview of the entire test,
`but is made considerably more flexible, too.
`Another worksheet can be used to describe the par-
`ticular test conditions for each named measurement,
`as
`well as to assign a label to the results from each mea-
`surement. For each
`one or
`identified measurement,
`more suitable measurement
`can be chosen
`algorithms
`library 22 to perform
`from the measurement
`algorithm
`that identified measurement.
`In addition, parameters
`for
`the measurement,
`levels, can be speci- 35
`such as voltage
`of the invention,
`fied. In a preferred
`implementation
`in any one of three
`these parameters can be specified
`forms. First, each might be simply
`listed as a fixed,
`numerical value. Secondly, a parameter can be assigned
`a name which is given a numeric value based upon user 40
`defined constants or variables which are given values
`by the user at the time of test execution, or as a result of
`a prior measurement performed on the wafer. Third, the
`parameter can be specified as an arithmetic expression