(12) United States Patent
`US 6,366,108 B2
`(10) Patent N0.:
`O’Neill et al.
`
`(45) Date of Patent: *Apr. 2, 2002
`
`USOO6366108B2
`
`(54)
`
`SYSTEM AND METHOD FOR DETECTING
`DEFECTS WITHIN AN ELECTRICAL
`CIRCUIT BY ANALYZING QUIESCENT
`CURRENT
`
`(75)
`
`Inventors: Peter M. O’Neill, Ft. Collins, CO (US);
`Victor Johansen, Santa Clara; Peter
`Maxwell, Sunnyvale, both of CA (US)
`
`(73)
`
`Assignee: Agilent Technologies, Inc., Palo Alto,
`CA (US)
`
`Notice:
`
`This patent issued on a continued pros-
`ecution application filed under 37 CFR
`1.53(d), and is subject to the twenty year
`patent
`term provisions of 35 U.S.C.
`154(a)(2).
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21)
`
`(22)
`
`(51)
`
`(52)
`
`(58)
`
`(56)
`
`EP
`EP
`EP
`
`Appl. No.: 09/203,295
`
`Filed:
`
`Dec. 1, 1998
`
`Int. Cl.7 ................................................ G01R 31/02
`
`US. Cl.
`
`........................................ 324/763; 324/765
`
`Field of Search ................................. 324/763, 765,
`324/768, 769, 771
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5,670,892 A *
`5,675,253 A
`5,784,166 A
`5,914,615 A *
`
`9/1997 Sporck ....................... 324/765
`10/1997 Smith, et a1.
`.
`324/306
`
`7/1998 Sogard .........
`356/363
`6/1999 Chess ......................... 324/765
`
`FOREIGN PATENT DOCUMENTS
`0694961 A1
`7/1995
`........... H01L/21/66
`
`0840227 A1
`10/1997
`..... G06F/11/24
`1008857
`8/1999
`........... GOlR/31/30
`
`OTHER PUBLICATIONS
`
`US. Patent Application Ser. No. 08/841,175 (Now US.
`Patent 5,914,615), entitled “A Method of Improving the
`Quality and Efficiency of IDDQ testing,” and filed Apr. 29,
`1977, by Chess.
`
`Gattiker, et al., “Current Signatures for Production Testing”,
`IEEE 1996, pp. 25—28.
`
`Gattiker, et al., “Current Signatures”, IEEE, 14’” VLSI Test
`Symposium—1996, pp. 112—117.
`
`* cited by examiner
`
`Primary Examiner—Safet Metj ahic
`Assistant Examiner—James C Kerveros
`
`(74) Attorney, Agent, or Firm—Alex J. Neudeck
`
`(57)
`
`ABSTRACT
`
`in general, provides for a testing
`The present invention,
`system and method for detecting defects within a circuit. A
`current signature of the quiescent current of the circuit is
`determined, and certain constant values are calculated based
`on the current signature using a linear iterative regression. A
`defect free state for the circuit associated with a minimum
`
`quiescent current (IDDQ) is then determined. The IDDQ of the
`circuit for this state is measured, and a signal indicating the
`IDDQ at this state is used along with the aforementioned
`constant values to create upper and lower threshold values.
`Thereafter, signals indicating the value of IDDQ for a plu-
`.
`rahty of other states are compared to the upper and lower
`threshold values. The circuit is determined to be defective if
`
`the values of any of the signals is greater than the upper
`threshold value or is less than the lower threshold value.
`
`21 Claims, 7 Drawing Sheets
`
`
`
`10
`
`\
`
`Power Supply
`Unit
`
`“17
`
`
`
`r”
`J79
`
`
`
`
`
`
`
`25
`Analyzer 4; Current Meter
`
`99
`
`K1s
`
`
`
`F15
`16\
`21
`
`
`State Generator
`
`
`
`
`
`
`\
`
`Linear Exhibit 1019
`
`Circuit
`
`
`
`
`
`

`

`US. Patent
`
`Apr. 2, 2002
`
`Sheet 1 0f 7
`
`US 6,366,108 B2
`
`
`
`Power Supply
`Unit
`
`17
`
`
`Analyzer
`
`Current Meter
`
`
`
`
`State Generator
`Circuit
`14
`
`
`

`

`US. Patent
`
`Apr. 2, 2002
`
`Sheet 2 0f 7
`
`US 6,366,108 B2
`
`30
`
`3N
`
`32
`
`Processing
`
`Element
`
`27
`
`Memory
`
`
`n
`
`
`
`Local Interface
`
`34
`
`Input
`Device
`
`Display
`
`Interface
`
`Parameter
`
`36
`
`

`

`US. Patent
`
`Apr. 2, 2002
`
`Sheet 3 0f 7
`
`US 6,366,108 B2
`
`
`Select a
`new circuit
`
`
`
`
`
`
`Determine state(s)
`associated with
`
`minimum test signal
`value
`
`
`
`Measure value of
`
`test signal at a
`plurality of states
`
`
`Determine maximum test signal
`value and minimum test signal
`
`
`value and plot the maximum test
`
`signal value versus the minimum
`test signal value
`
`
`
`
`
` All circuits
`
`
`analyzed?
`
`64
`
`
`
`Determine
`
`outlier margin
`
`
`value, m, and b
`
`
`
`Select a minimum
`
`Iddq state
`
`67
`
`Fig. 3A
`
`

`

`US. Patent
`
`Apr. 2, 2002
`
`Sheet 4 0f 7
`
`US 6,366,108 B2
`
`10
`\
`
`Select a circuit
`
`to be tested
`
`Determine the test
`
`signal value at the
`selected minimum
`
`
`
`
`72
`
`
`
`
`lddq state
`
`75
`
`Determine upper and
`lower threshold values
`
`77
`
`Change state of
`circuit to a new state 81
`
`
`
`
`Generate new test
`
`signal indicating lddq at
`the new state
`
`
`83
`
`
`
`Compare the new
`test signal to the
`
`threshold values
`
`
`
`85
`
`
` Defect
`Yes
`Detected?
`
`
`
`91
`
`Indicate circuit
`
`is defective
`
` More
`states to be
`
`tested?
`
`
`No
`97
`
`
`More
`circuits to be
`
`
`tested?
`
`
`
`
`m N°
`
`Yes
`
`Fig. 33
`
`

`

`US. Patent
`
`Apr. 2, 2002
`
`Sheet 5 0f 7
`
`US 6,366,108 B2
`
`Test Signal
`Value
`
`(max)
`
`(min)
`
`States
`
`

`

`US. Patent
`
`Apr. 2, 2002
`
`Sheet 6 0f 7
`
`US 6,366,108 B2
`
`Y
`
`Maximum Test
`
`Signal Value
`
`Minimum Test
`
`X
`
`Signal Value
`
`

`

`US. Patent
`
`Apr. 2, 2002
`
`Sheet 7 0f 7
`
`US 6,366,108 B2
`
`Maximum Test
`
`Signal Value
`
`Minimum Test
`
`X
`
`Signal Value
`
`

`

`US 6,366,108 B2
`
`1
`SYSTEM AND METHOD FOR DETECTING
`DEFECTS WITHIN AN ELECTRICAL
`CIRCUIT BY ANALYZING QUIESCENT
`CURRENT
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`
`The present invention generally relates to quiescent cur-
`rent testing and, more particularly, to a system and method
`for detecting defects within a complementary metal oxide
`silicon (CMOS) circuit by measuring and characterizing the
`power supply current conducted by the circuit in multiple
`quiescent states.
`2. Related Art
`
`An ideal complementary metal oxide silicon (CMOS)
`integrated circuit conducts a negligible amount of current
`when the circuit is in standby or a quiescent state. Therefore,
`when a CMOS circuit is not switching states, only a small
`amount of quiescent current should be conducted by the
`circuit. The quiescent current, commonly referred to as
`“IDDQ,” is composed primarily of leakage current. A defec-
`tive circuit may draw a significantly larger amount of
`quiescent current than a non-defective circuit.
`
`Typical IDDQ testing includes setting a threshold value of
`IBBQ in which the circuit being tested is failed if the IDDQ
`conducted by the circuit exceeds the threshold value. In this
`regard, input vectors drive the circuit’s nodes to predeter-
`mined states, and the IDDQ is measured while the circuit’s
`nodes are held in the predetermined states. IDDQ testing may
`be done at a single state or it may include stepping through
`many different input test vectors to test various states. The
`test vectors can be generated by automatic test pattern
`generation (ATPG) software tools or by integrated circuit
`designers.
`
`One of the difficulties of IDDQ testing is setting the
`threshold value. A circuit that draws more current than the
`
`threshold value of IDDQ for any input test vector is declared
`defective. Acircuit that draws less current than the threshold
`
`value of IDDQ is considered non-defective. If the threshold
`value is set too high, then circuits that contain defects may
`be considered non-defective. If the threshold value is too
`
`low, then circuits that are free of defects may fail the IDDQ
`test. This increases the cost of the circuits considered
`non-defective. Therefore, the determination of the threshold
`value for IDDQ testing usually involves a tradeoff between
`the quality and the cost of the circuits which pass IDDQ
`testing.
`As the scale of CMOS circuits is increasingly reduced to
`increase speed and density and to decrease cost, the back-
`ground current drawn by the CMOS circuits is increased. As
`known in the art, IDDQ consists of two components (1) defect
`current, which is the current drawn by a circuit due to defects
`within the circuit and (2) background current, which is IDDQ
`minus the defect current. The scale of CMOS circuitry has
`reached levels where the magnitude of the background
`current is comparable to or even exceeds the defect current.
`Therefore, it has become more difficult to determine whether
`a variation in IDDQ is due to a variation in background
`current or is due to a defect, thereby frustrating the process
`of identifying which circuits are defective.
`Process variations of the fabrication of electrical circuits
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`further complicate the determination of the IDDQ threshold
`value. Process variations are differences that exist between
`
`65
`
`individual circuits of the same circuit design. Process varia-
`tions can affect the quiescent current drawn by the circuits.
`
`2
`For example, two integrated circuits of the same design can
`draw different IDDQ values for the same set of input test
`vectors due to process variations between the two circuits.
`Gattiker and Maly (A. E. Gattiker and W. Maly, “Current
`Signatures”, Proc. VLSI Test Symposium, pp. 112—117,
`1996) have proposed a method which eliminates some of the
`threshold selection problems. Traditionally,
`testing of a
`circuit ends as soon as the circuit fails the IDDQ test. Gattiker
`and Maly propose that
`IDDQ values be measured for a
`complete set of input test vectors. A complete set of input
`test vectors include enough test vectors to completely exer-
`cise the functionality of the circuitry within the circuit being
`tested. From the measured values of IDDQ, a current signa-
`ture is generated. The current signature includes an ordering
`of the IDDQ measurements from the smallest value to the
`largest value. Gattiker and Maly claim that the magnitude of
`the measurements is not as important as the shape of a plot
`of the current signature. If there are no large jumps in the
`plot of the current signature, then the circuit is designated as
`non-defective. If the plot of the current signature includes
`any significant jumps or discontinuities, then the circuit is
`designated as defective.
`The IDDQ signature concepts proposed by Gattiker and
`Maly represent important findings in IDDQ testing analysis.
`However, these concepts cannot be directly implemented
`into present-day integrated circuit manufacturing environ-
`ments. Testing methods using the Gattiker and Maly IDDQ
`signature concepts require a complete set of input vector test
`settings to be applied to the integrated circuit under test and
`the resultant measured values of IDDQ for each input vector
`setting to be analyzed. Determination of the values of IDDQ
`for a complete set of input vector settings takes too long to
`implement in circuit manufacturing environment at a rea-
`sonable cost.
`
`It is desirable to provide a system and method for IDDQ
`testing which overcomes the limitations of present IDDQ
`testing methods using a single threshold test. Furthermore, it
`is desirable that
`the method of IDDQ testing be easily
`implemented into existing circuit manufacturing environ-
`ments by not requiring excessive storage and analysis of
`measured values of IDDQ.
`SUMMARY OF THE INVENTION
`
`The present invention overcomes the inadequacies and
`deficiencies of the prior art as discussed herein. The present
`invention provides a system and method for detecting
`defects in electrical circuits by analyzing quiescent current.
`In general, the present invention utilizes a circuit, a power
`supply unit, a current meter, and a analyzer. The power
`supply unit is connected to the circuit and transmits supply
`current to the circuit. The current meter measures the supply
`current and transmits a first signal and a second signal
`respectively indicating a first value and a second value of the
`supply current. The analyzer receives the first parameter and
`determines a threshold value based on the first parameter
`value. The analyzer then receives the second signal and
`compares the second signal to the threshold value. The
`analyzer determines whether a defect is detected based on
`the comparison of the second signal to the threshold value.
`In accordance with another
`feature of the present
`invention, the analyzer also determines a second threshold
`value based on the first signal. The analyzer can then
`determine whether a defect is detected by comparing the
`second signal to the second threshold value.
`In accordance with another
`feature of the present
`invention, the analyzer calculates the threshold values based
`
`

`

`US 6,366,108 B2
`
`3
`on predetermined constants. To determine the predetermined
`constants, the values of signals indicating the supply current
`values for a plurality of states and a plurality of circuits are
`measured. Then, selected values of the signals are then
`plotted to create a current signature of the circuits. A 5
`regression is then used to remove outliers from the plot and
`to fit a curve or line to the plotted points. The predetermined
`constants are then determined from the fitted curve or line,
`and the predetermined constants are used by the analyzer to
`determine the threshold values for each of the circuits tested.
`
`10
`
`4
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`In general, the present invention provides a testing system
`and method for detecting defects within an electrical circuit.
`In this regard, upper and lower threshold values for the
`quiescent current (IDDQ) of the circuit are determined, and a
`signal indicating the IDDQ value for the circuit at a plurality
`of states is compared to the upper and lower threshold
`values. A defect is detected when the signal corresponds to
`a value greater than the upper threshold value or less than the
`lower threshold value.
`
`15
`
`20
`
`FIG. 1 depicts a testing system 10 in accordance with the
`preferred embodiment of the present invention. The system
`10 includes a circuit 14, such as a complementary metal
`oxide silicon (CMOS) integrated circuit, that is to be tested
`for defects. The state of the circuit 14 is controlled by a state
`generator 15, which transmits input signals via connections
`16 to the circuit 14. As known in the art, the values of the
`input signals can be adjusted to transition the circuit 14 into
`different states. The number of connections 16 may vary
`depending on the number of states that are to be tested.
`
`25
`
`A power supply unit 17 is designed to transmit supply
`current to a current meter 18 via connection 19. The current
`
`meter 18 is designed to pass the supply current to circuit 14
`via connection 21 and to provide a test signal to an analyzer
`22 via connection 25. The current meter 18 may be included
`in the power supply unit 17 or may be in a stand alone
`configuration. The test signal transmitted to the analyzer 22
`by the current meter 18 indicates the value of IDDQ (which
`is the supply current being provided to the circuit 14 via
`connection 25 when the circuit 14 is in a quiescent state). For
`example, in the preferred embodiment, the current meter 18
`is designed to produce a voltage signal on connection 25
`proportional to the supply current being transmitted to the
`circuit 14 via connections 19 and 21. However,
`the test
`signal may be other types of signals as long as it indicates
`the value of IDDQ. For example, it is possible for the test
`signal to be a current signal with a current value matching
`or corresponding with the current value of IDDQ. It is also
`possible for the test signal to be a digital signal having a
`digital value corresponding with the current value of IDDQ.
`The analyzer 22 is designed to receive the test signal and
`to detect defects in the circuit 14 based on the test signal.
`The analyzer 22 can be implemented in software, hardware,
`or a combination thereof. In the preferred embodiment, as
`illustrated by way of example in FIG. 2, the analyzer 22 is
`implemented in software and stored in memory 30 of a
`computer system 31.
`
`Note that the analyzer 22 can be stored and transported on
`any computer-readable medium for use by or in connection
`with an instruction execution system, apparatus, or device,
`such as a computer-based system, processor-containing
`system, or other system that can fetch the instructions from
`the instruction execution system, apparatus, or device and
`execute the instructions. In the context of this document, a
`“computer-readable medium” can be any means that can
`contain, store, communicate, propagate, or transport
`the
`program for use by or in connection with the instruction
`execution system, apparatus, or device. The computer read-
`able medium can be, for example but not limited to, an
`electronic, magnetic, optical, electromagnetic, infrared, or
`semiconductor system, apparatus, device, or propagation
`medium. More specific examples (a non-exhaustive list) of
`the computer-readable medium would include the follow-
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`The present invention can also be viewed as providing a
`method for detecting defects within circuits. Briefly
`described, the method can be broadly conceptualized by the
`following steps: providing a circuit; measuring a value of a
`supply current associated with the circuit when the circuit is
`in a first state; determining a threshold value based on the
`value of the supply current measured in the measuring step;
`receiving a signal indicating another value of the supply
`current when the circuit is in a second state; comparing the
`signal to the threshold value; and detecting a defect in the
`circuit based on the comparing step.
`The present invention has many advantages, a few of
`which are delineated hereafter, as mere examples.
`An advantage of the present invention is that defects in
`circuits can be detected by comparing the quiescent current
`associated with circuit to threshold values. These compari-
`sons can be achieved without determining the value of the
`quiescent current,
`thereby making the comparisons rela-
`tively fast.
`Another advantage of the present invention is that the cost
`associated with quiescent current testing can be significantly
`reduced.
`
`Another advantage of the present invention is that quies-
`cent current
`testing can be achieved by comparing the
`quiescent current of a circuit to thresholds that are uniquely
`calculated for each circuit. Therefore, the effects of fluctua-
`tions in background current are reduced.
`Other features and advantages of the present invention
`will become apparent to one skilled in the art upon exami-
`nation of the following detailed description, when read in
`conjunction with the accompanying drawings. It is intended
`that all such features and advantages be included herein
`within the scope of the present invention, as is defined by the
`claims.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`The invention can be better understood with reference to
`
`the following drawings. The elements of the drawings are
`not necessarily to scale relative to each other, emphasis
`instead being placed upon clearly illustrating the principles
`of the invention. Furthermore, like reference numerals des-
`ignate corresponding parts throughout the several views.
`FIG. 1 depicts a block diagram illustrating a testing
`system in accordance with the present invention.
`FIG. 2 depicts a block diagram illustrating a computer
`system employing the analyzer of FIG. 1.
`FIGS. 3A and 3B depict a flow chart illustrating the
`architecture, functionality, and operation of the testing sys-
`tem of FIG. 1.
`
`FIG. 4 depicts a graph of the test signal value versus state
`for a circuit being tested by the testing system of FIG. 1.
`FIG. 5 depicts a graph of the maximum test signal value
`versus the minimum test signal value for each circuit being
`measured to derive the outlier margin value and the values
`of m and b.
`
`FIG. 6 depicts the graph of FIG. 5 after linear regression.
`
`

`

`US 6,366,108 B2
`
`5
`
`ing: an electrical connection (electronic) having one or more
`wires, a portable computer diskette (magnetic), a random
`access memory (RAM) (magnetic), a read-only memory
`(ROM) (magnetic), an erasable programmable read-only
`memory (EPROM or Flash memory) (magnetic), an optical
`fiber (optical), and a portable compact disc read-only
`memory (CDROM)
`(optical). Note that
`the computer-
`readable medium could even be paper or another suitable
`medium upon which the program is printed, as the program
`can be electronically captured, via for
`instance optical
`scanning of the paper or other medium,
`then compiled,
`interpreted or otherwise processed in a suitable manner if
`necessary, and then stored in a computer memory. As an
`example, the analyzer 22 may be magnetically stored and
`transported on a conventional portable computer diskette.
`The preferred embodiment of the computer system 31 of
`FIG. 2 comprises one or more conventional processing
`elements 32, such as a digital signal processor (DSP), that
`communicate to and drive the other elements within the
`
`computer system 31 via a local interface 33, which can
`include one or more buses. Furthermore, an input device 34,
`for example, a keyboard or a mouse, can be used to input
`data from a user of the computer system 31, and screen
`display 35 or a printer 36 can be used to output data to the
`user. A disk storage mechanism 37 can be connected to the
`local interface 33 to transfer data to and from a nonvolatile
`
`disk (e.g., magnetic, optical, etc.). Furthermore, an test
`signal interface 39 receives the test signal from connection
`25 (FIG. 1) and interfaces the test signal with the local
`interface 33. It should be noted that input device 34, display
`35, printer 36, and disk 37 are optional and are not a part of
`the preferred embodiment, although other embodiments may
`include these features.
`
`The analyzer 22, which will be discussed in further detail
`hereinafter, is configured to calculate or otherwise determine
`upper and lower threshold values for the test signal. The
`analyzer 22 is then designed to compare the test signal to the
`upper and lower threshold values and to determine that the
`circuit 22 is defective when the test signal is greater than the
`upper threshold value or is less than the lower threshold
`value.
`
`The analyzer 22 preferably utilizes a predetermined for-
`mula to calculate the upper and lower threshold values. In
`the preferred embodiment, this predetermined formula is
`modeled from the equation of a line. In this regard,
`the
`formula used by the analyzer 22 is:
`
`IDDQ,max=mX1DDQ,min+b
`
`Equation (1)
`
`where IDDQMHX is the maximum measured test signal value
`for the circuit 14 in a defect free state,
`IDDQMl-n is the
`minimum measured test signal value for the circuit 14 in a
`defect free state, m is a predetermined constant, and b is a
`predetermined constant. These values are predetermined in
`that they are determined before the first circuit 14 is tested.
`Determination of these values will be discussed in further
`
`detail hereinafter in the Operation section.
`The upper threshold value is preferably defined as the
`value of IDDQMM plus an outlier margin value, and the lower
`threshold value is preferably defined as IDDQm-n minus the
`outlier margin value. The addition and subtraction of the
`outlier margin value in calculating the threshold values
`allows small variations in IDDQ to exist without incorrectly
`declaring the circuit 14 as defective when the small varia-
`tions do not result from a defect. In other words, the addition
`and subtraction of the outlier margin value allows for small
`variations to occur which are attributable to measurement
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`6
`inaccuracies and/or process variations instead of circuit
`defects. The outlier margin value in the preferred embodi-
`ment is three times the standard of deviation of the residuals
`
`of the regression, although the outlier margin value can be
`set to other values. Calculation of the outlier margin value
`and performance of the regression will be discussed in
`further detail hereinafter.
`
`Once IDDQMM, IDDQm-n, and the outlier margin value
`have been determined,
`the analyzer 22 is configured to
`calculate the upper and lower threshold values. The analyzer
`22 is designed to then compare the upper and lower thresh-
`old values to the test signal transmitted on connection 25 to
`detect defects within the circuit 14.
`
`OPERATION
`
`The preferred use and operation of the testing system 10
`and associated methodology are described hereafter.
`Before the circuit 14 is tested, the behavior of the circuit
`14 is modeled to determine the outlier margin value and the
`values of m and b of Equation (1). In this regard, the test
`signal value of a plurality of circuits 14 (each circuit 14
`having the same design) is measured at a plurality of states
`for each circuit 14, as shown by blocks 52 and 55 of FIG.
`3A. FIG. 4 depicts the current signature for one of the
`circuits 14. Generally, the current signature is the shape of
`the curve representing the current versus state of a circuit 14
`or is any set of parameters that represent the shape of the
`curve. Measuring and plotting in FIG. 4 test signals from a
`plurality of circuits 14 characterizes the behavior of IDDQ
`over a range of manufacturing (i.e., process) variation. The
`number of states measured for each circuit 14 can vary.
`The maximum test signal value measured for each circuit
`14 at any one of the measured states is preferably plotted
`versus the minimum test signal value measured for each
`circuit 14 at any one of the measured states, as shown by
`FIG. 5 and blocks 57 and 61 of FIG. 3A. In other words,
`each dot of FIG. 5 represents the maximum test signal value
`measured at any state for a single circuit 14 versus the
`minimum test signal value measured at any state for the
`single circuit 14. For example, using the data shown in FIG.
`4, the value of the test signal at state 9 versus the value of
`the test signal at state 14 would comprise one dot in FIG. 5.
`The graph of FIG. 5 is preferably used to determine the
`outlier margin value in block 64. The outlier margin value is
`preferably three times the standard deviation of the regres-
`sion residuals of the points plotted in FIG. 5. The standard
`deviation can be calculated through techniques well known
`in the art. In the preferred embodiment, the standard devia-
`tion is calculated by performing an iterative linear regression
`(removing outliers at each iteration), although non-linear
`regression may also be used. As known in the art, an outlier
`is defined as points outside of the distribution of a popula-
`tion. The iterations of the regression terminate or stop when
`all remaining residuals are determined to be from a single
`population. Such regression techniques are well known in
`the art.
`
`For illustrative purposes, assume that points 41 of FIG. 5
`are determined to be outliers because of their respective
`position from the other points in the graph. It is likely that
`points 41 are located significantly far from the line estab-
`lished by the majority of the points on the graph due to
`defects and/or errors in measurement of the IDDQ values
`drawn by the circuits 14 associated with the points 41. Points
`41 are identified as outliers and are,
`therefore, removed
`during the regression such that
`the graph of FIG. 6 is
`produced. Once all of the outliers have been removed and
`
`

`

`US 6,366,108 B2
`
`7
`the linear regression is complete, the values of m and b that
`best represent
`the circuit’s defect free behavior can be
`determined. In this regard, In is the slope (i.e., AY/AX) of the
`fitted line, and b is the y-intercept of the fitted line. It should
`be noted that other techniques may be utilized for removing
`outliers and for fitting a curve or line to the sample points of
`FIG. 6.
`
`After calculating the outlier margin value and the values
`of m and b, these values are stored in memory 30 of the
`computer system 31 (FIG. 2). Then, the inputs to the circuit
`14 shown in FIG. 1 are set by the state generator 16 to put
`the circuit 14 into a minimum IDDQ state. The minimum
`IDDQ state is selected at block 67 of FIG. 3A and is the state
`where the plurality of circuits 14 measured to derive FIG. 6
`draw the smallest IDDQ value, as determined at block 69. The
`smallest IDDQ value may change from circuit 14 to circuit
`14, but the state at which the smallest IDDQ values occur
`should be constant. This state is the minimum IDDQ state.
`For example, in FIG. 4, the minimum IDDQ state is state 14
`since state 14 corresponds with the lowest measured value of
`IDDQ.
`It should be noted that due to process variations and/or
`other factors, it is possible that the same state for each circuit
`14 does not produce a minimum IDDQ for the circuit 14. It
`is sufficient for the purposes of the present invention that
`only a significant number of circuits 14 produce a minimum
`IDDQ at
`the state selected as the minimum IDDQ state.
`Furthermore, it is possible that multiple states may produce
`the minimum IDDQ value. In this situation, any one of the
`states producing the minimum IDDQ value or a value close
`to the minimum IDDQ value may be selected as the IDDQ
`minimum state.
`
`the state
`When a particular circuit 14 is to be tested,
`generator 15 produces values on connections 16 that place
`the circuit in the minimum IDDQ state. The analyzer 22 then
`reads the test signal on connection 25 and determines the
`value of the test signal at the minimum IDDQ state, as shown
`by blocks 72 and 75 of FIG. 3B. This value of the test signal
`is IDDQm-n of Equation (1). Then, the analyzer 22 calculates
`the upper and lower threshold values for the circuit 14 at
`block 77. In this regard, the analyzer 22 subtracts the outlier
`margin value from IDDQMm to determine the lower thresh-
`old. The analyzer 22 then determines IDDQm-n via Equation
`(1) where IDDQMm, b and m are now known values. The
`analyzer 22 adds the outlier margin value to IDDQMM to
`determine the upper threshold.
`The state of the circuit 14 is then changed in block 81 of
`FIG. 3B via the inputs from signal generator 15 to any
`desirable testing state. The analyzer 22 compares the test
`signal currently generated by the current meter 18 to the
`upper and lower threshold values, as shown by blocks 83
`and 85. The analyzer 22 detects a defect at block 88 if the
`test signal is greater than the upper threshold value or if the
`test signal is less than the lower threshold value. No defect
`is detected if the test signal is less than the upper threshold
`value and greater than the lower threshold value. If a defect
`is detected, then the analyzer 22 preferably indicates via
`display 35 or printer 36 (FIG. 2) that a defect has been
`discovered, as shown by block 91 of FIG. 3B. Furthermore,
`pursuant
`to conventional manufacturing techniques,
`the
`defective circuit is preferably marked as defective or sepa-
`rated from the other circuits that have not been determined
`to be defective.
`
`It should be noted that many hardware comparators exist
`in the art for determining whether one signal is greater than
`another signal. If desired, the analyzer 22 may include or
`
`5
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`8
`employ such a comparator to determine whether the test
`signal exceeds the threshold values.
`In this regard,
`the
`analyzer 22 preferably transmits an analog signal to the
`comparator. The analog signal preferably has a voltage or
`current value proportional to the value of one of the thresh-
`old values. The comparator, through techniques known in
`the art, can then determine whether the signal corresponding
`with the threshold value is greater than the test signal
`without knowing or discovering the actual values of either
`the test signal or the threshold value. It should be noted,
`however, that it is also possible to perform the comparisons
`in software or a combination of hardware and software.
`
`is detected at the
`After determining whether a defect
`current state, the state of the circuit 14 is changed by the
`state generator 15, and the test signal at this new state is
`again tested for defects. As shown by block 94 of FIG. 3B,
`this process is continued until a desired number of states
`have been tested or until a defect is detected. If no defects
`
`have been detected at any of the states, then the analyzer 22
`determines that the circuit is non-defective. However, if a
`defect is detected at any of the states (or, in the alternative,
`if a defect is detected at a predetermined number of states),
`then the analyzer 22 determines that
`the circuit 14 is
`defective.
`
`Note that the value of the test signal does not actually
`have to be determined in comparing the test signal to the
`upper and lower threshold values. Only a determination as
`to whether the test signal is greater than or less than the
`threshold values needs to be made. Making such a determi-
`nation is much faster than determining the value of the test
`signal. Therefore, a large number of states can be tested by
`the analyzer 22 in a relatively short time, thereby making
`IDDQ testing for a large number of states feasible.
`After the circuit 14 has been tested by the analyzer 22, the
`circuit 14 is then replaced by a new circuit 14, as shown by
`blocks 97 and 72 of FIG. 3B. The new circuit 14 is then
`
`tested according to the techniques described hereinabove. As
`long as the new circuit 14 has the same design as the original
`circuit 14, the same values of the outlier margin value and
`of m and b can be used in testing the new circuit 14.
`However, new values of IDDQMm an