IOC Datasheet
`
`Part No 0460,018
`Issue No 1.0
`30 September 1986
`
`_,
`i
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`1
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`•
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`I
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`II ·-
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`SCEA Ex. 1053 Page 1
`
`

`
`© Copyright Acorn Computers Limited 1986
`
`Neither the whole nor any part of the information contained in, or the product described in, this manual may be
`adapted or reproduced in any material form except with the prior written permission of the copyright holder.
`
`The product described in this manual is subject to continuous developments and improvements. All particulars of the
`product and its usc contained in this manual are given by Acorn Computers in good faith. However, all warranties
`implied or expressed, including but not limited to implied warranties or merchantability or fitness for purpose, are
`excluded.
`
`This manual is intended only to assist the reader in the usc of the product. Acorn Computers shall not be liable for any
`loss or damage arising from the use of any information in this manual, or any error or omission in such information, or
`any incorrect usc of the product.
`
`ISBN 1 85250 026 3
`
`Published by:
`Acorn Computers Limited, Fulbourn Road, Cherry Hinton, Cambridge CB 1 4JN, UK
`
`II
`
`IOC Datasheet
`
`·. •; '"'
`
`(!"J
`
`i
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`SCEA Ex. 1053 Page 2
`
`

`
`2
`3
`4
`5
`7
`8
`8
`8
`9
`10
`10
`10"
`11
`11
`11
`11
`11
`12
`12
`12
`12
`12
`12
`13
`13
`14
`14
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`22
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`23
`
`iii
`
`Contents
`
`1. Introduction
`2. Block diagram
`3. Functional Diagram
`4 .. Description of Signals
`5. Programming Model
`5.1 Access Speed
`5.2 Addresses
`5.3 Data
`6. Internal Registers
`6.1 Control Register
`6.1.1 Control register read
`6.1.2 Control register write
`6.2 Keyboard Asynchronous Receiver Transmitter (KART)
`6.2.1 Serial Tx Data regi:ster write
`6.2.2 Serial Rx Data read
`6.2.3 Initialisation
`6.2.4 Receive Interrupt
`6.3 Interrupt Registers
`6.3.1 Internal Interrupt Events
`6.3.2 External Interrupt Events
`6.3.3 Level Interrupts
`6.3.4 Latched Interrupts
`6.3.5 Synchronisation
`6.3.6 IRQ Status A register read
`6.3.7 IRQ Status B register read
`6.3.8 FIQ Status register read
`6.3.9 IRQ Clear register write
`6.3.10 Interrupt Request registers read
`6.3.11 Interrupt Mask registers read/write
`6.4 Counters
`6.4.1 Register actions
`6.4.2 Counter schematic
`6.4.3 Counter Registers
`6.4.4 Counters 0 and 1
`6.4.5 Counter 2 (BAUD)
`6.4.6 Counter 3 (KART)
`7. Peripherals
`8. ARM/IO Interface
`8.1 Peripheral Address and Data
`8.1.1 Peripheral Write Cycles
`8.1.2 Peripheral Read Cycles
`8.2 Peripheral Select Lines
`8.3 Multiple 10 Controllers
`8.4 IO Grant Line
`9. Reset and Power-on
`10. IO-Cycle State Machine
`11. DC Parameters
`11.1 Absolute Maximum Ratings
`1 L2 DC Operating Conditions
`
`JOC Datasheet
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`'U
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`...
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`L.
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`1: -·
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`SCEA Ex. 1053 Page 3
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`

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`'C.-
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`--
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`~
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`11.3 DC Characteristics
`12. AC Parameters
`12.1 Internal Register Read Timings
`12.2 Internal Register Write Timings
`12.3 General Timing For Cycle Types 0, 1 and 2
`12.4 General Timings for Cycle Type 3 (Synchronous)
`12.5 Cycle Types 0, I, 2 Common timing
`I2.5.I Cycle Start
`12.5.2 Cycle End
`I2.6 Read and Write Buffer Enables
`I3. Appendix A
`I Cycle Type 0 Read
`2 Cycle Type 0 Write
`3 Cycle Type I Read
`4 Cycle Type I Write
`5 Cycle Type 2 Read
`6 Cycle Type 2 Write
`7 Cycle Type 3 Read
`8 Cycle Type 3 Write
`14. Packaging
`
`24
`26
`28
`29
`30
`3I
`32
`32
`33
`34
`35
`35
`35
`36
`36
`37
`37
`38
`39
`40
`
`@:
`
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`IOC Datasheet
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`SCEA Ex. 1053 Page 4
`
`

`
`SCEA Ex. 1053 Page 5
`
`

`
`1. Introduction
`
`The Input Output Controller (IOC) is a member of the Acorn RISC Machine (ARM) support chip set, and
`interfaces directly with the Memory Controller (MEMC) and the Video Controller (VIDC) to provide a
`unified view of interrupts and peripherals within an ARM based system. IOC manages an 8 to 32 bit IO
`data bus to which peripheral controllers may be connected, provides a set of internal functions, and controls
`the access cycles to the external peripherals. The internal functions include timers, a serial keyboard
`interface, and interrupt control logic to satisfy the basic requirements of a computer system. The peripheral
`timing cycles allow standard peripheral controllers from a wide range of manufacturers to be interfaced
`without any additional logic. A flexible control port offers a number of general purpose input/output pins.
`
`FEATURES
`
`(!:.
`
`~
`~
`
`~~·
`
`~
`
`Bi-directional serial keyboard interface
`
`6 Programmable bi-directional control pins
`
`Interrupt mask, request and status registers for IRQ and FIQ
`
`* Power-on Reset Control
`*
`4 independent 16 bit programmable counters
`*
`*
`*
`*
`*
`*
`*
`7 external peripheral selects
`* ARMJIO bus interface control
`* Expansion bus buffer control
`* Fabricated in CMOS for low power consumption
`
`14 level-triggered interrupt inputs
`
`2 edge-triggered interrupt inputs
`
`4 programmable peripheral cycles
`
`2
`
`IOC Datasheet
`
`SCEA Ex. 1053 Page 6
`
`

`
`tl
`
`J
`
`2. Block diagram
`
`R
`E
`F
`8
`M
`
`R
`C w s
`I
`
`I
`I
`0
`0
`R W
`B G R
`L T
`0 T(0:1] E E
`
`CLK8
`CLK2
`WBE
`
`RBE
`
`STATE
`Machine
`
`A(2:6]
`
`Register Decoder
`
`8(0:2]
`
`Bank
`Decode
`
`KART
`control
`
`T
`I
`m
`e
`r
`0
`
`T
`i
`m
`e
`r
`1
`
`T
`i
`m
`e
`r
`2
`
`T
`i
`m
`e
`r
`3
`
`IL(0:7]
`
`IF
`
`IR
`
`FH(0:1]
`
`FL
`
`POR
`
`S(1 :7]
`
`SEXT
`
`KIN
`
`KOUT
`
`C[O:S]
`
`RST
`
`JOC Datasheet
`
`3
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`i
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`SCEA Ex. 1053 Page 7
`
`

`
`3. Functional Diagra1n
`
`I'
`
`ARM
`Interface
`
`A <
`
`-
`
`--
`
`"I(
`
`Data Bus
`Buffer
`Control
`
`MEMC
`Interface
`
`[
`
`"""'
`
`Power [
`
`"Y
`
`...
`)
`...
`)
`...
`)
`)
`" ......
`
`A[2:6]
`
`B[0:2]
`
`T[O:l]
`
`D[0:7]
`rs
`R/W
`
`TIL
`
`WllE
`
`RBE
`
`IOGT
`
`REFSM
`wi«5
`
`-..
`
`IRQ
`
`FIQ
`
`VDD(2)
`
`VSS (2)
`
`......
`
`-RST
`
`IOC
`
`CLK8
`CLK2
`BAUD
`
`srt:7l
`
`~
`
`K rr~ro:7l
`
`IF
`IR
`
`A
`
`K FH[O:ll
`" FL
`
`......
`
`SEXT
`RE
`wr~
`
`A
`
`C[O:S]
`
`-y
`
`KOUT
`
`KIN
`
`POR
`
`4
`
`IOC Datasheet
`
`J Peripheral timing
`
`Clocks
`
`Peripheral
`Selects
`
`Peripheral
`Interrupt
`Inputs
`
`timing
`
`General 10 Port
`
`J Peripheral Data
`J Keyboard
`
`Interface
`
`Power ON Control
`
`~·
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`~~
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`~I
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`~~I
`[
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`-
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`SCEA Ex. 1053 Page 8
`
`

`
`'
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`•
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`{'
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`I
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`t
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`---
`1
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`I
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`.a
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`4. D-escription of Signals
`
`18-25
`
`IOCZ Bi-directional 3-state data bus for accesses to the internal registers.
`
`Type Description
`
`IC
`
`OC
`
`8 MHz reference clock. The timings of all interface signals to ARM and
`MEMC are referenced to this clock.
`
`8 MHz clock for external peripherals. This is REF8M buffered and
`inverted.
`
`OC
`
`2 MHz clock for external synchronous peripheral timing.
`
`IC
`
`OD
`
`IO cycle request. A LOW on this input indicates that the ARM is
`performing an IO cycle.
`
`IO cycle grant. An IO cycle is complete cycle when IOGT and
`IORQ are both LOW on a rising edge of REFSM.
`
`OD
`
`Buffer latch control for the ARM/IO data.
`
`OC
`
`Read Buffer Enable. This is taken LOW during a read of any IO
`Controller or peripheral.
`
`OC Write Buffer Enable. This is taken LOW during a write to any IO
`Controller or peripheral.
`
`OC
`
`IC
`
`IC
`
`IC
`
`Select external peripheral. This may be used to control an optional
`external data buffer which may be placed between IOC and the IO bus if
`the bus is heavily loaded . It is active for any IOC peripheral access.
`
`Type lines. These are used to specify the timing characteristics of any
`peripheral access.
`
`Not read/write. This line determines the direction of data transfer in an
`IO cycle: LOW to read or HIGH to write an IO device.
`
`Bank select lines. These arc used to select an IO access either to an
`internal IOC register (ll[0:2]=0) or to a peripheral (ll[0:2]>0). ll[0:2)are
`decoded to drive one of the peripheral select lines, S[1:7], LOW.
`
`Active low peripheral selects which indicate valid address and write data.
`They arc decoded from ll[0:2]
`
`Chip select. When HIGH allows internal register and peripheral accesses
`to be performed. Even when LOW, IOC continues to control the RBE
`and WBE lines.
`
`Name
`
`Pin
`
`REF8M
`
`8
`
`CLK8
`
`54
`
`CLK2
`
`IORQ
`
`llL
`
`D[0:7)
`
`RllE
`
`SEXT
`
`2
`
`7
`
`6
`
`5
`
`11
`
`12
`
`55
`
`T[O:l)
`
`1,68
`
`RJW
`
`10
`
`ll[0:2)
`
`64-66
`
`S[1:7]
`
`63-61,59-56 OC
`
`cs
`
`67
`
`IC
`
`A[2:6)
`
`13-17
`
`IC
`
`Address lines for selecting internal registers.
`
`RE
`
`WE
`
`IRQ
`
`FIQ
`
`4
`
`3
`
`51
`
`50
`
`IL[0:7]
`
`33-40
`
`OC
`
`Read enable, used to time peripheral read accesses.
`
`OC Write enable, used to time peripheral write accesses.
`
`OD
`
`OD
`
`IT
`
`Interrupt request to ARM.
`
`Fast Interrupt request to ARM.
`
`IRQ interrupt active low inputs.
`
`IOC Datasheet
`
`5
`
`SCEA Ex. 1053 Page 9
`
`

`
`Chapter 4
`
`IF
`
`IR
`
`41
`
`42
`
`FH[O:l]
`
`30-31
`
`FL
`
`C[0:5]
`
`llAUD
`
`KIN
`
`KOUT
`
`POR
`
`32
`
`44-49
`
`27
`
`52
`
`53
`
`28
`
`IT
`
`IT
`
`IT
`
`IT
`
`IRQ interrupt active falling-edge input.
`
`IRQ interrupt active rising-edge input.
`
`FIQ interrupt active high inputs.
`
`FIQ interrupt active low input.
`
`Baud rate generator output.
`
`Control pins. A bi-directional programmable open-drain port.
`
`IOD
`oc
`IT
`Keyboard Serial interface input.
`oc Keyboard Serial interface output.
`IS
`Power-on reset input, usually connected to an external RC network. It is
`used to generate a reset pulse at power-on and to differentiate power-on
`from subsequent causes of reset.
`
`RST
`
`29
`
`IOD The reset line is driven low by POR
`low externally at any time.
`
`at power-on and may be driven
`
`vss
`VDD
`
`9,43
`
`26,60
`
`PWR Ground supply
`
`PWR Positive supply
`
`Key to Signal Types
`Input CMOS compatible
`IC
`Input TIL compatible
`IT
`IS
`Input with Schmitt trigger
`OC
`Output CMOS compatible
`OD
`Output open-drain
`IOD
`Bi-direction open-drain
`IOCZ
`Bi-directional 3-stnte
`Power pins
`PWR
`
`6
`
`!OC Datasheet
`
`\.."· -~ ..... ' ·: .'
`
`@
`
`@
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`~-
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`~:
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`-
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`SCEA Ex. 1053 Page 10
`
`

`
`: .•
`
`5. Programming Model
`
`If the Bank ll[0:2], Type T[O:l], Chip Select CS and Addresses Lines A[2:6] of IOC are joined to the
`CPU address lines, ~he IOC and peripherals are viewed as memory mapped devices. This allows the
`programmer to specify in a single memory instruction the peripheral to be accessed and the type of timing
`cycle it requires. In a typical system as shown in figure 1 the 10 Controller space is devided into two
`halves. The upper half is occupied by IOC, and the lower half is left for additional IO Controllers.
`
`The IOC space is decoded into eight banks, bank zero through seven, by the ll[0:2] lines. The bottom
`bank, bank zero, maps to the internal registers of IOC. The remaining seven banks map to the seven
`peripheral select lines S[1:7] respectively. The seven peripheral banks are each further decoded into four
`types of peripheral access by the T[O:l] lines. (See figure 2.) The type of the peripheral access determines
`the timing of the data transfer cycle.
`
`(.
`
`:
`
`A particular peripheral device may be accessed by choosing an address where CS is HIGH, ll[0:2] decodes
`to the appropriate peripheral select, and T[l:O] selects a cycle with timing to suit the accessed device. The
`remaining low order address lines may be used to select the register within the device.
`
`ARM clock
`
`A[2:21]
`
`RW
`
`0(24:31]
`
`0[16:23]
`
`0[8:15]
`
`0[0:7]
`
`0[0:31]
`
`:?
`
`I
`
`•
`
`IOA[2:6] IOA[16:18] IOA(19:20] IOA[21]
`
`cs
`
`RE
`
`WE
`
`S[1:7J
`
`SEXT
`
`A[2:6] B[0:3] T[0:1]
`
`RW
`
`BL
`
`WBE
`
`RBi:
`
`IOC
`
`0[0:7]
`
`100[0:7]
`
`8
`
`Figure 1: Typical system
`
`IOC Datasheet
`
`7
`
`SCEA Ex. 1053 Page 11
`
`

`
`Chapter 5
`
`T[0:1)
`
`sync
`
`fast
`
`medium
`
`slow
`
`IOC
`
`Expansion
`
`Internal
`Bank 0
`..._ __ __. Registers
`
`Figure 2: Typical Decoding Structure
`
`5.1 Access Speed
`While the peripherals appear as memory mapped devices, it is not possible for accesses to them to be
`completed in the same time as accesses to main memory. Four different access cycle timings are available,
`and the timing for an access is determined from the state of T[O: 1] at the start of the access.
`
`5.2 Addresses
`The pipelined ARM addresses are latched by external buffers to provide valid signals thoughout both 10
`accesses and ROM reads. The latches are controlled by an ARM clock line which is stretched during slow
`cycles.
`
`5.3 Data
`The ARM data bus is connected to the 10 data bus by a set of latches. These provide two functions.
`Firstly they isolate the IO bus load from the main data bus, and secondly they allow for the mis-match in
`speed between the two buses. These buffers are controlled by the BL, RBE and WBE lines from IOC .
`
`8
`
`IOC Datasheet
`
`SCEA Ex. 1053 Page 12
`
`

`
`6. Internal Registers
`
`~~ .I ,
`
`
`
`All internal registers arc accessed with no wait states, and accesses take two REF8M cycles to complete.
`The internal registers arc decoded as bank zero, so to access them the B[0:2] lines must all be LOW and
`the IOC must be selected by taking CS HIGH. The individual registers are then addressed using the A[2:6]
`lines. The registers arc decoded on word boundaries. The state of the T[O: 1] lines is ignored.
`
`Read
`
`I
`I
`I
`I Write
`IAddr.l
`I
`I
`I
`I
`I
`I
`I Control
`I Control
`I OOH
`I 04H I Serial Rx Data I Serial Tx Data
`I -
`I 08H I -
`I -
`I -
`I OCH
`I -
`I lOH I IRQ status A
`I 14H I IRQ request A
`I IRQ clear
`I IRQ mask A
`A
`I 18H I IRQ mask
`I -
`I lCH I -
`I -
`I 20H I IRQ status B
`I 24H I IRQ request B
`I
`I 28H I IRQ mask
`I IRQ mask B
`B
`I -
`I -
`I 2CH
`I -
`I 30H I FIQ status
`I -
`I 34H I FIQ request
`I 38H I FIQ mask
`I FIQ mask
`I 3CH I -
`I -
`I 40H I TO count Low
`I TO latch Low
`I TO latch High
`I TO count High
`I 44H
`command
`I -
`I 48H
`I TO go
`I -
`I TO latch command
`I 4CH
`I Tl count Low
`I Tl latch Low
`I SOH
`I Tl count High
`I Tl latch High
`I 54H
`I 58H I -
`command
`I Tl go
`I -
`I Tl latch command
`I SCH
`I T2 count Low
`I T2 latch Low
`I 60H
`I T2 count High
`I T2 latch High
`I 64H
`I -
`command
`I 68H
`I T2 go
`I 6CH I -
`I T2 latch command
`I 70H I T3 count Low
`I T3 latch Low
`I 74H I T3 count High
`I T3 latch High
`command
`I -
`I 78H
`I T3 go
`I T3 latch command
`I -
`I 7CH
`I
`I
`I
`
`Table 1: Internal register memory map
`
`•
`
`,-~
`
`JOC Datasheet
`
`9
`
`SCEA Ex. 1053 Page 13
`
`

`
`Chapter 6
`6.1 Control Register
`The control register allows the external control pins C[O:S] to be read and written and the st..1tus of the IR
`and IF inputs to be inspected. The C[O:S] bits manipulate the C[O:S] IO Port. When read, they reflect the
`current state of these pins. When written LOW the output pin is driven LOW. These outputs arc open(cid:173)
`·drain, and if programmed HIGH the pin is undriven and may be treated as an input.
`
`On reset all bits in the control register arc set to "1 ".
`
`6.1.1 Control register OOH read
`7
`6
`5
`4
`3
`2
`
`IR
`
`TF I C[5] I C[4] I C[3] I C[2] I C[1] I C[O] I
`
`1
`
`0
`
`6.1.2 Control register OOH write
`5
`4
`3
`7
`6
`2
`
`I C[5] I C[4] I C[3] I C[2] I C[1] I C[OJ I
`
`0
`
`Set on pin C[O] HIGH
`Cleared on pin C[O] LOW
`
`Set on pin C[1] HIGH
`Cleared on pin C[1] LOW
`
`Set on pin C[2] HIGH
`Cleared on pin C[2] LOW
`
`Set on pin C[3] HIGH
`Cleared on pin C[3] LOW
`
`Set on pin C[4] HIGH
`Cleared on pin C[4] LOW
`
`Set on pin C[5] HIGH
`Cleared on pin C[5] LOW
`
`Set on pin iF HIGH
`Cleared on pin "W LOW
`
`Set on pin IR HIGH
`Cleared on pin IR LOW
`
`0 =pin C[O] driven LOW
`
`1 • pin C[O] undriven
`
`0 =pin C[1] driven LOW
`
`1 • pin C[1] undriven
`
`0 = pin C[2] driven LOW
`
`1 = pin C[2] undriven
`
`0 = pin C[3] driven LOW
`
`1 = pin C[3] undriven
`
`0 = pin C[4] driven LOW
`
`1 =pin C[4] undriven
`
`0 = pin C[5] driven LOW
`
`1 = pin C[5] undriven
`
`10
`
`IOC Datasheet
`
`~
`
`~
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`@'
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`@.
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`~-
`
`~
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`@i
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`~
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`@I
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`~
`
`~-
`
`@1.
`
`~;
`
`~' t!'- [
`~!
`I
`~ I
`I
`f!-· I I
`,- '' -.. , .. ,..:
`
`' .... ~- ----
`
`SCEA Ex. 1053 Page 14
`
`

`
`·•
`
`·•
`
`Internal Registers
`
`6.2 Keyboard Asynchronous Receiver Transmitter (KART)
`The KART provides an asynchronous serial link, usually to a keyboard. It is of fixed format with 8 bits to
`a character which is framed with one start bit and two stop bits. The least significant bit KD[OJ is
`transmitted/received first. The KART divides into two halves, the receiver and the transmitter.
`
`The ARM accesses the receiver via the Serial Rx Data register. A clock of 16 times the data rate is used
`by the KART to clock in the serial data from the KIN pin. When a data byte has been received, the SRx
`bit is asserted in the IRQ Status B Register to indicate that the byte is available for reading. False start biL'>
`of less than a half bit duration arc ignored.
`
`The ARM accesses the transmitter via the Serial Tx Data register. The byte written to tJ1e Serial Tx Data
`register is transmiLted serially from t11c KOUT pin, and the STx bit is asserted in the IRQ Status B register
`to indicate that the transmission is finished and the Serial Tx Data register may be reloaded.
`
`The receive and transmit speeds are t11e same and are programmed using counter 3.
`
`6.2.1 Serial Tx Data register 04H write
`
`7
`
`6
`
`5
`
`4
`
`3
`
`2
`
`0
`
`Writing to this register loads the serial output shift register, clears any outstanding TRx interrupt and starts
`the transmission. An interrupt is raised when the register is ready to be reloaded.
`
`KART Data
`
`KD[7:0]
`
`6.2.2 Serial Rx Data 04H read
`
`7
`
`6
`
`5
`
`4
`
`3
`
`2
`
`1
`
`0
`
`KART Data
`
`KD[7:0]
`
`Reading from this register clears any outstanding SRx interrupt and returns the currently received byte. Data
`is only valid while the SRx bit is set in the IRQ status B register.
`
`6.2.3 Initialisation
`
`,.
`J
`
`I
`,
`
`After Power-On, the KART is in an undefined state. The KART is initialised by programming the serial
`line speed using counter 3 and performing a read from the Serial Rx Data register, discarding the data
`byte. This will clear any outstanding receive interrupt and enable the KART for the next reception. Finally
`the Tx Data register should be written to. This will abort any transmission in progress, cause a new one to
`be started, and clear any STx interrupt.
`
`6.2.4 Receive Interrupt
`
`The SRx interrupt is set halfway though the reception of the last data bit. Care should be taken to ensure
`that the last bit has been received before the Serial Rx data register is read, to prevent this bit being
`interpreted as the start bit of the next packet.
`
`i )
`
`IOC Datasheet
`
`11
`
`SCEA Ex. 1053 Page 15
`
`

`
`Chapter 6
`6.3 Interrupt Registers
`The IOC generates two independant interrupt requests, IRQ and FIQ. Interrupt requests can be caused by
`events internal to IOC or by external events on the interrupt or control port input pins.
`
`The IOC interrupts are controlled by four types of register, status, mask, request and clear. The status
`registers reflect the current state of the various interrupt sources. The mask registers determine which
`sources may generate an interrupt. The request registers are the logical AND of the status and mask
`registers and indicate which sources are genera,ting interrupt requests to the processor. The clear register
`allows clearing of interrupt requests where appropriate. The mask registers arc undefined after power up.
`
`~-
`
`The IRQ events arc split into two sets of registers A and B . There is no priority encoding of the sources.
`
`6.3.1 Internal Interrupt Events
`Timer interrupts TM[O:l].
`*
`*
`*
`*
`*
`
`Power-on reset POR.
`
`Keyboard Rx data available SRx.
`
`Keyboard Tx data register empty STx.
`
`Force interrupts "J".
`
`IRQ falling-edge input IF.
`
`IRQ rising-edge input JR.
`
`6.3.2 External Interrupt Events
`*
`IRQ active low inputs IL[0:7].
`*
`*
`*
`*
`*
`
`FIQ active high inputs Fll[O:J ].
`
`FIQ active low input FL.
`
`Control port inputs C[3:5].
`
`6.3.3 Level Interrupts
`
`The majority of external and a few of the internal interrupt sources are level sensitive. When one of these
`sources has caused an interrupt it is cleared by removing the source.
`
`.6.3.4 Latched Interrupts
`
`The IF, IR, POR and TM[O:l] sources are latched. That is, once one of these sources has caused an
`interrupt, it must be cleared by an explicit write of "I" to the appropriate bit in the IRQ Clear A register.
`One or many may be cleared in a single operation.
`
`6.3.5 Synchronisation
`All the interrupt sources are synchronised by the REFSM clock input. It can take up to three clock phases
`before a source is recognised as requesting an interrupt, and the same delay occurs between a level
`sensitive request going inactive at an input pin and the removal of the corresponding bit from the status
`·register and the processor interrupt line.
`
`12
`
`IOC DaJasheet
`
`~-
`
`@
`
`i
`
`~i @!
`@.!
`~~
`I @_I
`~' - I
`~· - I
`~i
`
`SCEA Ex. 1053 Page 16
`
`

`
`.....
`\'
`
`;r~
`
`t'l
`
`6.3.6 IRQ Status A register lOH read
`2
`7
`6
`5
`4
`3
`
`T I TM[1]1 TM[O]I POR IIR
`
`IF
`
`0
`
`IL[7] IIL[6] I
`
`Internal Registers
`
`Set on pin ll[G] LOW
`Cleared on pin IL[6] HIGH
`
`Set on pin IL[7] LOW
`Cleared on pin IC{7THIGH
`
`Set on HIGH-to-LOW edge on pin TF
`Cleared by IRQ Clear Register
`
`Set on LOW-toHIGH edge on pin IR
`Cleared by IRQ Clear Register
`
`Set at power-on
`Cleared by IRQ Clear Register
`
`Set on timer 0 reload
`Cleared by IRQ Clear Register
`
`•
`Set on Timer 1 reload.
`Cleared by IRQ Clear Register
`
`Set always
`Cleared never
`
`Set on pin IL[O] LOW
`Cleared on pin IL[O] HIGH
`
`Set on pin ll[1] LOW
`Cleared on pin TC[i] HIGH
`
`Set on pin IL[2] LOW
`Cleared on pin IL[2] HIGH
`
`Set on pin IL[3] LOW
`Cleared on pin IL[3] HIGH
`
`Set on pin [[[41 LOW
`Cleared on pin IL[4] HIGH
`
`Set on pin IL[5] LOW
`Cleared on pin IL[5] HIGH
`
`Set on KART Tx Data register empty
`Cleared by write to KART Tx data register
`
`Set on KART Rx Data register full
`Cleared by read from KART Rx Data register
`
`6.3.7 IRQ Status B register 20H read
`5
`6
`3
`7
`4
`2
`
`0
`
`IOC Datasheet
`
`13
`
`SCEA Ex. 1053 Page 17
`
`

`
`Chapter 6
`
`6.3.8 FIQ Status register 30H read
`5
`4
`6
`3
`2
`7
`
`0
`
`6.3.9 IRQ Clear register 14H write
`6 54 3 210
`7
`
`Set on pin FH[O] HIGH
`Cleared on pin FH[O] LOW
`
`Set on pin FH[1] HIGH
`Cleared on pin FH[1] LOW
`
`Set on pin FL LOW
`Cleared on pin FL HIGH
`
`Set on pin C[3] LOW
`Cleared on pin C[3] HIGH
`
`Set on pin C[4] LOW
`Cleared on pin C[4] HIGH
`
`Set on pin C[5] LOW
`Cleared on pin C[5] HIGH
`
`Set on pin [[OJ LOW
`Cleared on pin JL[O] HIGH
`
`Set always
`Cleared never
`
`0 • no action
`1 • clear
`
`0- no aclion
`1 =clear
`
`0 • no action
`1. clear
`
`0 • no action
`1 • clear
`
`0 ::s no action
`1 -clear
`
`14
`
`IOC Datasheet
`
`~
`
`~
`
`~
`
`@
`
`~
`
`~
`
`~
`
`~
`
`~
`
`@
`
`@·
`
`~
`
`@:
`
`@:
`i @.r
`[
`@I
`I
`~-, l
`t!:l
`~!
`~~
`I
`~--• I
`- I
`~ J
`I
`~,
`
`~-I
`
`. . . ~·
`
`-:
`
`'_~ .. i ..... ;;t ',, ·:. :~~ l~'~
`
`SCEA Ex. 1053 Page 18
`
`

`
`6.3.10 Interrupt Request registers 14H 24H 34H read
`
`These registers show which interrupt sources are currently enabled and active. They give the logical AND
`of the corresponding status and mask registers.
`
`Internal Registers
`
`(i)
`
`IRQ request A address 14H
`
`(ii)
`
`IRQ request B address 24H
`
`(iii) FIQ request
`
`address 34H
`
`7
`
`6
`
`5
`
`4
`
`3
`
`2
`
`0
`
`0 = mask disabled or source not requesting an interrupt
`
`1 = mask enabled and source requesting an interrupt
`
`6.3.11 Interrupt Mask registers 18H 28H 38H read/write
`The mask registers are readable to simplify the sharing of these registers between a number of interrupt
`handlers.
`
`7
`
`6
`
`5
`
`4
`
`3
`
`2
`
`0
`
`0 • source disabled
`
`1 • source enabled
`
`(i)
`
`IRQ mask A address 18H
`
`(ii)
`
`IRQ mask B address 28H
`
`(iii) FIQ mask
`
`address 38H
`
`IOC Datasheet
`
`15
`
`i!
`
`;~
`I
`:~
`
`l )
`
`il
`
`~
`
`r?)
`
`j )
`
`"'S'l~~1~~~1~~i~~~w:r~R~~~~~~~~~1~1~.~~~~~~'t~;~if:'o':~~-::~y~:'n"\;'J.~~~~:~~~-.
`
`•
`
`•
`
`•
`
`<1.
`
`•
`
`SCEA Ex. 1053 Page 19
`
`

`
`Chapter 6
`
`6.4 Counters
`Four identical 16 bit counters arc provided. Two arc used as timers, the third for the keyboard BAUD rate
`and the fourth as a general purpose output. They all have fully programmable start/reload values.
`
`Each counter consists of a 16 bit down counter, a 16 bit input latch (latch low and latch high) and a 16 bit
`output latch (count low and count high) which contains the value of the counter when the latch command is
`given. The counter decrements continuously, clocked at 2 MHz. When it decrements to zero, it is reloaded
`from
`the input latch and recommences decrementing. The reload is used to trigger different events
`depending on the use of the counter. If a counter is loaded with zero it continuously reloads and does not
`count. If the GO register is written at the same time as the counter reloads an extra 2 MHz clock tick is
`taken to reload. After power-on the state of the counters is unknown.
`
`latch = latch low + 256 * latch high
`
`6.4.1 Register actions
`Writing to this updates the low order byte of the input latch
`Latch low
`Writing to this updates the high order byte of the input latch
`Latch high
`Writing to this causes the counter to be reloaded immediately with the latch value.
`GO command
`This causes the low order byte of the output latch to be read.
`Count low
`This causes the high order byte of the output latch to be read.
`Count high
`This causes the current value of the counter to be placed in the output latch.
`Latch command
`
`6.4.2 Counter schematic
`
`~·
`
`Control
`Logic
`
`2MHz
`
`GO
`
`1 6 bit counter
`
`ut~ r---------,_------~------------~------~
`
`0[0:7]
`
`Figure 3: Counter schematic
`
`16
`
`IOC Datasheet
`
`•'·
`
`. \
`
`·,
`
`SCEA Ex. 1053 Page 20
`
`

`
`' l
`
`;;~
`
`l·
`
`!~
`
`~
`
`.. ;,_
`~
`"J
`
`Internal Registers
`
`6.4.3 Counter Registers
`
`Address
`for counter
`1
`2
`
`0
`
`read or
`write
`
`3
`
`Latch low
`Latch high
`GO command
`Count low
`Count high
`Latch command
`
`70H write
`60H
`SOH
`40H
`74H write
`54H
`44H
`64H
`48H
`68H
`58H
`78H write
`40H
`SOH
`70H
`read
`60H
`44H
`54H
`74H
`read
`64H
`4CH 5CH 6CH 7CH write.
`
`6.4.4 Counters 0 and 1
`Two general purpose timers are provided. The reload event sets a timer interrupt, TM[O:l] in the IRQ
`status A register. The interrupt is cleared via the IRQ Clear A register. In order to generate an interrupt
`after time, Tinterval• the 16 bit value, (latch), to be used is calculated from the following equation.
`
`Tinterval := latch/2
`
`1-l-Seconds
`
`6.4.5 Counter 2 (BAUD)
`
`The counter 2 output is used to drive the BAUD pin. The reload event toggles the BAUD clock line. In
`order to generate a clock of frequency fBAUD• the 16 bit value, (latch), to be used is calculated from the
`following equation.
`
`fBAUD := 1/(latch+1) MHz
`
`The maximum BAUD rate of 500kHz is obtained by programming latch=l.
`
`6.4.6 Counter 3 (KART)
`
`--~
`
`This counter 3 output controls the speed of the keyboard serial link. In order to generate a baud rate
`kBAUD• the 16 bit value, (latch), to be used is calculated from the following equation.
`
`kBAUD := l/((/atch+1)*16) MHz
`
`The maximum baud rate of 31250Hz is obtained by programming latch=l.
`
`-~
`
`----:11
`
`I~
`'~
`
`IOC Datasheet
`
`17
`
`SCEA Ex. 1053 Page 21
`
`

`
`7. Peripherals
`
`The IOC provides control for external peripherals which cannot be accessed in a single cycle. A number of
`differently timed cycles, selected by the T[O:l] lines, arc provided. The peripheral cycles arc controlled by
`a state machine clocked from REF8M . The cycles arc timed to two clocks CLK2 and CLK8. Two timed
`data strobes, write enable WE and read enable RE, manipulate data.
`
`(Internal accesses complete in two REF8M cycles, and the state machine remains IDLE during these.)
`
`The number of REF8M cycles an IO access takes to complete depends on three things:
`
`(I) The minimum time for the cycle;
`
`(2) The synchronisation time
`
`(3) DMA activity on the ARM bus.
`
`The times arc expressed as in REF8M cycles. The first three cycles share common timing and arc of fixed
`duration. The last is synchronised to the CLK2 output, a 2 MHz square wave. Examples of the peripheral
`access are given in Appendix A.
`
`T [1: OJ
`
`Name
`
`0:0
`0:1
`1:0
`1: 1
`
`slow
`medium
`fast
`sync
`
`I
`Minimum I Synchronisation
`time
`time
`I
`(REFSM
`I
`(REFSM
`cycles}
`cycles}
`I
`I
`I
`I
`. I
`I
`I
`I
`
`0
`0
`0
`0, 1' 2' 3
`
`7
`6
`5
`5
`
`Table 2: Cycle timing
`
`18
`
`JOC Dmasheet
`
`. ~ . ' ......
`
`.. ' .
`
`-~
`
`. \ . ·.
`
`SCEA Ex. 1053 Page 22
`
`

`
`·-}
`
`8. ARM/10 Interface
`
`8.1 Peripheral Address and Data
`The peripheral address and data arc not provided by IOC, so their timing is system dependent. The
`following explanations assume that the configuration is as in figure 1. Additionally, process dependent
`delays though IOC can be up to half a REF8M clock pulse, so there can be considerable skew between
`signals coming from IOC and those from other sources.
`
`8.1.1 Peripheral Write Cycles
`
`Since the MEMC may perform DMA transfers on the main data bus while an IO cycle is in progress, the
`write data must be latched to provide valid data throughout the IO cycle. This is done by taking BL LOW
`at the start of the cycle. It is taken I-ITGH again at the end of the cycle.
`
`8.1.2 Peripheral Read Cycles
`
`To provide fixed duration cycles for the peripherals, the read data is latched by taking BL LOW as the
`RE strobe is taken HIGH. This allows the peripheral cycle to complete independently of the processor, and
`the data is held in the data latches until the processor is ready to complete the IO cycle.
`
`8.2 Peripheral Select Lines
`The peripheral select lines S[ l :7] are timed at the start of a cycle from IORQ and disabled at the end of
`the cycle by the state machine.
`
`8.3 Multiple IO Controllers
`The IOC has been designed to allow multiple IORQ/ IOGT devices to be connected to MEMC. For this
`reason the IOGT and llL lines arc open drain outputs. Even when IOC is not selected it continues to
`control the external buffer enables RllE and WllE, so additional IO Controllers need not generate these
`signals.
`
`8.4 10 Grant Line
`In order for an internal register access to complete in two REF8M clock cycles the IOGT line cannot be
`made to depend logically on IORQ, which indicates the start of an IO cycle, as IORQ becomes valid too
`late. Therefore IOGT is generated from ll[0:2] and CS only, and will sometimes be driven LOW during
`non-IO cycles.
`
`For peripheral access the IOGT line is controlled by the state machine.
`
`JOC Datasheet
`
`19
`
`·.~
`
`.,
`\
`'::::l
`
`II
`
`I -
`
`J
`
`'
`
`ll
`
`-•
`
`SCEA Ex. 1053 Page 23
`
`

`
`9. Reset and Power-on
`
`The IOC may be reset in two ways: by driving the bidirectional RST line LOW, or by driving the
`POR line LOW. The POR pin is designed to be connected to an external RC network to ensure that
`when power is first applied to the IOC, a system reset signal is generated on RST. POR causes an
`internal latched interrupt to be set to allow system software to differentiate between "power-on" and "soft"
`resets, and ensures that peripheral chips have had a stable clock for a suitable length of time before being
`released from reset.
`
`The control register is initialised on reset causing the C[O:S] pins to be set to a known state, HIGH, before
`the processor commences execution.
`
`~.·
`
`100R
`
`IN4148
`
`I
`
`VDD
`
`vss
`
`Figure 4: Suggested circuit for power-on reset
`
`sv
`
`Schmitt
`Thr~d•r-------------~--------~~~-4------------~
`
`ov
`
`RST
`
`REFBM - - - - - - -
`
`Figure 5: Power-on timing
`
`20
`
`IOC DaJasheet
`
`.. ".
`
`SCEA Ex. 1053 Page 24
`
`

`
`10~ 10-Cycle State Machine
`
`Loop if IDLE
`+----------+
`I
`RESET (note 2)
`---------+
`\II
`I
`+-----------+
`+--->1
`+----+ Type 3 Cycle (note 1)
`+-------------->1
`+-----------------------------+
`IDLE
`I
`+--+-----+--+
`I
`I
`I
`I Type 3 Cycle (note 1)
`I
`I +----------------+
`+-----------------+
`I
`\I I
`I I
`I IType 0 Cycle +-----------+
`+-----------+
`I +------------>1
`1<-+
`REIWE=O I
`I
`WAIT
`+-----+-----+
`+--+-----+--+
`I I
`I
`I I
`I
`I
`I
`I
`+-----+
`I I
`\II
`I
`I IType 1 Cycle +-----+-----+
`I
`I +------------>1
`REIWE=O 1<-------------+-----------+
`+-----+-----+
`I
`I
`I I
`I
`\I I
`I
`I
`I IType 2 Cycle +-+-------+-+
`I +------------>1
`REIWE=O I
`+-+-------+-+
`I
`I
`I
`I Type 0, 1 or 2 Cycles
`I
`I
`\II
`I +-----+-----+
`I
`I
`I
`REIWE-0 I
`I +-----+-----+
`I
`I
`I
`I Type 0, 1 or 2 Cycles
`I
`\II
`\II
`+-+-------+-+
`I
`I
`IOGT-0
`+-----+-----+
`I
`I
`I
`I
`\II
`+-----------+
`I
`IOGT-0 1<---------+
`I
`I
`+---+----+--+
`I
`I Loop until ARM
`I
`I
`I
`I
`is ready
`+-------------------+
`+-------------+
`
`Type 3
`
`Loop till
`synchronised
`
`NOTES:
`
`(1) Type 3 cycles will go into the wait state unless the cycle starts at the optimal point in the CLK2
`cycle.
`
`(2) RESET is a forcing signal to return to IDLE from any state .
`
`IOC Datasheet
`
`21
`
`i )
`
`I )
`
`:~
`
`:~
`
`--
`"B:)
`
`•
`
`SCEA Ex. 1053 Page 25
`
`

`
`11. DC Para1neters
`
`11.1 Absolute Maximum Ratings
`
`Symbol
`
`Parameter
`
`Min
`
`Max
`
`Units Note
`
`VDD
`
`Vip
`
`Ts
`
`Supply· voltage
`
`VSS-0.3
`
`VSS+7.0