`IPR of U.S. Pat. No. 6,128,290
`
`
`
`BodyLANTM: A Low-Power Communications System
`
`by
`
`Thomas J. Barber Jr.
`
`Submitted to the
`
`Department of Electrical Engineering and Computer Science
`
`30 January 1996
`
`In Partial Fulfillment of the Requirements for the Degree of
`Master of Science in Electrical Engineering and Computer Science
`
`Abstract
`
`In the last few years the wireless communications market has exploded with products such
`
`as pagers and cellular phones becoming common items. The trend in this field has been to move
`
`toward communications over a smaller area using less power. This thesis presents the Body-
`
`LANT“ system which is a communications network designed to gather data from within the
`
`sphere of the body and provide that information to the user through wireless links. To make the
`
`system marketable the battery life of the component must be maximized. This presents a chal-
`
`lenge to provide wireless communications at microwatt power levels. This goal is accomplished
`
`through the use of a custom integrated circuit controller which dissipates under 50 ttW.
`
`Thesis Supervisor: Anantha Chandrakasan
`Title: Analog Devices, Inc. Career Development Professor
`
`
`
`Acknowledgments
`
`I would like to thank my thesis advisor Professor Anantha Chandrakasan who provided
`
`me with all the support, encouragement and motivation I needed to complete this project. I would
`
`also like to thank Phil Carvey of Bolt Barenek and Newman for defining the project and letting
`
`me run with it. Also, for his invaluable advice and feedback. Thanks to Professor Mitch Trott who
`
`took time out of his schedule to review some of the communications theory in theproject.
`
`The members of our research group especially Raj Amirtharaj ah who took the time to read
`
`this entire thesis. Also, Vadim Gutnik, for being my general Unix guru. Mike Perrott and Don
`
`Hitko for helping me with the analog side of the house. As well as Duke Xanthopoulos, Jim
`
`Goodman and Tom Simon for sharing their experience with in circuit design.
`
`Finally, I would like to thank those who helped in non-technical ways. My roommates
`
`Matt Greenman, Randy Berry and Chris May for helping keep me sane (and walking the dog). Jill
`
`Wilkens for getting me out into the real world occasionally (and feeding me). Mark Gustafson and
`
`Nate Them for letting me know what it was like on the outside. Master Jon I-Ienkel without whom
`
`I would haven't have had the courage to attend MIT. Finally, Thomas and Mary Ann Barber with-
`
`out whom I would be here at all.
`
`From the very bottom of my heart. thank you all. Goodnight...
`
`
`
`For Mom and Dad,
`
`
`
`Table of Contents
`
`.
`.
`.
`. .
`.
`Chapter 1: Overview of BodyLAN'““ System .
`.
`.
`.
`1.1 BodyLAN'"-4 Network Configuration .
`.
`.
`1.2 BodyLANT” Communications Protocol . .
`.
`1.3 BodyLANTM Architecture .
`.
`.
`.
`. .
`.
`.
`.
`.
`.
`. .
`1.4 Bod}/LANTM System Power Consumption .
`
`.
`.
`.
`.
`.
`.
`. .
`.
`.
`
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Chapter 2: Review of Low-Power Design Principles .
`. .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`2.1 Power Consumption Basics .
`.
`.
`.
`.
`.
`.
`.
`.
`. .
`. .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`2.2 Low Power Design Overview .
`. .
`.
`.
`.
`. .
`.
`.
`. .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`2.2.1 Voltage Scaling .
`.
`.
`.
`. .
`.
`.
`.
`.
`.
`.
`.
`2.2.2 Minimizing Effective Switched Capacitance per Cycle .
`2.2.3 Gated Clocks .
`.
`.
`.
`.
`.
`. .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`. .
`
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`.
`
`. 7
`.
`. 7
`.
`. 9
`.
`. 10
`. 12
`
`. 14
`. 14
`. 15
`. 16
`. 17
`. 20
`
`Chapter 3: BodyLAN"”"‘ Controller Integrated Circuit Operation .
`3.0 Introduction .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`3.1 System Architecture .
`3.2 BodyLANTM Controller Chip Operation .
`3.2.1 Attachment Mode.
`.
`.
`.
`.
`.
`.
`.
`. .
`.
`.
`
`.
`.
`.
`
`.
`.
`.
`
`. .
`.
`.
`.
`.
`
`.
`.
`.
`
`.
`.
`.
`
`3.2.2 Synchronization Mode .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`3.2.3 Time Division Multiple Access Mode . .
`
`.
`.
`.
`
`.
`.
`
`.
`.
`.
`
`.
`.
`
`.
`.
`.
`
`.
`.
`
`.
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`.
`
`.
`.
`
`. 22
`. 22
`
`. 22
`. 22
`. 23
`
`. 24
`. 27
`
`.
`.
`
`. 29
`. 29
`
`Chapter 4: Low—Power Microcontroller Design .
`4.0 Introduction .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`
`4.1 Microcontroller Core .
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`.
`
`. .
`
`.
`.
`
`.
`
`.
`.
`
`.
`.
`
`. .
`
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`4.2 Digital Sequencers .
`.
`.
`.
`.
`.
`.
`.
`4.2.1 Delay-Line Digital Sequencer .
`.
`.
`.
`.
`.
`4.2.2 Asynchronous Digital Sequencer.
`.
`.
`.
`.
`.
`4.2.3 Synchronous Digital Sequencer .
`.
`.
`4.2.4 Pseudo-Grey Code Digital Sequencer .
`.
`4.3 Bodyl_,ANTM Microcontroller .
`.
`.
`.
`.
`.
`.
`. .
`.
`.
`.
`.
`.
`.
`4.3.1 Instruction Set .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`. .
`.
`.
`.
`. .
`
`.
`.
`
`.
`
`.
`.
`.
`.
`.
`.
`.
`
`.
`.
`
`.
`
`.
`.
`.
`.
`.
`.
`.
`
`.
`.
`
`.
`
`.
`.
`.
`.
`.
`.
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`
`. .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`
`.
`.
`
`.
`
`.
`.
`.
`.
`.
`.
`.
`
`.
`
`.
`.
`.
`.
`.
`.
`.
`
`.
`.
`
`.
`
`.
`.
`.
`.
`.
`.
`.
`
`.
`.
`
`.
`
`.
`.
`.
`.
`.
`.
`.
`
`.
`.
`
`.
`
`.
`.
`.
`.
`.
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`.
`.
`.
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`.
`.
`.
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`.
`.
`.
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`.
`.
`.
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`.
`.
`.
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`.
`.
`.
`.
`.
`
`.
`
`.
`
`. 29
`
`.
`.
`.
`.
`.
`.
`.
`
`. 30
`. 32
`. 32
`. 32
`. 33
`. 35
`. 35
`
`.
`
`. 37
`
`4.3.2 Microcontroller Core .
`
`.
`
`.
`
`.
`
`.
`
`4.3.3 Burst Execution Hardware .
`
`.
`
`.
`
`.
`
`.
`
`. .
`
`. .
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`.
`
`4.3.4‘Synchronization Beacon Processing Hardware .
`4.3.5 Duration Comparator Hardware .
`.
`.
`.
`_
`.
`.
`.
`.
`.
`.
`.
`
`.
`
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`
`.
`
`.
`.
`
`.
`.
`
`.
`
`.
`
`.
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`.
`
`. 39
`
`. 39
`. 40
`
`. 42
`. 42
`
`Chapter 5: Low Power Matched Filter Design .
`5.0 Introduction .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`
`5.1 Low Power Matched Filters .
`
`.
`
`.
`
`. .
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`.
`.
`.
`.
`.
`.
`5.1.1 Algorithm Design.
`5.1.2 Matched Filter Architecture .
`
`.
`
`.
`
`. .
`. .
`
`.
`5.1.3 Matched Filter Logic Design .
`.
`5.2 BodyI..AN'”"' Attachment System .
`.
`.
`.
`.
`5.2.1 Attachment Beacons .
`.
`.
`.
`.
`.
`. .
`
`.
`
`.
`.
`
`.
`.
`.
`
`.
`
`.
`.
`
`.
`.
`.
`
`.
`
`.
`.
`
`.
`.
`.
`
`.
`
`.
`.
`
`.
`.
`.
`
`.
`
`.
`.
`
`.
`.
`.
`
`.
`
`.
`.
`
`.
`.
`.
`
`.
`
`.
`.
`
`.
`.
`.
`
`.
`
`.
`.
`
`.
`.
`.
`
`.
`
`.
`.
`
`.
`.
`.
`
`.
`
`.
`.
`
`.
`.
`.
`
`.
`
`.
`.
`
`.
`.
`.
`
`.
`
`.
`.
`
`.
`.
`.
`
`.
`
`.
`.
`
`.
`.
`.
`
`.
`
`.
`.
`
`.
`.
`.
`
`.
`
`.
`.
`
`.
`.
`.
`
`.
`
`.
`.
`
`.
`.
`.
`
`.
`
`.
`.
`
`.
`.
`.
`
`.
`
`.
`.
`
`.
`.
`.
`
`.
`
`.
`.
`
`.
`.
`.
`
`.
`
`.
`
`. .
`.
`.
`
`.
`.
`.
`
`.
`.
`.
`
`.
`
`.
`.
`
`.
`.
`.
`
`.
`
`.
`.
`
`.
`.
`.
`
`.
`
`.
`.
`
`.
`.
`.
`
`. 42
`
`. 42
`. 45
`
`. 46
`. 49
`. 50
`
`Page 5
`
`
`
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`5.2.2 BodyLANTM Matched Filter .
`5.2.3 BodyLAN““ Beacon Detection Processing .
`
`Chapter 6: BodyLANT“ Controller Chip .
`6.0 Introduction .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`. .
`
`6.1 BodyLANT'*" Controller Hardware . .
`6.1.1 RF Interface .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`. .
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`. .
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`. .
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`. 50
`. 51
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`. 53
`. 53
`
`. 53
`. 53
`
`. 55
`. 58
`
`6.1.2 Microprocessor Interface .
`6.1.3 Sensor Interface .
`.
`.
`.
`.
`.
`.
`.
`
`6.1.4 Clock Division Chain .
`
`.
`
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`6.1.5 Microprocessor Wake-—up Circuitry .
`6.2 BodyLANTM Controller Power Measurements .
`
`.
`.
`
`.
`
`.
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`. 59
`
`. 60
`. 62
`
`Appendix 1: A Comparison of Switched Capacitance Estimation Methods .
`
`.
`
`.
`
`.
`
`.
`
`.
`
`. 67
`
`List of Tables
`
`Table 1: Range and Bandwidth Comparision for Various Wireless Networks .
`Table 2: Decimal, Grey Code and Pseudo-Grey Code .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Table 3: Microcontroller Instruction Set .
`.
`.
`.
`.
`.
`. .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`
`.
`.
`.
`
`.
`.
`.
`
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Table 4: Number of Combinations Needed for a 32-bit System .
`.
`.
`Table 5: Code Bits and the Interval Location Where They are Transmitted .
`.
`.
`Table 6: Effective Switched Capacitance per Cycle for the Matched Filter .
`.
`Table 7: Effective Capacitance Switched for the Beacon Detection Hardware .
`Table 8: Register Allocation for BodyLANT“ System .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`. .
`.
`Table 9: Microprocessor Sleep Times .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`. .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Table 10: Power Dissipation for the System Blocks .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Table 11: Energy Dissipation for Microprocessor Interface .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Table 12: RF Interface Energy Dissipation .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Table 13: SRAM Energy Dissipation .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Table 14: Power Dissipation of BodyLANT” Controller Chip Components .
`.
`.
`Table 16: Area Capacitances for a 1.211 CMOS process .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`
`.
`.
`.
`
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`
`.
`.
`.
`
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`
`. 6
`.
`. 33
`. 37
`
`. 43
`. 50
`. 51
`. 52
`. 56
`. 61
`. 63
`. 63
`. 64
`. 65
`. 65
`. 69
`
`Page 6
`
`
`
`List of Figures
`
`. .
`.
`.
`.
`.
`.
`. .
`.
`.
`.
`.
`.
`. .
`.
`.
`. . .
`.
`.
`.
`. .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Figure la: Star Configuration .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`. .
`.
`.
`.
`. .
`. .
`.
`.
`.
`. .
`. .
`Figure lb: Ring Configuration .
`.
`.
`.
`.
`_
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Figure 1c: Complete Configuration .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Figure 2: BodyLAN“‘ Architecture .
`.
`.
`.
`.
`.
`. .
`. .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`. .
`.
`.
`.
`.
`.
`.
`.
`Figure 3: PCMICIA Interface Architecture .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Figure 4: PEA Architecture .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Figure 5: Custom Controller Integrated Circuit Architecture .
`.
`.
`.
`.
`.
`.
`.
`.
`Figure 6: Propagation Delay vs. Supply Voltage for a Single Inverter .
`.
`.
`.
`.
`.
`.
`.
`.
`Figure 7a: Non-Pipelined System with td = tdl + td2 + td3 + td4 .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Figure 7b: Pipelined System with td = max (tdl, td2, td3, m4) .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Figure 8a: Chain Architecture for an Addition .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`. .
`.
`.
`.
`.
`.
`Figure 8b: Tree Architecture for an Addition .
`.
`.
`.
`.
`. .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Figure 9a: Shift Register without Parallization .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Figure 9b: Parallel Shift Register with n = 2 .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Figure 10: Power Consumption vs. Degree of Parallism for a Shift Register .
`.
`.
`Figure 11: BodyLANTM Controller Custom Integrated Circuit Architecture .
`.
`.
`.
`Figure 12: Control Flow of the Controller Chip .
`.
`.
`. .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`. .
`.
`.
`.
`.
`.
`.
`.
`.
`Figure 13: Sample Attachment Beacon Placement within TDMA Frame and
`Section of an Attachment Beacon .
`.
`.
`.
`.
`. .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`. .
`.
`.
`.
`.
`.
`
`.
`
`.
`
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`..
`.
`.
`.
`
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`
`.
`
`.
`
`. .
`
`.
`
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`
`.
`
`.
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`
`.
`
`.
`.
`.
`.
`.
`.
`
`. .8
`.
`. .8
`.
`. .8
`.
`. .11
`. .11
`. .12
`. .12
`. .17
`. .17
`. .17
`. .18
`. .18
`. .19
`. .19
`. .20
`. .22
`. .23
`
`. .24
`
`. .25
`. .26
`. .26
`. .27
`. .28
`. -30
`
`.
`
`.
`
`. .31
`
`.
`.
`.
`.
`.
`.
`
`.
`
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Figure 14: Digital Phase—Locked Loop Architecture .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Figure 15a: Synchronization Beacon Sampled Early .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Figure 16: Analog Phase Detector .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Figure 17: Analog Phase Detector Control Signals for Different Cases .
`.
`. .
`.
`.
`Figure 18: BodyLANTM Microcontroller Architecture .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Figure 19: Architecture for all Digital Sequencers Investigated .
`.
`.
`.
`.
`.
`.
`Figure 20: Digital Sequencer Architecture to Minimize Capacitance Switched
`While Inactive .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`. .
`.
`.
`.
`.
`.
`.
`. .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`.
`
`.
`
`.
`
`.
`.
`.
`.
`.
`.
`
`.
`
`.
`
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Figure 21: Delay-Line Counter .
`.
`.
`.
`.
`. .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Figure 22: Asynchronous Counter Cell
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Figure 23: Synchronous Counter Cell.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Figure 24: Pseudo-Grey Code Counter Cell .
`Figure 25: Power Consumption of Counter Normalized to Pseudo-Grey Counter .
`Figure 26: Digital Sequencer Power Dissipation vs. Degree of Loading .
`.
`.
`.
`.
`.
`.
`.
`.
`Figure 27: Microcontroller Core .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Figure 28: Microcontrollcr Phase 1
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Figure 29: Microcontroller Core Phase 2 .
`.
`.
`.
`.
`.
`.
`.
`. .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`. . .
`.
`.
`.
`.
`Figure 30: Microcontroller Core Phase 3 .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Figure 31: Burst Execution Hardware .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`. .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Figure 32: Synchronization Beacon Processing Hardware.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Figure 33: Duration Controller Architecture .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Figure 34: Basic Matched Filter Architecture .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`. . .
`.
`.
`.
`.
`.
`.
`.
`.
`Figure 35: Tree Adder Structure . .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`. .
`.
`.
`.
`.
`.
`. .
`.
`.
`.
`.
`.
`.
`.
`.
`Figure 36: Hybrid Comparison Algorithm .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`.
`
`.
`
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`
`Page 7
`
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`. .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`. .
`.
`.
`
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`
`. .32
`. .32
`. .33
`. .34
`. .34
`. .36
`. .38
`. .38
`. .39
`. .39
`. .39
`. .40
`. .40
`. .42
`. .43
`. .44
`
`
`
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Example Parallel Shift Register .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Tri-State Buffer Tapping Architecture .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Tapped Delay Line Parallelism .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`CZMOS register in transistor and schematic for111 .
`.
`.
`.
`.
`.
`.
`.
`.
`True Single Phase Clock Register .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Low—Power Frequency Divider Based Register Cell .
`.
`.
`.
`.
`.
`.
`Low Clock Load Register Design . .
`.
`.
`.
`.
`.
`.
`. .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Register Cell Power Consumption vs. Supply Voltage .
`.
`.
`.
`.
`.
`C—V Characteristic for a MOS Capacitor .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`BodyLAN'W Matched Filter Architecture .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Beacon Detect System Architecture .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Custom Integrated Circuit Architecture .
`.
`.
`. .
`.
`.
`.
`.
`.
`.
`.
`Expanded View of the BodyLANTM Controller Architecture .
`Modem Interface Architecture .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`
`Hardware to Determine Change in Port B .
`Timing of a Double-Byte Access .
`.
`.
`.
`.
`.
`.
`Port D Interface .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`
`.
`.
`.
`
`.
`.
`.
`.
`. .
`
`.
`.
`.
`
`.
`.
`.
`
`.
`
`.
`.
`.
`
`.
`
`.
`.
`.
`
`.
`
`.
`.
`.
`
`.
`
`.
`.
`.
`
`.
`.
`.
`
`. .
`
`.
`.
`.
`
`.
`
`.
`.
`.
`
`.
`
`.
`.
`.
`
`.
`
`.
`.
`.
`
`.
`
`.
`.
`.
`
`.
`
`.
`.
`.
`
`.
`
`.
`.
`.
`
`.
`
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`
`.
`.
`.
`
`.
`
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`. .
`.
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`. .
`.
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`. .
`.
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`
`. .45
`. .45
`. .46
`. .47
`. .47
`. .48
`. .48
`. .49
`. .49
`. .5 l
`. .52
`. .53
`. .54
`. .55
`
`.
`.
`.
`
`.
`
`.
`.
`.
`
`.
`
`.
`.
`.
`
`.
`
`.
`.
`. .
`.
`.
`
`.
`
`.
`
`.
`.
`.
`
`.
`
`.
`.
`.
`
`.
`
`.
`.
`.
`.
`. .
`
`. .57
`. .58
`. .58
`
`. .
`
`. .59
`
`Figure 37:
`Figure 33:
`Figure 39:
`Figure 40:
`Figure 41:
`Figure 42:
`Figure 43:
`Figure 44:
`Figure 45:
`Figure 46:
`Figure 47:
`Figure 48:
`Figure 49:
`Figure 50:
`Figure 51:
`Figure 52:
`Figure 53:
`Figure 54:
`Figure 55:
`Figure 56:
`Figure 57:
`Figure 58:
`Figure 59:
`Figure 60:
`
`Sensor Interface Architecture .
`
`.
`
`.
`Clock Division Chain Design .
`SRAM Controller Architecture .
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`. .
`
`.
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Delay vs. Supply Voltage for the Adder Tree .
`.
`.
`.
`_
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`BodyLANTM Controller Chip .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`. .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`Circuit Used to Measure Power Consumption in Hspice .
`Plot of Power Estimate Normalized to the Hspice Estimate for Increasing
`Circuit Complexity .
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`.
`
`.
`,
`
`.
`.
`
`.
`.
`. .
`.
`.
`
`. .59
`. .61
`
`. .62
`. .66
`. .63
`
`.
`
`.
`
`. .71
`
`Page 8
`
`
`
`Chapter 1: Overview of BodyLAN“"
`System
`
`The BodyLANW system is a low-power wireless communications system designed to
`
`operate within the sphere of the body. The wireless communications industry has been increas-
`
`ingly moving toward networks that communicate over smaller areas with lower power levels (see
`
`Table 1). Until recently most wireless communications was in the form of satellite transmissions.
`
`In the 90s, the mobile cellular phone industry has exploded and work has begun on short range
`
`wireless networks to communicate data (e.g. Xerox’s DigitalDesk [1] and Berkeley's InfoPad
`
`Project [2]). BodyLANTM proposes to take this progression one step further, by lowering the
`
`power consumption by more than an order of magnitude.
`
`
`
`
`
`Satellite [14]
`
`23,000 miles
`
`155 Mbls
`
`:0 — 100 W
`
`Mobile Cellular
`
`500- 1000 feet
`
`700 kbit/s
`
`.1 — 1 W
`
`Typical Bit Rate
`
`
`
`
`
`Phone [5]
`
`Wireless LAN [5]
`
`15-25 feet
`
`2 Mb./s
`
`.l - 1 mW
`
`
`
`
`
`
`BodyLANm
`
`6-10 feet
`
`200 kbit/s
`
`1-10 j.tW
`
`Table 1: Comparison for Various Wireless Networks
`
`The BodyLANT“ system is intended to augment human senses through the use of special-
`
`ized sensors and a computer interface. These sensors will provide the user with more detailed data
`
`than human senses alone. For example, where a user could determine approximate air temperature
`
`(hot, cool, etc.) with a BodyLANTM sensor the user could be provided with the exact air tempera-
`
`ture. The applications of this technology range from medical applications, such as non-invasive
`
`patient monitoring, to sports and fitness training, such as automated training logs.
`
`1.1 BodyLANW Network Configuration
`
`There are three major network configurations: Star, Ring, and Complete[3]. In the Star
`
`configuration, all communication occurs through a single central node, referred to as the Hub. In a
`
`Ring configuration messages are passed from node to node until the message reaches the desired
`
`node. In a Complete configuration all communication proceeds directly to the desired node.
`
`Page 9
`
`
`
`Figure la: Star Configuration
`
`Figure 1b: Ring
`Configuration
`
`Figure 1c: Complete
`Configuration
`
`Each node in a network can either be a complete system or a slave to another node. If the
`
`node is a complete system it has the ability to independently send data to and receive data from
`
`other nodes as well as accept input and deliver output to a user. If a node is a slave to another node
`
`the functionality can be reduced. For example, in a Star configuration system the Hub can conve-
`
`niently control all the communications, therefore the functionality of the other nodes can be
`
`reduced.
`
`The Star configuration is preferable for low-power applications because of the distribution
`
`of the power consumption. For the BodyLANTM system reducing the power consumption is
`
`important because reducing the power consumption is equivalent to reducing the weight. In a Star
`
`configuration it is possible to partition computation such that most of the functionality resides in a
`
`single location, the Hub. Concentrating the functionality in one location translates to concentrat-
`
`ing the power dissipation (and the weight) in a single node while each of the other nodes can be
`
`implemented with the minimum functionality and weight. This translates to a system with a single
`
`centralized weight source, which can be worn where the effect of the weight is minimized (i.e., on
`
`the waist or back) and a large number of extremely small light functional blocks. If a Ring or
`
`Complete configuration is used, all the nodes in the system are identical since the functionality of
`
`each of the nodes must be the same due to the fact each node has an identical connection to the
`
`network. Therefore, a functional block worn on the wrist would need to be the same size and
`
`weightas a iglgck worn on the waist, which is not reasonable.
`The Star configuration should also dissipate the minimum amount of power for the Body-
`
`LANT“ application. The purpose of the BodyLANT“ network is to gather information and pro-
`
`vide the information to a user. If the user is assumed to be in a single location the information can
`
`be sent to the user in a single transmission using either the Star or Complete configurations. Using
`
`Page 10
`
`
`
`a Ring configuration it would take an average of M4 transmissions where n is the number of nodes
`
`in the system. In the Complete configuration each node has a channel to all of the other nodes,
`
`however, if these channels are not necessary (as in the BodyLANT” system) providing those
`
`channels dissipates excess energy. Therefore, the Star network configuration is used for the Body-
`
`LANT” application because the weight distribution of the Star configuration is optimal and the
`
`type of communications necessaly (i.e., sensors gathering information for a single user) favors the
`
`Star configuration.
`
`1.2 BodyLAN““ Communications Protocol
`
`There are many methods of dividing access to a communications channel, three of which
`
`are: by time, by frequency and by code. When a channel is divided by time, Time Division Multi-
`
`ple Access (TDMA), each node has a scheduled time to use the channel and is inactive during all
`
`other times. VVher1 a channel is divided by frequency, Frequency Division Multiple Access
`
`(FDMA), each node communicates using a different frequency range and all nodes can be active
`
`all the time. When a channel is divided by code, CDMA, all the nodes share time and frequency
`
`as in Direct Sequence Spread Spectrum (DSSS) where the data is modulated by a high speed code
`
`such that a receiver with the same code receives the data with little additional noise from other
`
`channels.
`
`The Time Division Multiple Access protocol is the natural choice for Iow—power applica-
`
`tions since there is an inherent low-power (inactive) mode. Depending on the data rate the system
`
`can be in the low-power mode for a significate portion of the time. The duty cycle for a TDMA
`
`system will be defined as the data rate the system is being used at divided by the maximum data
`
`rate of the system. For example if a TDMA system where the data is transmitted at 200 kbitsfs is
`
`being used at 2 kbitfs, the duty cycle is 1:100. The average power dissipated in a TDMA system is
`
`given by Eq. 1, where dis the duty cycle for the system.
`
`PTDMA
`
`= dP
`
`active
`
`+ (1 — d) P
`
`inactive
`
`Eq. 1
`
`The Frequency Division Multiple Access protocol is unsuitable for low-power applica-
`
`tions. By definition, FDMA protocol involves establishing a continuous link between each node
`
`and the Hub (in a Star configuration) at different frequencies [4]. Maintaining these continuous
`
`links while there is no data transmission causes the power dissipation to be higher.
`
`The Code Division Multiple Access protocol has been used for low power communica-
`
`Page 11
`
`
`
`tions [5]. A CDMA link can have the same inherent low-power mode (and duty cycle) as a TDMA
`
`system. The addition of the code to the signal causes excess power dissipation as in DSSS where
`
`the data must be transmitted at a much higher rate, the chip rate, which is typically orders of mag-
`
`nitude laiger than the data rate [4].
`
`For the BodyLAN'”"' system the TDMA communications protocol is preferred over the
`
`CMDA protocol. To implement the BodyLANT“ system at the lowest possible power level it is
`
`critical to power—down the RF hardware as much as possible, since the RF hardware can consume
`
`up to 5 mW while active continuously. Since the RF section is completely powered down during
`
`the interval between communications bursts, the receiver must re—synchronize for each burst.
`
`Synchronizing a TDMA system consists of synchronizing the receiver symbol clock to the trans
`
`mitter symbol clock. Using a voltage controlled crystal oscillator the frequency will not vary
`
`much and synchronization can be maintained during power down by storing the control voltage
`
`on a capacitor. If the voltage is stored on a large capacitor through low-leakage components (ie.,
`
`high quality diodes) the control voltage degradation should be minimized. Synchronizing a
`
`CDMA system involves synchronizing the receiver and transmitter code generators as well as
`
`symbol clocks. Again, using a voltage controlled crystal oscillator the code lock can be main-
`
`tained during power down by running the Code generator continuously. If the code generator is not
`
`run continuously, the code must be reacquired before every transmission, greatly increasing the
`
`burst length necessary. For an extremely low power system neither of these options is acceptable.
`
`A code generator running continuously at even 10 times the data rate would consume more power
`
`than the rest of the system. Increasing the active period of the RF sections would greatly increase
`
`the power consumed and decrease the effective data rate (due to the time spent synchronizing the
`
`code). Therefore. the BodyLANW system is designed to use a TDMA communications protocol.
`
`1.3 BodyLANTM Architecture
`
`The BodyLANTM architecture consists of two components a central Hub and many indi-
`
`vidual nodes, called Personal Electronic Assistants (PEAS). The Hub is responsible for interfacing
`
`with the user, controlling the overall TDMA schedule and gathering and processing the data from
`
`the PEAS. The PEAS are responsible for initializing the connection to the network, gathering data
`
`and transmitting the data to the Hub.
`
`The Hub system consists of two major components: the central Hub computer and the
`
`BodyLANT“ controllerlmodem interface card. The central Hub computer is responsible for pre-
`
`Page 12
`
`
`
`Wireless Links
`
`PEA#1
`
` PEA#2
`
`PEA#3
`
`Figure 2: BodyLAN'““ Architecture
`
`senting the data gathered from the PEAs in a format that is acceptable to the user. The Body-
`
`LANW controllerfmodem interface card is a PCMICIA card that is responsible for the TDMA
`
`scheduling and gathering and processing data from the PEAS.
`
`TDMA Scheduling
`
`
`User H PEAS
`I
`
`Figure 3: PCM/CIA Interface Architecture
`
`The Personal Electronic Assistants (PEAS) are the heart of the BodyLANTM system. The
`
`PEAS provide all the specialized functionality for the system. A typical PEA will consist of four
`
`major components: one or more sensors, a radio modem, a microprocessor and a custom control-
`
`ler integrated circuit. The sensor(s) are responsible for collecting data, which can be provided to
`
`the user through the Hub computer. The radio modem provides a wireless link between the PEA
`
`and the Hub computer. The microprocessor handles the higher level data processing functions that
`
`need to be performed locally (e.g. computing the amount of phase correction for the symbol
`
`clock) and provides flexibility due to it's programmable nature. Once the system functionality has
`
`been proven and the need for flexibility has decreased the microprocessor functionality will be_
`
`moved onto the controller integrated circuit. The custom controller integrated circuit provides the
`
`control of the entire sensor system.
`
`The BodyLAN'”“ controller integrated circuit is responsible for synchronizing and con-
`
`trolling the interaction between the PEA and the Hub computer. The custom integrated circuit is
`
`Page 13
`
`
`
`Hub
`
`Environment
`
`
`
`Microprocessor
`
`Controller
`
`Figure 4: PEA Architecture
`
`responsible for determining if there is a Hub present and initializing the communications link with
`
`that Hub. The custom integrated circuit is responsible for providing the information needed to
`
`phase—lock the local symbol clock to the Hub symbol clock. The custom integrated circuit is
`
`responsible for controlling the interaction of the Hub and the PEA, including maintaining the
`
`phase—locl<, extracting data from the sensors and transmitting it to the Hub, providing a channel
`
`for communications between the microprocessor and the Hub and controlling the Command and
`
`Control Channel (CCC) interaction. The architecture of the custom integrated circuit is derived
`
`Micro-
`
`
`
`Sensor
`
`PYOCCSSOF
`
`Microprocessor
`Intel-face
`
`Sensor Interface
`
`
`
`_
`_
`Signal Processing
`
`_
`Mlcrocontroller
`
`
`
`
`ModemInterface
`
`Modem I
`
`Figure 5: Custom Controller Integrated Circuit Architecture
`
`from the dual functionality of handling the synchronization and communications. There is a sig—
`
`nal processing block which handles attaching the PEA to the BodyLANTM network and a rnicro—
`
`controller block which handles the TDMA plan execution. The rest of the blocks interface to the
`
`rest of the system.
`
`1.4 BodyLANT” System Power Consumption
`
`The power consumption of the BodyLANT” system must be minimized to provide a sys-
`
`tem that is convenient from a user’s perspective. In normal use, there will be a single Hub and
`
`many PEAS. While changing the battery in a single centralized Hub with regularity is acceptable,
`
`much in the same way replacing the batteries in notebook computers is acceptable, changing the
`
`batteries in a PEA with regularity is not acceptable, much in the same way changing a watch bat-
`
`Page 14
`
`
`
`tery with regularity is not acceptable. Therefore, the power dissipation in the PEA must be mini-
`
`mized.
`
`The PEA can be broken down into four components: the radio modem, the microproces-
`
`sor, the sensor and the controller. The radio modem has been designed at Bolt Beranek and New-
`
`man to comply with FCC regulation. The microprocessor was chosen after comparing the power
`
`consumption of a number of microprocessors. The design of low power sensors is an area for fur-
`
`ther research and the design of the controller is the focus of this thesis.
`
`The BodyLANTM radio modem has been designed to comply with the regulations of the
`
`Federal Communications Commission (FCC). The FCC Part 15 Specification allows for unregu-
`
`lated transmission in the 320-400 Mhz band as long as the field strength is below 200 tLW'm at 3
`
`meters [15]. The BodyLAN“"' radio modem consists of two independent sections, one for trans-
`
`mission and one for reception. The transmission section consumes 1 mA at 3 V when active and
`
`the receiver consumes 1.6 mA at 3 V when active. Including the overhead time needed to power-
`
`up the oscillators transmission can be accomplished at 2 nJfbit and reception can be accomplished
`
`at 3 nlfbit, using 4-bit bursts. This translates to a power dissipation of 5 p.W per lcbitfs of commu-
`
`nications bandwidth.
`
`The PIC l6C64 microprocessor manufactured by MicroChip Corporation was selected for
`
`use in the BodyLANT” system. The PIC16C64 exhibited the lowest power consumption per
`
`instruction of any microprocessor examined. The PIC16C64 can execute 4 million instructions
`
`while dissipating 2mA at 3 V. This gives a cost of 1.511] per instruction. The goal of this project
`
`was to design the digital controller such that the magnitude of the power consumed by the control-
`
`ler was equal to or less than the power consumed by the rest of the system. Both the radio modem
`
`and the microprocessor function in the microwatt power range, so the power consumption of the
`
`controller should be in the rnicrowatt range.
`
`Page 15
`
`
`
`Chapter 2: Review of Low-Power Design
`Principles
`
`The purpose of this chapter is to provide a quick review of low-power design principl