LG ELECTRONICS, INC.,
`LG ELECTRONICS, INC.,
`V.
`ADVANCED MICRO DEVICES, INC.
`
`CASE IPR2015-00324
`U.S. PATENT NO. 6,895,520
`Petitioner’s Hearing Demonstratives | Hearing Date: February 10 2016
`
`1
`
`
`LG ELECTRONICS, INC.,
`V.
`ADVANCED MICRO DEVICES, INC.
`
`CASE IPR2015-00324
`U.S. PATENT NO. 6,895,520
`Petitioner’s Hearing Demonstratives | Hearing Date: February 10 2016
`
`1
`
`
`
`INSTITUTED GROUNDS
`
`• Anticipation of claims 16-18 over Bertin
`• Obviousness of claims 20-23 over Bertin
`• Anticipation of claims 16-18 over Gunther
`• Obviousness of claims 20-23 over Gunther and ACPI
`• Obviousness of claims 20-23 over Gunther and ACPI
`
`2
`
`
`
`CLAIMS 16-18 ARE ANTICIPATED BY BERTIN
`
`Pet. at 14 citing Ex. 1003 at Fig. 1B
`
`3
`
`
`
`PATENT OWNER ONLY CHALLENGES THREE LIMITATIONS
`
`• [16.A]/ [23.A]
`“utilization circuits respectively associated with the functional
`blocks and coupled to provide block utilization information of
`the functional blocks.” Resp. at 27-29.
`• [16.B]/[23.B]
`• [16.B]/[23.B]
`“independently adjust power consumption levels of the
`functional blocks to match respective block utilization levels”
`Resp. at 29-32.
`• [17.A]
`“wherein at the power consumption levels of the functional
`blocks are determined at least in part by independently
`adjustable clock frequencies of respective clocks being
`supplied to the functional blocks..” Resp. at 32-40.
`
`4
`
`
`
`CLAIMS 16 & 23
`
`CLAIM
`
`16/23
`
`[16.A]/[23.A]
`
`[16.B]/[23.B]
`[16.B]/[23.B]
`
`[16.C]/[23.C]
`
`TEXT
`
`An integrated circuit comprising
`a computer system comprising
`
`a plurality of functional blocks;
`an integrated circuit that includes a plurality of functional blocks
`
`utilization circuits respectively associated with the functional blocks and coupled
`utilization circuits respectively associated with the functional blocks and coupled
`to provide block utilization information of the functional blocks
`utilization circuits respectively associated with the functional blocks and coupled
`to provide block utilization information of the functional blocks
`
`the integrated circuit is responsive to the block utilization information to
`independently adjust power consumption levels of the functional blocks to
`match respective block utilization levels
`a computer program including an instruction sequence executable by the
`integrated circuit to adjust power consumption levels of the functional blocks to
`match respective block utilization levels according to the block utilization
`information
`
`5
`
`
`
`CLAIM [16.B]/[23.B]
`Construction:“utilization circuits respectively associated with the functional
`blocks and coupled to provide block utilization information of the functional
`blocks”
`
`Ex. 1035 at par. 6
`
`6
`
`
`
`CLAIM [16.B]/[23.B]
`Construction: “utilization circuits respectively associated with the functional
`blocks and coupled to provide block utilization information of the functional
`blocks”
`
`Ex. 1035 at par. 8
`
`7
`
`
`
`CLAIM [16.B]/[23.B]
`Construction: “utilization circuits respectively associated with the functional
`blocks and coupled to provide block utilization information of the functional
`blocks”
`
`Ex. 1034 at 107:2-22
`
`8
`
`
`
`CLAIM [16.B]/[23.B]
`“utilization circuits respectively associated with the functional blocks and
`coupled to provide block utilization information of the functional blocks”
`
`Pet. at 10
`
`9
`
`
`
`CLAIM [16.C]/[23.C]
`Construction :“adjust power consumption levels of the functional blocks to
`match respective block utilization levels”
`“responsive to the block utilization information” [16.C]/”according to the block
`utilization information” [23.C]
`
`Ex. 1035 at par. 15-16
`
`10
`
`
`
`CLAIM [16.C]/[23.C]
`Construction:“adjust power consumption levels of the functional blocks to
`match respective block utilization levels”
`“responsive to the block utilization information” [16.C]/”according to the block
`utilization information” [23.C]
`
`Ex. 1001 at 7:43-50; 1035 at par. 19
`
`11
`
`
`
`CLAIM [16.C]/[23.C]
`“adjust power consumption levels of the functional blocks to match respective
`block utilization levels”
`“responsive to the block utilization information” [16.C]/”according to the block
`utilization information” [23.C]
`
`Ex. 1003 at 6:41-57
`
`12
`
`
`
`CLAIMS 17-18
`
`CLAIM
`
`TEXT
`
`[17]
`
`[17.A]
`
`[18]
`
`The integrated circuit as recited in claim 16
`wherein at the power consumption levels of the functional blocks are
`determined at least in part by independently adjustable clock frequencies of
`respective clocks being supplied to the functional blocks.
`
`The integrated circuit as recited in claim 17 wherein the power consumption
`levels of the functional blocks are determined at least in part according to
`independently controllable voltages being supplied to respective ones of the
`independently controllable voltages being supplied to respective ones of the
`functional blocks.
`
`13
`
`
`
`CLAIMS 20-22
`
`CLAIM
`
`TEXT
`
`[20]
`
`[21]
`
`[22]
`[22]
`
`The integrated circuit as recited in claim 16 further comprising registers
`associated with respective utilization circuits of the functional blocks containing
`block utilization information.
`
`The integrated circuit as recited in claim 16 wherein the utilization circuits are
`software accessible.
`
`The integrated circuit as recited in claim 16 further including software operable
`The integrated circuit as recited in claim 16 further including software operable
`on the integrated circuit to read utilization information of a selected functional
`block and to control at least one power performance parameter of the selected
`functional block in response thereto.
`
`14
`
`
`
`CLAIM [17.A]
`Construction: “wherein at the power consumption levels of the functional
`blocks are determined at least in part by independently adjustable clock
`frequencies of respective clocks being supplied to the functional blocks.”
`
`Ex. 1035 at par. 59 citing Ex. 1031 at 1:66-2:10
`
`15
`
`
`
`CLAIM [17.A]
`“wherein at the power consumption levels of the functional blocks are
`determined at
`least
`in part by independently adjustable clock
`frequencies of respective clocks being supplied to the functional
`blocks.”
`
`Ex. 1002 at par. 111 citing Ex. 1003 at 9:81-12.
`
`16
`
`
`
`CLAIMS 20-23 ARE RENDERED OBVIOUS BY BERTIN
`
`Pet. at 14 citing Ex. 1003 at Fig .1B
`
`17
`
`
`
`CLAIMS 20-23
`
`CLAIM
`
`TEXT
`
`[20]
`
`[21]
`
`[22]
`[22]
`
`[23]
`
`The integrated circuit as recited in claim 16 further comprising registers
`associated with respective utilization circuits of the functional blocks containing
`block utilization information.
`
`The integrated circuit as recited in claim 16 wherein the utilization circuits are
`software accessible.
`
`The integrated circuit as recited in claim 16 further including software operable
`The integrated circuit as recited in claim 16 further including software operable
`on the integrated circuit to read utilization information of a selected functional
`block and to control at least one power performance parameter of the selected
`functional block in response thereto.
`
`A computer system comprising:
`an integrated circuit that includes a plurality of functional blocks;
`utilization circuits respectively associated with the functional blocks and coupled
`to provide block utilization information of the functional blocks; and
`a computer program including an instruction sequence executable by the
`integrated circuit to adjust power consumption levels of the functional blocks to
`match respective block utilization levels according to the block utilization
`information.
`
`18
`
`
`
`PATENT OWNER ONLY MAKES ONE ARGUMENT
`
`• AMD does not allege that any limitations are missing from the
`modified Bertin, except those redundant limitations already
`discussed above with respect to anticipation.
`• Alleges no motivation to modify because software capabilities
`would slow down Bertin and/or use too many registers.
`would slow down Bertin and/or use too many registers.
`
`19
`
`
`
`CLAIMS 20-23 ARE RENDERED OBVIOUS BY BERTIN
`
`Ex. 1002 at par. 155; Ex. 1035 at par. 64
`
`20
`
`
`
`CLAIMS 20-23 ARE RENDERED OBVIOUS BY BERTIN
`
`CLAIMS 20-23 ARE RENDERED OBVIOUS BY BERTIN
`
`63-
`
`This type ef feature ean he irnplernentetl, fer e;-tanaple, using a simple
`
`legie ein: uit that triggers a predetermined time perie-Ll using a rnenestahle
`
`1'I1L1Iti1.'i|:r1::_=tt-El-1' talse lsnewn as a ene-shet] and mis signal ean he legieally Ahlfled
`
`with an a+.:fi1.'it}' ntenitering signal. This eireuit, eentnrising a handful e1" legie
`
`gates and hardly “tee many registers,” as Dr- Lew.-itt argues, ean determine an
`
`arljitrflfilg.-' high perie-:1 ef tirne witheut aetiw.-ity and triggers me pewering elewn er
`
`up vi‘ funsfinnal units
`
`Ex. 1035 at par. 68
`Ex. 1035 at par. 68
`
`21
`21
`
`
`
`CLAIMS 16-18 AND 20 ARE ANTICIPATED BY GUNTHER
`
`Pet. at 31 citing Ex. 1004 at Fig. 3
`
`22
`
`
`
`PATENT OWNER ONLY CHALLENGES THREE LIMITATIONS
`
`• [16.c]/[23.c]
`“adjust power consumption levels of the functional blocks to
`match respective block utilization levels” Resp. at 43, 45-50.
`• [18.pre] / [17.a]
`“independently adjustable clock frequencies.” Resp. at 43, 50-52.
`“independently adjustable clock frequencies.” Resp. at 43, 50-52.
`• [18.a]
`“independently adjustable voltages.” Resp. at 43, 50-52.
`
`23
`
`
`
`CLAIMS 16 & 23
`
`CLAIM
`
`16/23
`
`[16.A]/[23.A]
`
`[16.B]/[23.B]
`[16.B]/[23.B]
`
`[16.C]/[23.C]
`
`TEXT
`
`An integrated circuit comprising
`a computer system comprising
`
`a plurality of functional blocks;
`an integrated circuit that includes a plurality of functional blocks
`
`utilization circuits respectively associated with the functional blocks and coupled
`utilization circuits respectively associated with the functional blocks and coupled
`to provide block utilization information of the functional blocks
`utilization circuits respectively associated with the functional blocks and coupled
`to provide block utilization information of the functional blocks
`
`the integrated circuit is responsive to the block utilization information to
`independently adjust power consumption levels of the functional blocks to
`match respective block utilization levels
`a computer program including an instruction sequence executable by the
`integrated circuit to adjust power consumption levels of the functional blocks to
`match respective block utilization levels according to the block utilization
`information
`
`24
`
`
`
`CLAIM [16.C] /[23.C]
`Construction: “Independently adjust power consumption levels of the
`functional blocks to match respective block utilization levels”
`
`Ex. 1001 at 1:34-59
`
`25
`
`
`
`CLAIM [16.C] /[23.C]
`Construction: “Independently adjust power consumption levels of the
`functional blocks to match respective block utilization levels”
`
`Ex. 1035 at par. 25
`
`26
`
`
`
`CLAIM [16.C] /[23.C]
`Construction: “Independently adjust power consumption levels of the
`functional blocks to match respective block utilization levels”
`
`Ex. 1001 at 7:33-50
`
`27
`
`
`
`CLAIM [16.C] /[23.C]
`Construction: “Independently adjust power consumption levels of the
`functional blocks to match respective block utilization levels”
`
`Ex. 1001 at 4:8-15
`
`28
`
`
`
`CLAIM [16.C] /[23.C]
`“Independently adjust power consumption levels of the functional blocks to
`match respective block utilization levels”
`
`It below.
`
`Ex. 1004 at 10:62-11:2
`
`29
`
`
`
`CLAIMS 17, 18
`
`CLAIM
`
`TEXT
`
`17
`
`[17.A]
`
`
`
`1818
`
`[18.A]
`
`The integrated circuit as recited in claim 16 wherein
`
`at the power consumption levels of the functional blocks are determined at least in part by
`independently adjustable clock frequencies of respective clocks being supplied to the
`functional blocks.
`
`
`
`The integrated circuit as recited in claim 17 whereinThe integrated circuit as recited in claim 17 wherein
`
`the power consumption levels of the functional blocks are determined at least in part
`according to independently controllable voltages being supplied to respective ones of the
`functional blocks.
`
`30
`
`
`
`CLAIMS [17.A]/[18.A]: THERE IS NO DISPUTE THAT EACH LIMITATION IS
`DISCLOSED BY GUNTHER
`“independently adjustable clock frequencies”
`“independently adjustable voltages”
`
`ç
`
`It below.
`
`Ex. 1004 at 5:54-61
`
`31
`
`
`
`CLAIMS [17.A]/[18.A]: THERE IS NO DISPUTE THAT EACH LIMITATION IS
`DISCLOSED BY GUNTHER
`“independently adjustable clock frequencies”
`“independently adjustable voltages”
`
`ç
`
`It below.
`
`Ex. 1004 at 10:67-11:8
`
`32
`
`
`
`CLAIMS [17.A]/[18.A]
`“independently adjustable clock frequencies”
`“independently adjustable voltages”
`
`It below.
`
`It below.
`
`Ex. 1034 at 85:11-24
`
`33
`
`
`
`CLAIMS 20-23 ARE OBVIOUS IN VIEW OF GUNTHER IN VIEW OF
`ACPI
`
`Ex. 1002 at par. 127 citing Ex. 1006 at 38
`
`34
`
`
`
`PATENT OWNER ONLY MAKES THREE ARGUMENTS
`
`• The combination allegedly does not render obvious:
`
`[23.C] “adjust power consumption levels of the functional
`blocks to match respective block utilization levels” Resp. at 55.
`• A POSA allegedly would not combine ACPI with Gunther. Resp. at
`• A POSA allegedly would not combine ACPI with Gunther. Resp. at
`55-56.
`• ACPI allegedly is not a printed publication. Resp. at 57-58.
`
`35
`
`
`
`COMBINATION OF GUNTHER WITH ACPI
`
`Ex. 1035 at par. 91 citing Ex. 1006 at 38-39
`
`36
`
`
`
`ACPI IS A PRIOR ART PUBLICATION
`
`Reply at 24
`
`37
`
`
`
`ACPI IS A PRIOR ART PUBLICATION
`
`Ex. 1036 at par. 9, 16
`
`38
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