(12> Ulllted States Patent
`Helms et al.
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`US 6,889,332 B2
`May 3, 2005
`
`US006889332B2
`
`(54) VARIABLE MAXIMUM DIE TEMPERATURE
`BASED ON PERFORMANCE STATE
`
`(75) Inventors: Frank P. Helms, Round Rock, TX
`(US); J e?'rey A. Brinkley, Georgetown,
`TX (US)
`
`(73) Assignee: Advanced Micro Devices’ Inc"
`Sunnyva1e> CA (Us)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U_S_C_ 154(k)) by 554 days_
`
`( * ) Notice:
`
`_
`(22) F1169:
`(65)
`
`Dec‘ 11’ 2001
`Prior Publication Data
`
`US 2003/0110423 A1 Jun. 12, 2003
`
`nt.
`
`.
`
`................................................ ..
`
`EP
`JP
`JP
`
`FOREIGN PATENT DOCUMENTS
`0 632 360 A1
`1/1 995
`08328698
`12/1996
`10198456 A
`7/1998
`
`OTHER PUBLICATIONS
`
`IBM Technical Disclosure Bulletin, “PoWer Management
`Clock Change for 603 Processor,” vol. 38, No. 12, Dec.
`1995’ pp’ 325_327'_
`_
`_
`PC NTMMTA: Using Performance Monitor With MMTA
`(Q130288),
`http://support.microsoft.com/default.aspX?s
`cid=kb;en—us;Q130288 (3 pages) (last modi?ed Aug. 8,
`
`Performance Monitor Collects Data for Only One Instance
`(Q101474),
`http://support.microsoft.com/default.aspX?s
`cid=kb;en—us;Q[0]474 (2 pages) (last modi?ed Nov. 5,
`1999), printed Apr. 16, 2002.
`
`Primary Examiner—A. Elamin
`ttorne ,
`ent, 0r zrm— a or1n
`
`r1en
`
`ra am
`
`(52) US. Cl. ...................... .. 713/322; 713/501; 702/132
`
`(57)
`
`ABSTRACT
`
`(58) Field of Search ............................... .. 713/322, 501;
`702/132
`
`(56)
`
`References Cited
`
`713/501
`
`Us. PATENT DOCUMENTS
`5502 838 A * 3/1996 Kikinis
`5’511’2O3 A
`4/1996 Wisor et' """"""""" "
`5’682’273 A 10/1997 Hetzler
`'
`5,713,030 A * 1/1998 Evoy ........................ .. 713/322
`5’745’375 A
`4/1998 Reinhardt et a1‘
`517521011 A * 5/1998 Thomas et aL ___________ __ 713/501
`5,812,860 A
`9/1998 Horden et aL
`5,838,968 A 11/1998 Culbert
`5,852,737 A 12/1998 Bikowsky
`5,873,000 A
`2/1999 Lin et a1_
`5,881,298 A
`3/1999 Cathey
`5,884,049 A
`3/1999 Atkinson
`5,887,179 A
`3/1999 Halahmi et a1.
`5,925,133 A
`7/1999 Buxton et a1.
`5,954,820 A
`9/1999 HetZler
`(Continued)
`
`The maximum performance state available to a processor in
`a computer system, in terms of operating frequency and/or
`voltage, changes according to thermal criteria. When the
`temperature Increases above a predetermined threshold, the
`maximum performance state available is reduced. Multiple
`temperature thresholds may be utilized providing for a
`gradually reduced maximum performance state as tempera
`ture Increases. When the temperature returns to' a loWer
`level’ the maxlmum perfofmance Slate avallable 1S
`Increased. Changing the maximum available performance
`state according to temperature provides for more gradual
`reduction in performance as temperature increases, Which
`results in higher average system performance as temperature
`increases. Thus, a more gradual reduction in performance is
`provided While still maintaining a high speed rating of the
`processor in more ideal conditions. In normal operating
`conditions, high processor performance is provided, While
`slightly reduced performance is provided in abnormal oper
`a?ng CQndi?Qns~
`
`21 Claims, 4 Drawing Sheets
`
`| _______________ '1
`i W POWER MANAGEMENT CONTROL
`1
`I
`s
`9.1:.
`l 303\
`I331
`:V'D
`vomes
`I \
`REGULATOR
`$ |
`305
`|
`l
`
`CORE
`CLOCK
`
`K305
`
`LG Ex. 1001, pg 1
`
`

`
`US 6,889,332 B2
`Page 2
`
`US. PATENT DOCUMENTS
`
`9/1999 Bamls
`59587058 A
`6,006,248 A 12/1999 Nag,“
`6’014’611 A
`1/2000 Am‘ “31'
`6,073,244 A
`6/2000 IWaZakl
`6076171 A
`60000 Kawata
`R’E36’839 E
`8/2000 Simmons et a1‘
`3
`.
`.
`6,119,241 A * 9/2000 Mlchall et a1. ........... .. 713/322
`6,128,745 A 10/2000 Anderson
`6,151,681 A 11/2000 Roden et a1.
`
`6,363,490 B1 * 3/2002 Senyk ...................... .. 713/300
`6,442,700 B1
`8/2002 Cooper
`6,574,740 B1
`6/2003 Odaohhara et 211.
`6,594,753 B2
`7/2003 Choquette et a1.
`6,630,754 B1 * 10/2003 Pippin ...................... .. 307/117
`*
`6,647,320 B1
`11/2003 1116116
`.700/300
`6,701,273 B2 * 3/2004 Nlshlgakl et a1. ......... .. 702/132
`6 711 129 B1
`3/2004 Bauer et 211.
`’
`’
`
`* cited by examiner
`
`LG Ex. 1001, pg 2
`
`

`
`U.S. Patent
`
`May 3,2005
`
`Sheet 1 0f 4
`
`US 6,889,332 B2
`
`I
`
`START
`
`I
`
`CD———————+ V
`1 O1
`PERIODICALLY
`DETERMINE CPU ’\/
`UTILIZATION
`
`V
`
`INCREASE
`PERFORMANCE
`
`I03
`
`I07
`
`UTILIZATION <
`LOW TRIGGER?
`
`N0
`
`DECREASE
`‘09f PERFORMANCE
`
`FIG. 2
`
`LG Ex. 1001, pg 3
`
`

`
`U.S. Patent
`
`May 3,2005
`
`Sheet 2 0f 4
`
`US 6,889,332 B2
`
`317
`\‘
`A
`
`REGULATOR
`3i
`
`306
`
`:
`l
`|
`I 303
`I k“
`VOLTAGE 4 IV")
`vOLTAGE
`I 1
`l
`|
`l
`‘——>1 310
`1 r’
`:
`|
`|
`1
`l
`
`BUS
`HP ""
`
`POWER MANAGEMENT cONTROL
`319
`CLOCK
`GENERAT1ON ’\J/
`CIRCUIT
`/_\:/307
`1‘
`304i
`EREO ‘\J |
`:
`1
`CORE
`CLOCK I
`1
`:
`I
`1 |
`:
`|
`'
`l
`L ________________ __|
`
`+
`
`COUNT
`
`1
`@055
`
`309
`
`313
`v
`
`CPU CORE
`LOGIC
`
`313
`
`II
`
`301
`
`LG Ex. 1001, pg 4
`
`

`
`U.S. Patent
`
`May 3,2005
`
`Sheet 3 0f 4
`
`US 6,889,332 B2
`
`FIG. 4
`
`Temperature
`
`Type of Trip Point
`
`Action
`
`Available
`Performance
`States
`
`Tem
`Ran l;
`9
`
`103C
`
`Critical Trip Point
`
`98C
`
`280C
`
`Passive Trip Point
`(max active cooling)
`Maximum Pstate
`Change
`
`05 performs
`orderly shut down
`05 throttles
`processor (50%) P2, P3, P4
`Transition to
`PstateZ as max
`
`>8OC
`
`378C
`
`Maximum Pstate
`Change
`
`Transition to
`Pstatel as max
`
`270C
`
`368C
`
`55[
`
`60C
`
`50[
`
`Maximum Pstate
`Change
`
`Transition to
`Pstatel as max
`
`Maximum Pstate
`Change
`
`Transition to
`Pstate 0 as max
`
`Active trip point 2
`(max active cooling)
`Active trip point 3
`(med active cooling)
`Active trip point 4
`(min active cooling)
`
`Turn on Fan
`100%
`Turn on Fan 66%
`
`Turn on Fan 33%
`
`P1, P2, P3,
`P4
`
`7080C
`
`PO, Pl, P2,
`P3, P4
`
`<7OC
`
`LG Ex. 1001, pg 5
`
`

`
`U.S. Patent
`
`May 3,2005
`
`Sheet 4 0f 4
`
`US 6,889,332 B2
`
`TIJ
`
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`LG Ex. 1001, pg 6
`
`

`
`US 6,889,332 B2
`
`1
`VARIABLE MAXIMUM DIE TEMPERATURE
`BASED ON PERFORMANCE STATE
`
`BACKGROUND
`
`1. Field of the Invention
`This invention relates to computer systems and more
`particularly to poWer management of computer systems.
`2. Description of the Related Art
`An important market criteria for microprocessors is the
`rated frequency at Which the microprocessor operates, typi
`cally denominated in hundreds of MHZ or GHZ. Rated
`frequency is used as a surrogate for performance and higher
`performance processors command higher prices. Thus, it is
`advantageous to market processors With the highest possible
`frequency rating.
`HoWever, there are limitations as to hoW high one may
`rate a processor in terms of frequency. As the number of
`transistors provided on a single integrated circuit has
`increased and the clock speed of integrated circuits has
`increased, poWer and related thermal considerations have
`become an important consideration in computer design.
`PoWer and thermal considerations can limit processor per
`formance in certain environments, particularly in mobile
`applications. Computer systems measure the die temperature
`or case temperature using sensors on or close to the proces
`sor. In order to keep processor die temperatures Within safe
`bounds to avoid potential damage to the processor, passive
`and active cooling have traditionally been employed to
`control temperature. Passive cooling has been accomplished
`by reducing a processors clocks speed, either by throttling
`processor clocks (reducing effective frequency by turning
`clocks off for a predetermined period) or by reducing actual
`frequency of the clocks. Reducing the actual and/or effective
`frequency of an integrated circuit causes a reduction in
`poWer consumption and thus reduces temperature. In addi
`tion to reducing clock frequency, it is knoWn in the art to
`reduce voltage in conjunction With reduced clock speed to
`achieve additional cooling.
`Thus, the rated processor speed can be limited by poWer
`and thermal considerations and more speci?cally is
`determined, at least in signi?cant part, by operating
`frequency, voltage, and temperature. If the die temperature
`can be kept suf?ciently loW, the rated processor clock speed
`can be increased. In one prior art approach to maXimiZing
`frequency at Which a processor can be marketed, the pro
`cessor includes an on-die temperature sensor that automati
`cally throttles (reduces) the CPU’s clock by 50% if the
`processor’s temperature crosses a factory set threshold. If
`the maXimum die temperature is set at a suf?ciently loW
`level of, e.g., 70 degrees C., the processor is able to meet the
`timing budget for the silicon process in Which it is manu
`factured at a higher frequency at a given voltage than if the
`die temperature Was signi?cantly higher. The timing budget
`is the amount of time a signal has to propagate through
`combinational logic from one set of storage elements (e.g.,
`?ip-?ops) to another set of storage elements and meet the
`setup and hold times associated With the ?ip-?ops. At a
`loWer temperature, a device can more easily meet a timing
`budget because, e.g., the propagation delays are reduced.
`Thus, to ensure that timing budgets are met, in the prior art
`approach described above, When the maXimum die tempera
`ture associated With the device is crossed, e.g., 70 degrees
`C., the processor clock is throttled back to, e.g., 50% of its
`rated speed, Which reduces the poWer consumption and thus
`the temperature. Thus, a processor rated at 2 GHZ Would run
`
`2
`at 1 GHZ upon crossing of the maXimum die temperature
`threshold. In that Way the processor can be rated at a higher
`speed at or beloW 70 degrees C., although it may operate
`With signi?cantly reduced capability above that temperature.
`While that alloWs the processor to be rated highly, it also
`results in a system that operates at a signi?cantly loWer clock
`speed in certain environments. It Would be desirable to ship
`more higher speed rated processors Without having to dras
`tically sacri?ce performance When the critical temperature
`threshold is crossed.
`
`SUMMARY
`
`Accordingly, the invention provides a system in Which the
`maXimum performance state, Which is typically based on
`such factors as operating frequency and voltage, changes
`according to thermal criteria. The thermal criteria may be,
`for example, a die temperature of the microprocessor. Once
`the temperature crosses above a predetermined temperature
`threshold, the maXimum performance state available to the
`system is changed to a loWer performance state. As the
`temperature crossed above successive temperature
`thresholds, successively loWer maXimum performance states
`become available to the system. That alloWs processor
`performance to be impacted less than the throttling alterna
`tive described above as the temperature increases. When the
`temperature crosses beloW a predetermined temperature
`threshold, a higher maXimum performance state is again
`available to the system. Hysteresis may be implemented to
`ensure the system does not rapidly sWitch betWeen perfor
`mance states When the temperature is close to predetermined
`thresholds.
`In an embodiment, the invention provides a processor that
`has multiple performance states determined by such factors
`as operating frequency and/or voltage. In a ?rst temperature
`range, the processor operates With a ?rst maXimum perfor
`mance state and in a second temperature range, higher than
`the ?rst temperature range, the processor operates With a
`loWer maXimum performance state.
`In another embodiment the invention provides a method
`of operating a computing system that includes determining
`a temperature associated With an integrated circuit and
`operating the integrated circuit With a ?rst performance state
`as a maXimum performance state according to the deter
`mined temperature, the ?rst performance state being one of
`a plurality of performance states available at the determined
`temperature.
`In another embodiment a method for providing a variable
`maXimum die temperature for an integrated circuit in a
`computer system having a plurality of different maXimum
`performance states, comprising increasing the maXimum
`alloWable die temperature as a maXimum alloWable perfor
`mance state is decreased.
`
`10
`
`15
`
`25
`
`35
`
`40
`
`45
`
`55
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The present invention may be better understood, and its
`numerous objects, features, and advantages made apparent
`to those skilled in the art by referencing the accompanying
`draWings in Which the use of the same reference symbols in
`different draWings indicates similar or identical items.
`FIG. 1 is a high level How diagram of poWer management
`operations based on CPU utiliZation.
`FIG. 2 illustrates sWitching betWeen performance states
`according to utiliZation.
`FIG. 3 illustrates an exemplary processing system that can
`change performance state.
`
`65
`
`LG Ex. 1001, pg 7
`
`

`
`US 6,889,332 B2
`
`3
`FIG. 4 illustrates a table including various temperature
`trip points for an exemplary system.
`FIG. 5 shoWs the high level How of an embodiment of the
`invention in Which the maximum performance state avail
`able is adjusted according to temperature measurements.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`A computer system according to one embodiment of the
`invention has a plurality of processor performance states, the
`processor performance states being generally determined by
`unique voltage/frequency combinations. The computing sys
`tem provides loWer maximum performance states as the
`detected temperature of, eg the processor die, increases. In
`addition to having a different maximum performance state
`associated With particular temperature ranges, the computer
`system may change to a different performance states based
`on such factors as processor utiliZation as explained more
`fully herein. The detected temperatures may be related
`directly to the processor by measuring the die temperature
`directly using a sensor on the die or may measure the die
`temperature indirectly using a sensor that is off-die. In
`addition, other indirect measurements may be taken such as
`ambient temperatures or measurements of the temperature of
`other computer system components to determine the appro
`priate mode of operation although indirect measurements
`may reduce accuracy. Because the different temperature
`ranges have different maximum performance states, the
`maximum amount of poWer that can be consumed groWs
`less as the temperature increases through the various tem
`perature ranges and loWer maximum performance states are
`provided.
`While a performance state is commonly based in operat
`ing voltage and frequency, other criteria can also be used.
`For example, in some embodiments, processor performance
`states could be determined by an amount of chip area that
`Was enabled for processing. Thus, portions of the processor
`may be selectively disabled to control the amount of poWer
`consumed. For example, the number of execution units that
`are enabled may vary.
`In order to more fully appreciate the invention, the use of
`performance states is described in Which a poWer manage
`ment control function in the computer system periodically
`determines the utiliZation level of the processor, i.e., hoW
`much of the available processor resources are being utiliZed,
`and selects a performance state that is appropriate for the
`utiliZation level. Referring to FIG. 1, a flow diagram illus
`trates at a high level, operation of an embodiment of a poWer
`management function utiliZed to provide the requisite poWer
`management control. The current CPU utiliZation is peri
`odically determined in 101. That current utiliZation is then
`compared to a high threshold level, e.g., 80% of processing
`resources, in 103. If the utiliZation level is above the high
`threshold level, indicating that processor resources are being
`utiliZed at a level above 80%, the poWer management
`control function increases the performance state of the
`processor in 105. In one embodiment, that can be accom
`plished by selecting a voltage/frequency pair that provides
`greater performance and then causing the processor to
`operate at the neW voltage and frequency, as described
`further herein.
`If the current utiliZation is beloW the high threshold, then
`the current utiliZation is compared to the loW threshold in
`107. An exemplary loW threshold level is 55%. If the current
`utiliZation is beloW that loW threshold, the poWer manage
`ment control function decreases the performance state of the
`
`15
`
`35
`
`40
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`45
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`55
`
`65
`
`4
`processor in 109. As described further herein, that may be
`accomplished by selecting, e.g., a voltage/frequency pair
`providing loWer performance and then causing the perfor
`mance change to occur. The poWer management control
`function then returns to 101 to periodically determine the
`utiliZation level and again compare the current utiliZation
`level to the high and loW threshold levels. In that Way the
`poWer management can tailor the performance state of the
`processor to the actual requirements.
`In a computer system With several possible processing
`performance states, if the management control function
`determines that more performance is necessary to meet
`performance requirements, one approach to providing
`increased performance is to increase the performance one
`step at a time until the current utiliZation is beloW the high
`threshold level. HoWever, in another approach rather than
`increasing the performance state one step at a time, the
`poWer management control function selects the highest
`performance state regardless of the current performance
`state. The reasons for alWays selecting the highest possible
`performance state When a higher performance state is
`needed are as folloWs. In computer systems, performance
`demands are often of a bursty nature. When a higher
`performance state is required based on the current utiliZation
`level, stepping the performance state to a next higher level
`can result in degradation of performance that can be per
`ceived by the user. That is especially true When the task that
`needs the increased performance requires a near real-time
`response, for instance, While decoding an audio or video ?le.
`FIG. 2 illustrates that concept. Assume the processor has
`?ve performance states P0—P4, With P0 being the highest
`and P4 the loWest. Whenever the poWer management deter
`mines that a higher performance state is required When
`operating at any of the levels P1—P4, the poWer management
`selects the maximum performance state P0 as the next
`performance state. Thus, in one embodiment, if the perfor
`mance state is alWays taken straight to the maximum per
`formance state When a performance increase is required,
`rather than stepping up to the maximum performance state,
`there is less of a chance that a user could notice any
`performance degradation. In effect, the poWer management
`control function anticipates a peak loading by assuming that
`any indication of a required increase in performance is
`assumed to be a burst requiring peak performance.
`HoWever, if a loWer performance state is required, a next
`loWer performance state is selected. Thus, if at performance
`state P0, P1 is selected as the next loWer performance state.
`If the current performance state is P1, the next loWer
`performance state selected is P2 When a performance
`decrease is effectuated by the poWer management control
`function. In that Way, if the performance is still too high,
`successively loWer performance states can be selected and
`the chance than any degradation is detected by a system user
`is reduced. Thus, if the utiliZation information indicates that
`an increase in performance is necessary, the poWer manage
`ment control function selects the maximum (or near
`maximum) performance state, While a decrease in perfor
`mance causes the poWer management control function to
`step to the next loWest performance state.
`If the processor utiliZation is kept Within the range of the
`high and loW thresholds, then a user should experience a
`crisp, high performance system, While still getting the ben
`e?t of poWer savings for those applications or those portions
`of applications requiring less performance. That approach
`reduces poWer consumption, extends battery life, reduces
`temperature resulting in less need for cooling and thus less
`fan noise, While still maintaining high performance and thus
`
`LG Ex. 1001, pg 8
`
`

`
`US 6,889,332 B2
`
`5
`maintaining a perception of fast response to the user. Note
`that running at a loWer average CPU die temperature
`increases CPU reliability, and that a loWer CPU temperature
`results in a loWer system temperature, Which increases
`system reliability.
`In order to effect changes to the performance state, the
`poWer management softWare has to cause the voltage and
`frequency used by the CPU to change. In one embodiment
`that can be accomplished as folloWs. Referring to FIG. 3, a
`processor is shoWn that can dynamically adjust its frequency
`and/or operating voltage to provide better thermal and poWer
`management in accordance With processor utiliZation. Pro
`cessor 301 includes a programmable voltage control ?eld
`303, core clock frequency control ?eld 304 and count ?eld
`305. Those ?elds may be located in one or more program
`mable registers. When the processor and/or system deter
`mines that a change to the operating voltage and/or fre
`quency is desired to increase or decrease the performance
`state, the desired frequency and voltage control information
`are loaded into frequency control ?eld 304 and voltage
`control ?eld 303, respectively. Access to a register contain
`ing those ?elds, or an access to another register location, or
`access to a particular ?eld in one of those registers can be
`used as a trigger to initiate the protocol for a performance
`state change. The protocol, Which Will vary according to
`processor design, ensures that the processor enters a quies
`cent state that is suitable for performance state transitions.
`In some protocols, that Will ensure that the portion of the
`processor, referred to for convenience herein as the CPU
`core logic 311 becomes quiescent, including any external
`bus interfaces 310 and interfaces With internal logic that may
`not be affected by the performance state change. Note that in
`one implementation bus interface 310 is implemented sepa
`rately from CPU core logic 311 and functions to hold off
`traf?c to CPU core logic 311 during performance state
`transitions. Various messages may be sent or signals pro
`vided indicating that the processor has or is about to enter
`the quiescent state. In addition various control and/or status
`signals 309 and 313 may be provided to and from core logic
`311. Note that in some processor implementations, various
`poWer planes and clock grids may ensure some parts of the
`processor are unaffected by the processor core logic 311
`entering the quiescent state. Further, the quiescent state may
`vary according to processor design. For example, for one
`processor the quiescent state may have the clocks turned off
`and in other processors, the clocks may be reduced to an
`extent to alloW appropriate voltage changes. Note also that
`the poWer state changes may include clock frequency
`changes, voltage changes or both. In X86 architectures, such
`a quiescent state has been referred to as the “stop grant” state
`in Which execution of operating system and application code
`is stopped. As Would be knoWn to those of skill in the art,
`other Ways may be used to initiate the protocol necessary to
`enter the quiescent state suitable for performance state
`changes. For example, initiation of the protocol to enter the
`quiescent state may be indicated by Writing a command over
`a communication link coupling the processor to another
`device.
`Once in the quiescent state, the processor can transition
`the voltage and frequency to the neW states speci?ed in
`voltage control ?eld 303 and clock frequency control ?eld
`304. As described above, in some processor
`implementations, the processor core clocks are stopped after
`the processor enters the quiescent state to suitable for
`changing performance states. In other processor
`implementations, the processor core clock frequency is
`reduced to a frequency Which can safely tolerate desired
`
`10
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`15
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`25
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`6
`voltage changes. In one implementation clock control fre
`quency information is supplied as multiplier values for a
`clock that is supplied to processor 301. Those of skill in the
`art appreciate that many other approaches can be used to
`specify the core operating frequency. In either case, the
`voltage control information speci?ed in voltage control ?eld
`303 is supplied to voltage regulator 315 Which in turn
`supplies CPU core logic 311 With the neW voltage during the
`quiescent state. As Will be appreciated by those of skill in the
`art, there are many alternatives to supplying the voltage
`information to an external voltage regulator from a register
`in the processor. For example, the voltage information may
`be supplied from a device outside the processor, or may be
`supplied by a communication link With a voltage regulator
`circuit.
`Because changing the voltage and frequency can not be
`done instantaneously, the quiescent state is typically main
`tained for a period of time to alloW the neW voltage and
`clock frequency to stabiliZe. That time period may be
`speci?ed in count ?eld 305 and counted using a counter in
`the processor or in another location in the computer system.
`Once the count is complete, the protocol is initiated to exit
`the quiescent state and resume executing operating system
`and application code, including restarting any buses that
`have been “turned off” by the processor as part of entering
`the quiescent state.
`Note that changing both voltage and frequency to enter a
`neW performance state can be particularly effective.
`Changes in the processor’s core clock frequency have an
`approximately linear affect on the poWer dissipated by the
`processor. Thus, a 20% reduction in clock frequency reduces
`the poWer dissipated by the processor by 20%. The range of
`change is signi?cant since a ratio of highest frequency to
`loWest frequency is usually greater than 2:1. Consequently,
`the processor’s poWer may be changed by similar ratio.
`Changes in the processor’s core voltage have an approxi
`mately square laW effect. That is, potential poWer savings is
`proportional to the square of the voltage reduction. The
`square laW effect results in signi?cant changes in the pro
`cessor’s poWer if the core voltage of the processor is
`reduced.
`In addition to modifying processor frequency and/or
`voltage and to match processor utiliZation, computer sys
`tems also monitor temperature and take active or passive
`poWer management actions to ensure that the temperature of
`the processor die stays Within operational levels using poWer
`management control softWare such as that associated With
`the Advanced Con?guration and PoWer Interface (ACPI)
`Speci?cation. For example, at certain temperatures, the
`computing system may take actions that take active poWer
`management action such as turning on a fan, or increasing
`fan speed. At other temperatures, a computer system may
`take passive actions such as throttling the processor
`(reducing its effective frequency by stopping or sloWing
`clocks With a predetermined duty cycle and period appro
`priate for the processor). At another temperature threshold,
`the processor may shut doWn the computer system to
`prevent potential damage. FIG. 4 illustrates an exemplary set
`of temperature “trip points” at Which poWer management
`activities take place. As shoWn in FIG. 4, there are “active”
`trip points at Which various actions are performed such as
`adjusting fan speed. The types of actions described in FIG.
`4 are in addition to the utiliZation based poWer management
`described previously. The actual temperatures, the number
`of trip points, and the speci?c actions taken Will of course
`vary according to the particulars of the computer system.
`Note that the poWer management control described herein
`may be implemented as part of the operating system (OS),
`
`LG Ex. 1001, pg 9
`
`

`
`US 6,889,332 B2
`
`7
`in Whole or in part. In addition, separate power management
`applications may incorporate some or all of the capability
`described herein. In other computer systems, the various
`poWer management tasks may be shared betWeen the oper
`ating system, softWare applications running under the oper
`ating system and BIOS routines. In addition, the poWer
`management techniques may be implemented in hardWare.
`NoW that the process of changing processor states has
`been described, and the utiliZation of trip points in poWer
`management has been described, the utiliZation of different
`maXimum performance states based on temperature Will be
`described. Assume that a processor system has ?ve perfor
`mance states P0—P4, With P0 being the highest performance
`state. The highest performance state is that state having the
`highest clock frequency (and in some embodiments the
`highest voltage) and having the highest poWer consumption.
`Referring again to FIG. 4, the performance states available
`are shoWn to be based on temperature range.
`In the eXample shoWn in the last column of the table in
`FIG. 4, When the die temperature is beloW 70 C, all the
`performance states are available (P0—P4) and the maXimum
`performance state available, e.g., for utiliZation based (or
`other) poWer management activities, is the maXimum per
`formance state that the system provides, namely P0. When
`the temperature is betWeen 70 C and 80 C, the performance
`states available are P1—P4 With the maXimum available
`performance state being P1. Finally, When the temperature
`crosses above 80 C the available performance states are
`further reduced, With the maXimum available performance
`state being P2. Thus, the embodiment represented in FIG. 4,
`both the number of performance states and the maXimum
`performance state changes based on temperature trip points
`of 70 C and 80 C.
`When the temperature falls back into a temperature range,
`e.g., <70 C, the higher maXimum performance state once
`again becomes available. HoWever, in one embodiment a
`temperature trip point that causes the system to make a
`higher maXimum performance state available differs from
`the temperature trip point that causes a loWer maXimum
`performance state to be available. That provides hysteresis
`and avoids frequent changes in the available maXimum
`performance state if the temperature is at or near a trip point.
`In the eXample shoWn in FIG. 4, hysteresis is imple
`mented by causing P0 to become unavailable as the maXi
`mum performance state at 70 C but to again become
`available at a temperature trip point of 68 C. Thus, if the
`system is operating With P1 as the maXimum performance
`state and a temperature of 68 C is detected, P0 becomes the
`maXimum performance state. Similarly, P1 becomes
`unavailable as the maXimum performance state at 80 C but
`again become available as the maXimum performance state
`When the temperature crosses back beloW 78 C. Note that in
`various implementations, the system may detect Whether the
`temperature is greater than, greater than or equal to, equal to,
`less than or less than or equal to a particular temperature, as
`appropriate for the particular situation, to determine if the
`system has crossed a temperature trip point.
`Note that the available performance states may be imple
`mented as a table or other data structure in BIOS, in
`application softWare, or in a poWer management portion of
`the operating system softWare. Other Ways to encode the
`appropriate performance states according to the temperature
`Would be readily apparent to those of skill in the art.
`The How chart in FIG. 5 provides a high level illustration
`of the operation of an embodiment of the invention. For ease
`of understanding, FIG. 5 deals With maXimum performance
`
`10
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`15
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`25
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`40
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`45
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`state transitions and does not illustrate operations of all
`poWer management functions. The How chart corresponds to
`an embodiment of the invention that utiliZes three tempera
`ture ranges illustrated in FIG. 4. In 500, a temperature
`associated With the microprocessor, e.g., a die temperature
`of the microprocessor, is supplied or obtained. The system
`checks to see if it is operating With the maXimum perfor
`mance state being P0 in 503. If so, the system checks to