
`
`UC2842/3/4/5
`UC3842/3/4/5
`
`CURRENT MODE PWM CONTROLLER
`
`. OPTIMIZED FOR OFF-LINE AND DC TO DC
`. LOW START-UP CURRENT (< 1 mA)
`. AUTOMATIC FEED FORWARD COMPENSA-
`TION. PULSE-BY-PULSE CURRENT LIMITING
`. ENHANCED LOAD RESPONSE CHARAC-
`. UNDER-VOLTAGE LOCKOUT WITH HYSTER-
`ESIS. DOUBLE PULSE SUPPRESSION
`. HIGH CURRENT TOTEM POLE OUTPUT
`. INTERNALLY TRIMMED BANDGAP REFER-
`. 500 KHz OPERATION
`. LOW RO ERROR AMP
`
`CONVERTERS
`
`TERISTICS
`
`ENCE
`
`Minidip
`
`SO14
`
`logic to insure latched operation, a PWM compara-
`torwhich also providescurrentlimit control,anda to-
`tem pole output stage designed to source or sink
`high peak current. The output stage, suitable for
`driving N-Channel MOSFETs, is low in theoff-state.
`Differences between members of this family are the
`under-voltage lockout thresholds and maximum
`duty cycle ranges. The UC3842 and UC3844 have
`UVLO thresholds of 16V (on) and 10V (off), ideally
`suited off-line applications The corresponding
`thresholds for the UC3843 and UC3845 are 8.5 V
`and 7.9 V. The UC3842 and UC3843 can operate
`to duty cycles approaching 100%. A range of the
`zero to < 50 % is obtained by the UC3844 and
`UC3845 by the additionof an internal toggle flip flop
`which blanks the output off every other clock cycle.
`
`DESCRIPTION
`TheUC3842/3/4/5family of controlICs providesthe
`necessary features to implement off-line or DC to
`DC fixed frequency current mode control schemes
`witha minimalexternalparts count.Internallyimple-
`mentedcircuitsinclude undervoltagelockoutfeatur-
`ing start-up current less than 1 mA, a precision ref-
`erence trimmed for accuracy at the error amp input,
`
`BLOCK DIAGRAM (toggle flip flop used only in U3844 and UC3845)
`
`October 1998
`
`1/11
`
`RIGID-1003 page 1
`
`

`

`UC2842/3/4/5-UC3842/3/4/5
`
`ABSOLUTE MAXIMUM RATINGS
`
`Symbol
`Vi
`Vi
`IO
`EO
`
`Ptot
`Ptot
`Tstg
`TL
`
`Parameter
`Supply Voltage (low impedance source)
`Supply Voltage (Ii < 30mA)
`Output Current
`Output Energy (capacitive load)
`Analog Inputs (pins 2, 3)
`Error Amplifier Output Sink Current
`Power Dissipation at Tamb ≤ 50 °C (minidip, DIP-14)
`Power Dissipation at Tamb ≤ 25 °C (SO14)
`Storage Temperature Range
`Lead Temperature (soldering 10s)
`
`* All voltages are with respect to pin 5, all currents are positive into the specified terminal.
`
`PIN CONNECTIONS (top views)
`
`Value
`30
`Self Limiting
`±1
`5
`– 0.3 to 6.3
`10
`1
`725
`– 65 to 150
`300
`
`Unit
`V
`
`A
`m J
`V
`mA
`W
`mW
`°C
`°C
`
`SO14
`
`Minidip
`
`ORDERING NUMBERS
`
`Type
`
`UC2842
`UC3843
`UC2844
`UC2845
`UC3842
`UC3843
`UC3844
`UC3845
`
`THERMAL DATA
`
`Minidip
`
`UC2842N
`UC2843N
`UC2844N
`UC2845N
`UC3842N
`UC3843N
`UC3844N
`UC3845N
`
`SO14
`
`UC2842D
`UC2843D
`UC2844D
`UC2845D
`UC3842D
`UC3843D
`UC3844D
`UC3845D
`
`Symbol
`Rth j-amb
`
`Description
`Thermal Resistance Junction-ambient.
`
`Minidip
`100
`
`max.
`
`SO14
`165
`
`Unit
`°C
`
`2/11
`
`RIGID-1003 page 2
`
`

`

`ELECTRICAL CHARACTERISTICS (Unless otherwise stated, these specifications apply for -25 < Tamb <
`85°C for UC2824X; 0 < Tamb < 70°C for UC384X; Vi = 15V (note 5); RT = 10K; CT = 3.3nF)
`
`Symbol
`
`Parameter
`
`Test Conditions
`
`UC384X
`UC284X
`Min. Typ. Max. Min. Typ. Max.
`
`Unit
`
`UC2842/3/4/5-UC3842/3/4/5
`
`4.95 5.00 5.05 4.90 5.00 5.10
`
`20
`
`25
`
`0.4
`
`5.1
`
`6
`
`6
`
`0.2
`
`50
`
`6
`
`6
`
`0.2
`
`50
`
`4.82
`
`V
`
`mV
`
`20
`
`mV
`25
`0.4 mV/°C
`5.18
`V
`m V
`
`REFERENCE SECTION
`Tj = 25°C Io = 1mA
`12V ≤ Vi ≤ 25V
`1 ≤ Io ≤ 20mA
`(Note 2)
`
`4.9
`
`Line, Load, Temperature (2)
`10Hz ≤ f ≤ 10KHz Tj = 25°C
`(2)
`Tamb = 125°C, 1000Hrs (2)
`
`VREF
`D VREF
`D VREF
`D VREF/D T
`
`eN
`
`ISC
`
`fs
`
`V4
`
`Output Voltage
`
`Line Regulation
`
`Load Regulation
`
`Temperature Stability
`
`Total Output Variant
`Output Noise Voltage
`
`Long Term Stability
`
`Output Short Circuit
`
`Initial Accuracy
`
`Voltage Stability
`Temperature Stability
`
`Amplitude
`
`5
`
`25
`
`5
`
`25
`
`mV
`
`-30
`
`-100 -180
`
`-30
`
`-100 -180 mA
`
`47
`
`57
`
`1
`
`47
`
`52
`
`0.2
`5
`
`1.7
`
`52
`
`0.2
`5
`
`1.7
`
`57
`
`1
`
`KHz
`
`%
`%
`
`V
`
`OSCILLATOR SECTION
`Tj = 25°C (6)
`12 ≤ Vi ≤ 25V
`TMIN ≤ Tamb ≤ TMAX (2)
`VPIN4 Peak to Peak
`ERROR AMP SECTION
`VPIN1 = 2.5V
`
`V2
`Ib
`
`B
`SVR
`Io
`Io
`
`GV
`V3
`SVR
`Ib
`
`IOL
`
`IOH
`
`tr
`tf
`
`Input Voltage
`Input Bias Current
`AVOL
`Unity Gain Bandwidth
`Supply Voltage Rejection
`
`Output Sink Current
`Output Source Current
`VOUT High
`
`VOUT Low
`
`Gain
`Maximum Input Signal
`Supply Voltage Rejection
`
`Input Bias Current
`
`Delay to Output
`
`Output Low Level
`
`Output High Level
`
`Rise Time
`
`Fall Time
`
`2
`-0.5
`5
`
`65
`
`0.7
`60
`
`2 ≤ Vo ≤ 4V
`(2)
`12V ≤ Vi ≤ 25V
`VPIN2 = 2.7V VPIN1 = 1.1V
`VPIN2 = 2.3V VPIN1 = 5V
`VPIN2 = 2.3V;
`RL = 15KW
`to Ground
`VPIN2 = 2.7V;
`RL = 15KW
`to Pin 8
`CURRENT SENSE SECTION
`(3 & 4)
`2.85
`VPIN1 = 5V (3)
`0.9
`12 ≤ Vi ≤ 25V (3)
`
`OUTPUT SECTION
`ISINK = 20mA
`ISINK = 200mA
`ISOURCE = 20mA
`ISOURCE = 200mA
`Tj = 25°C CL = 1nF (2)
`Tj = 25°C CL = 1nF (2)
`
`13
`12
`
`2.45 2.50 2.55 2.42 2.50 2.58
`-0.3
`-1
`-0.3
`-2
`
`90
`
`1
`70
`
`6
`-0.8
`6
`
`65
`
`0.7
`60
`
`2
`-0.5
`5
`
`90
`
`1
`70
`
`6
`-0.8
`6
`
`V
`m A
`dB
`
`MHz
`dB
`
`V
`mA
`V
`
`0.7
`
`1.1
`
`0.7
`
`1.1
`
`V
`
`3
`1
`70
`
`-2
`
`150
`
`0.1
`1.5
`13.5
`13.5
`50
`
`50
`
`3.15
`1.1
`
`2.8
`0.9
`
`-10
`
`300
`
`0.4
`2.2
`
`150
`
`150
`
`13
`12
`
`3
`1
`70
`
`-2
`
`150
`
`0.1
`1.5
`13.5
`13.5
`50
`
`50
`
`3.2
`1.1
`
`-10
`
`300
`
`0.4
`2.2
`
`150
`
`150
`
`V/V
`V
`dB
`m A
`ns
`
`V
`V
`V
`V
`ns
`
`ns
`
`3/11
`
`RIGID-1003 page 3
`
`

`

`UC2842/3/4/5-UC3842/3/4/5
`
`ELECTRICAL CHARACTERISTICS (continued)
`
`Symbol
`
`Parameter
`
`Test Conditions
`
`UC384X
`UC284X
`Min. Typ. Max. Min. Typ. Max.
`UNDER-VOLTAGE LOCKOUT SECTION
`
`Unit
`
`Start Threshold
`
`Min Operating Voltage
`After Turn-on
`
`Maximum Duty Cycle
`
`Minimum Duty Cycle
`
`X842/4
`X843/5
`X842/4
`X843/5
`PWM SECTION
`
`X842/3
`X844/5
`
`15
`7.8
`9
`7.0
`
`93
`46
`
`TOTAL STANDBY CURRENT
`
`Ist
`Ii
`Viz
`
`Start-up Current
`Operating Supply Current
`
`Zener Voltage
`
`VPIN2 = VPIN3 = 0V
`Ii = 25mA
`
`Notes : 2. These parameters, although guaranteed, are not 100% tested in production.
`3. Parameter measured at trip point of latch with VPIN2 = 0.
`4. Gain defined as :
`D VPIN1
`; 0 ≤ VPIN3 ≤ 0.8 V
`D VPIN3
`5. Adjust Vi above the start threshold before setting at 15 V.
`6. Output frequency equals oscillator frequency for the UC3842 and UC3843.
`Output frequency is one half oscillator frequency for the UC3844 and UC3845.
`
`A =
`
`14.5
`7.8
`8.5
`7.0
`
`93
`47
`
`17
`9.0
`11
`8.2
`
`100
`50
`0
`
`1
`20
`
`16
`8.4
`10
`7.6
`
`97
`48
`
`0.5
`11
`
`34
`
`17.5
`9
`11.5
`8.2
`
`100
`50
`0
`
`1
`20
`
`16
`8.4
`10
`7.6
`
`97
`48
`
`0.5
`11
`
`34
`
`V
`V
`V
`V
`
`%
`%
`%
`
`mA
`mA
`
`V
`
`4/11
`
`RIGID-1003 page 4
`
`

`

`Figure 1 : Error Amp Configuration.
`
`UC2842/3/4/5-UC3842/3/4/5
`
`Error amp can source or
`sink up to 0.5mA
`
`Figure 2 : UnderVoltage Lockout.
`
`During Under-Voltage Lockout, the output driver is
`biased to sink minor amounts of current. Pin 6
`should be shunted to groundwith a bleederresistor
`
`Figure 3 : Current Sense Circuit .
`
`to preventactivating the power switch with extrane-
`ous leakage currents.
`
`Peak current (is) is determined by the formula
`1.0 V
`IS max ≈
`RS
`A small RC filter may be required to suppress switch transients.
`
`5/11
`
`RIGID-1003 page 5
`
`

`

`UC2842/3/4/5-UC3842/3/4/5
`
`Figure 4.
`
`Figure 5 : Deadtime vs. CT (RT > 5KW
`
`).
`
`for RT > 5KW
`
`f =
`
`1.72
`RTCT
`
`Figure 6 : Timing Resistance vs. Frequency.
`
`Figure 7 : Output Saturation Characteristics.
`
`Figure 8 : Error Amplifier Open-loop Frequency
`Response.
`
`6/11
`
`RIGID-1003 page 6
`
`

`

`Figure 9 : Open Loop Test Circuit.
`
`UC2842/3/4/5-UC3842/3/4/5
`
`High peak currentsassociatedwith capacitive loads
`necessitate careful grounding techniques. Timing
`and bypass capacitors should be connected close
`
`to pin 5 in a single point ground. The transistor and
`5 KW potentiometerareusedto sampletheoscillator
`waveform and apply an adjustableramp to pin 3.
`
`Figure 10 : Shutdown Techniques.
`
`Shutdownof the UC2842 can be accomplished by
`two methods; eitherraise pin 3 above1V or pull pin
`1 below a voltage two diode drops above ground.
`Either method cause the output of the PWM com-
`parator to be high (refer to block diagram). The
`PWM latch is reset dominant so that the output will
`remain low until the next clock cycle after the shut-
`
`down conditionat pins 1 and/or3 is removed. In one
`example, an externally latched shutdown may be
`accomplishedby addingan SCR which will be reset
`by cyclingVi belowthelowerUVLOthreshold.At this
`pointthe referenceturnsoff, allowing the SCR to re-
`set.
`
`7/11
`
`RIGID-1003 page 7
`
`

`

`UC2842/3/4/5-UC3842/3/4/5
`
`Figure 11 : Off-line Flyback Regulator.
`
`Power Supply Specifications
`1. Input Voltage :
`95 VAC to 130 VAC
`(50 Hz/60 Hz)
`3750 V
`2. Line Isolation :
`40 KHz
`3. Switching Frequency :
`4. Efficiency @ Full Load : 70 %
`
`Figure 12 : Slope Compensation.
`
`5. OutputVoltage :
`A. + 5 V, ± 5 % : 1 A to 4 A load
`Ripple voltage : 50 mV P-P Max.
`B. + 12 V, ± 3 % : 0.1 A to 0.3 A load
`Ripple voltage : 100 mV P-P Max.
`C. – 12 V, ± 3 % : 0.1 A to 0.3 A load
`Ripple voltage : 100 mV P-P Max.
`
`A fraction of the oscillator ramp can be resistively
`summed with the current sense signal to provide
`slope compensation for converters requiring duty
`cycles over 50 %.
`
`Note that capacitor, C, forms a filter with R2 to su-
`press the leading edge switch spikes.
`
`8/11
`
`RIGID-1003 page 8
`
`

`

`DIM.
`
`inch
`mm
`TYP. MAX.. MIN.. TYP.. MAX..
`
`MIN..
`
`0.1
`
`0.35
`
`0.19
`
`A
`
`a1
`
`a2
`
`b
`
`b1
`
`C
`
`c1
`
`D (1)
`
`8.55
`
`5.8
`
`3.8
`
`4.6
`
`0.4
`
`E
`
`e
`
`e3
`
`F (1)
`
`G
`
`L
`
`M
`S
`
`1.75
`
`0.25
`
`1.6
`
`0.46
`
`0.25
`
`0.004
`
`0.014
`
`0.007
`
`0.5
`
`0.020
`
`1.27
`
`7.62
`
`0.050
`
`0.300
`
`45° (typ.)
`8.75
`0.336
`
`6.2
`
`0.228
`
`4
`
`5.3
`
`0.150
`
`0.181
`
`1.27
`
`0.016
`
`0.68
`8°
`(max.)
`
`0.069
`
`0.009
`
`0.063
`
`0.018
`
`0.010
`
`0.344
`
`0.244
`
`0.157
`
`0.209
`
`0.050
`
`0.027
`
`(1) D and F do not include mold flash or protrusions. Mold flash or
`potrusions shall not exceed 0.15mm (.006inch).
`
`UC2842/3/4/5-UC3842/3/4/5
`
`OUTLINE AND
`MECHANICAL DATA
`
`SO14
`
`9/11
`
`RIGID-1003 page 9
`
`

`

`UC2842/3/4/5-UC3842/3/4/5
`
`DIM.
`
`mm
`
`inch
`
`MIN.
`
`TYP. MAX. MIN.
`
`TYP. MAX.
`
`OUTLINE AND
`MECHANICAL DATA
`
`0.7
`
`1.39
`
`0.91
`
`0.38
`
`3.3
`
`0.5
`
`8.8
`
`2.54
`
`7.62
`
`7.62
`
`0.028
`
`1.65
`
`0.055
`
`1.04
`
`0.036
`
`0.015
`
`0.5
`
`9.8
`
`7.1
`
`4.8
`
`0.130
`
`0.020
`
`0.346
`
`0.100
`
`0.300
`
`0.300
`
`0.065
`
`0.041
`
`0.020
`
`0.386
`
`0.280
`
`0.189
`
`3.3
`
`0.130
`
`0.44
`
`1.6
`
`0.017
`
`0.063
`
`Minidip 0.300”
`
`A
`
`a1
`
`B
`
`B1
`
`b
`
`b1
`
`D
`
`E
`
`e
`
`e3
`
`e4
`
`F
`
`I
`
`L
`
`Z
`
`10/11
`
`RIGID-1003 page 10
`
`

`

`UC2842/3/4/5-UC3842/3/4/5
`
`Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the conse-
`quences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
`license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this
`publication are subject to change without notice. This publication supersedes and replaces all
`information previously supplied. STMi-
`croelectronics products are not authorized for use as critical components in life support devices or systems without express written
`approval of STMicroelectronics.
`
`The ST logo is a registered trademark of STMicroelectronics
` 1998 STMicroelectronics – Printed in Italy – All Rights Reserved
`STMicroelectronics GROUP OF COMPANIES
`Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands -
`Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
`http://www.st.com
`
`11/11
`
`RIGID-1003 page 11
`
`

`

`This datasheet has been downloaded from:
`
`www.DatasheetCatalog.com
`
`Datasheets for electronic components.
`
`RIGID-1003 page 12
`
`