United States Patent [191
`Sachs et al.
`
`[11] Patent Number:
`[45] Date of Patent:
`
`4,933,835
`Jun. 12, 1990
`
`[54] APPARATUS FOR MAINTAINING
`CONSISTENCY OF A CACHE MEMORY
`WITH A PRIMARY MEMORY
`Howard G. Sachs, Los Altos; James
`[75] Inventors:
`Y. Cho, Los Gatos; Walter H.
`Hollingsworth, Campbell, all of Calif.
`Intergraph Corporation, Huntsville,
`Ala.
`[21] Appl. No.: 300,174
`[22] Filed:
`Jan. 19, 1989
`
`[73] Assignee:
`
`[63]
`
`Related US. Application Data
`Continuation of Ser. No. 915.272, Oct. 3, 1986, aban
`doned, Continuation-impart of Ser. No. 704,568, Feb.
`22, 1985, abandoned.
`
`[51] Int. (31.5 .............................................. .. G06F 9/00
`[52] US. Cl. ............................... .. 364/200; 364/243.4;
`364/243.4l; 364/243.42; 364/243.43
`[58] Field of Search .............................. .. 364/200, 100
`[56]
`References Cited
`U.S. PATENT DOCUMENTS
`364/200
`3,693,765 9/1972 Reiley et al.
`364/200
`3,723,976 3/1973 Alvarez et al.
`364/200
`3,761,881 9/1973 Anderson et a1.
`364/200
`3,764,996 10/1973 Ross ............ ..
`364/200
`3,896,419 7/1975 Lange et a1.
`364/200
`3,898,624 8/1975 Tobias ......... ..
`364/200
`3,902,164 8/1975 Kelley et al.
`364/200
`3,956,737 5/1976 Ball .............. ..
`364/200
`4,037,209 7/1977 Nakajima et al. .
`364/200
`4,057,848 11/1977 Hayashi ....... ..
`364/200
`4,068,303 1/1978 Morita ..... ..
`364/200
`4,077,059 2/1978 Corcli et a1.
`364/200
`4.144.563 3/1979 l-leuer et a1.
`4,151,593 4/1979 Jenkins et al. .................... .. 364/200
`(List continued on next page.)
`
`FOREIGN PATENT DOCUMENTS
`58-58666 4/1983 Japan
`364/200
`60-41146 3/1985 Japan .
`60-120450 6/1985 Japan .
`60-144847 7/1985 Japan .
`1444228 7/1976 United Kingdom
`
`364/200
`
`OTHER PUBLICATIONS
`Losq, et al., “Conditional Cache Miss Facility for Han
`dling Short/Long Cache Requests", IBM TDB, vol. 25,
`No. 1, Jun. ‘82, pp. 110-111.
`MC68120/MC6812l-Intelligent Peripheral Controller
`Users Manual, Motorola, Inc.
`Electronics International, vol. 55, No. 16, Aug. 1982,
`pp. 112-117, N.Y., 115; P. Knudsen: "Supermini Goes
`Multiprocessor Route to Put it up Front in Perfor
`mance".
`Primary Examiner-Raulfe B. Zache
`Assistant Examiner-John G. Mills
`Attorney, Agent, or Firm—Townsend and Townsend
`[57]
`ABSTRACT
`A microprocessor system is disclosed having a high
`speed system bus for coupling system elements, and
`having a dual bus microprocessor with separate ultra
`high speed instruction and data cache-MMU interfaces
`coupled to independently operable instruction and data
`cache-MMU, respectively. A main memory is coupled
`to the system bus for selectively storing and outputting
`digital information. The instruction and data cache
`MMU‘s are coupled to the main memory via the system
`bus for independently storing and outputting digital
`information to respective mapped addressable very
`high speed cache memory. The microprocessor is cou
`pled via separate and independent very high speed in
`struction and data buses to each of the instruction
`cache-MMU and data cache-MMU, respectively, for
`processing data received from the data cache-MMU
`responsive to instructions received from the instruction
`cache-MMU. The instruction bus and data bus are ex
`clusive and independent of one another, and allow for
`simultaneous very high-speed transfer. The data cache
`MMU and instruction cache-MMU each have separate
`dedicated system bus interfaces for coupling to the main
`memory and to other peripheral devices which are
`coupled to the system bus. Numerous other system
`elements can also be coupled to the system bus, includ
`ing an interrupt controller, an I/O processor, a bus
`arbiter, an array processor, and other peripheral con
`troller devices.
`23 Claims, 23 Drawing Sheets
`
`, : vscrons
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`

`

`US. Patent
`
`_Jun. 12, 1990
`
`Sheet 1 on3
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`4,933,835
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`US. Patent
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`Sheet 3 0f23
`US. Patent Jun. 12, 1990
`INTERFACE 1310
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`4,933,835
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`US. Patent
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`Jun. 12, 1990
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`US. Patent
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`Jun. 12, 1990
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`US. Patent
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`Jun. 12, 1990
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`US. Patent
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`US. Patent
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`US. Patent Jun. 12, 1990
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`US. Patent Jun. 12,1990
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`Sheet 12 0123
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`US. Patent Jun. 12, 1990
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`US. Patent Jun. 12, 1990
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`US. Patent Jun. 12, 1990
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`US. Patent
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`Jun. 12, 1990
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`mux SL‘l'
`PCinc CRhold
`OR hold
`
`
`
`i (43)
`
`_ _ __
`:Tgnslutor j
`I..-
`V
`OUTPUT
`Signals
`
`STKset
`
`19
`
`19
`
`

`

`US. Patent
`
`Jun. 12, 1990
`
`Sheet 190f23
`
`4,933,835
`
`7: 7 ca 25'_
`
`CAMMU CONTROL
`
`{320
`CACHE
`MEMORY
`
`,830
`CACHE
`CONTROL
`
`CAWT
`
`CAEN
`
`CA HIT/MISS
`
`(420
`QUAD.
`COMP.
`CMPEN
`HIT/
`H55 [5'0
`START
`CPU
`CONTROL
`
`TOH
`CPU
`
`(650
`_L8_‘E)
`our SYSTEM
`To
`BUS "SYSTEM
`IN CONTROL
`BUS
`
`MICRO
`ENGINE
`
`END
`
`TLBEN
`
`[350
`ma
`MEMORY
`
`_TLB ummss i
`‘820
`TLB WT
`
`TLB
`CONTROL
`
`20
`
`

`

`US. Patent
`
`Jun. 12,1990
`
`Sheet 20 of 23
`
`4,933,835
`
`$.; g _ 2 4 _
`CPU CONTROL
`
`FROM CPU FCR
`
`930
`
`
`
`
`INPUT
`DECODER
`
`FROM TLBHIT
`T
`PLF
`
`SYSBUSY
`FROM SYSCTL
`
`920
`
`OUTPUT
`DECODE'
`
`TO
`CAMMU
`
`CAHIT
`FROM
`CACTL
`
`
`
`
`‘ CPSTATE
`TO ENGINE
`
`
`END
`FROM
`ENGINE
`
`
`
`MCLK
`
`lNST/nDATA
`
`21
`
`21
`
`

`

`US. Patent
`
`Jun.12, 1990
`
`Sheet 21 0123
`
`4,933,835
`
`ng_ 2 5..
`
`TLB CONTROL
`
`LOAD/STORE/TAS
`
` PROTECT ION
`
`FAULT LEVEL
`
`DECODER
`
`
`TO
`CPCTL
`
`
`U
`TLB
`
`
`
`TLB
`sv W/X
`REPLACEMENT
`MEMORY
`uv wxx
`LOGIC
`
`
`
`
`WRITE
`STROBE
`
`GENERATOR
`
`W/x SELECT
`
`TLBWT
`FROM
`ENGINE
`
`
`
`TLB HIT
`TO
`CPCTL
`
`
`1030
`
`
`
`MEMORY
`MAPPED I/O
`
`
`DECODER
`
`
`
`RESET
`R/W REGISTERS
`R/W TLB
`
`22
`
`22
`
`

`

`US. Patent
`
`Jun. 12,1990
`
`Sheet 22 0123
`
`4,933,835
`
`7:49-26-
`CACHE CONTROL
`
`IIBO
`
`CACHE
`REPLACEMENT
`LOGIC
`
`
`
`
`
`
`
`— CACHE HIT
`CA HIT X
`DETECTOR
`
`CACHE
`MEMORY
`
`W/X SELECT
`
`CA HIT
`
`CP1COTL
`
`
`FROM SYSCTI.
`
`
`
`CAWT
`
`FROM ENGINE
`
`FROM CPCTL
`
`23
`
`23
`
`

`

`US. Patent
`
`Jun. 12,1990
`
`Sheet 23 of23
`
`4,933,835
`
`‘7:_7_—g_27_
`SYSTEM BUS CONTROL
`
`250
`
`W BUS
`
`SYSTEM
`OUTPUT REG.
`
`h. SYSTEM 9 ADDR/DATA
`hm
`65°
`READ/WRITE
`m READ/WRITE
`LOGIC
`
`INPUT REG.
`
`'220
`
`TRANSFER
`END
`
`COUNTER
`
`CAEQI'L QADR
`
`BUS CLOCK
`DETECTOR
`
`BUS WATCH
`START
`
`INST
`
`BUS WATCH
`DETECTOR
`
`READ/
`WRITE
`
`MODE
`
`CONTROL
`REGISTER
`
`'2 '
`
`I230
`
`I2IO
`
`I250
`
`T0
`SYSTEM
`BUS
`
`ROY
`
`"DIR
`
`BCLK
`MCLK
`
`TG
`c1-
`CBUSY
`
`260
`READ/WRITE
`
`FROM
`TLBCTL
`
`24
`
`24
`
`

`

`1
`
`4,933,835
`
`APPARATUS FOR MAINTAINING CONSISTENCY
`OF A CACHE MEMORY WITH A PRIMARY
`MEMORY
`
`This application is a continuation of US. patent appli-
`cation Ser. No. 915,272, which is a continuation-in-part
`of U.S. patent application Ser. No. 704,568, both now
`abandoned.
`
`BACKGROUND
`
`This invention relates to computer system architec-
`tures and more particularly to a microprocessor system
`having a system bus for coupling system elements, and
`having a dual bus microprocessor with separate instruc-
`tion and data cache interfaces coupled to independently
`operable instruction and data caches which are coupled
`to the system bus.
`Prior microprocessor system architectures have pro-
`vided a single external cache subsystem for data and/or
`instructions. Such systems have typically provided for
`direct microprocessor interface to both the cache sys-
`tem and other system elements. In prior systems, a sin-
`gle address/data/control bus provided for interfacing
`to the cache system and to other system elements. Some
`newer microprocessor designs have provided a separate
`interface to a single cache system for data and/or in-
`structions. Some have additionally provided a separate
`general bus for coupling of all system elements to the
`microprocessor,
`including main memory, peripheral
`controller chips, etc. Transfer of digital information to
`and from the microprocessor in these prior art designs
`could either occur between microprocessor and the
`cache system or the microprocessor and peripheral
`controllers or main memory directly. Furthermore, the
`cache system memory cycle required address informa-
`tion from the processor to the cache system for each
`transfer of digital information to the processor from the
`cache system. While the cache system could return one
`or more words of data per cache system data transfer,
`each cache system memory access cycle required a
`separate address be provided from the processor.
`SUMMARY
`
`In accordance with the present invention, a micro-
`processor-based computing system is provided, which
`has a system bus, a main memory and instruction and
`data cache and memory management units (cache-
`MMU) coupled to the system bus. The system bus pro-
`vides for communication of digital information. The
`main memory selectively stores and outputs digital in-
`formation from an addressable high speed read-write
`memory. The instruction cache-MMU manages selec.
`tive access to the main memory via the system bus and
`provides for the selective storage and output of digital
`instruction words to a mapped addressable very high
`speed cache memory, and therefrom to the processor
`via a very high speed processor/cache bus. A data
`cache-MMU manages access to the main memory for
`selectively storing and outputting digital data words to
`and from a mapped addressable very high speed cache
`memory, to and from main memory via the system bus.
`A processor is independently coupled to each of the
`instruction cache-MMU and data cache-MMU via inde-
`pendent very high speed buses. The processor provides
`means for processing data received from the data cache-
`MMU responsive to instructions simultaneously re-
`ceived from the instruction cache-MMU.
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`45
`
`50
`
`55
`
`65
`
`25
`
`2
`The data cache and instruction cache each have sepa-
`rate dedicated system bus interfaces for coupling to the
`main memory and to other peripheral devices coupled
`to the system bus. Numerous other system elements can
`be coupled to the system bus. These include an interrupt
`controller, an [/0 processor, a bus arbiter, an array
`processor, and other peripheral interface or peripheral
`controller devices. The 1/0 processor provides intelli-
`gent interface to various I/O devices and other proto—
`cols and buses. The bus arbiter is coupled to the devices
`coupled to the system bus, such as the instruction and
`data caches, the I/O processor. etc. The bus arbiter
`provides means for selectively resolving channel access
`conflicts between the various elements coupled to the
`system bus so as to maintain the integrity of communi-
`cations on the system bus.
`The data cache contains an address register which is
`loaded with an address from the processor prior to each
`transfer of a defined number of words of data between
`the data cache and the processor. The instruction cache
`contains a program counter which is loaded with an
`address from the processor, and which is advanced by a
`cache advance signal from the microprocessor. The
`instruction cache program counter is loaded with an
`address only during branch instructions and context
`switches. This provides for continuous transfer of in-
`structions from the instruction cache to the processor
`responsive to a single initial address until a branch or
`context switch occurs.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`These and other features and advantages of the pres-
`ent invention will become apparent from the following
`detailed description of the drawings, wherein:
`FIG. 1 illustrates a block diagram of a microproces-
`sor-based dual cache/dual bus system architecture in
`accordance with the present invention;
`FIG. 2 shows CPU 110 of FIG. 1 in more detail;
`FIG. 3 shows the CPU instruction bus interface of
`FIG. 2 in more detail;
`FIG. 4 is an electrical diagram illustrating the instruc-
`tion cache/processor bus, the data cache/processor bus,
`and the system bus;
`FIG. 5 illustrates the system bus to cache interface of
`FIG. 4 in greater detail;
`FIG. 6 is an electrical diagram illustrating the dri-
`vers/receivers between the instruction cache~MMU
`and the system bus;
`FIGS. 7A-C illustrate the virtual memory, real mem-
`ory, and virtual address concepts as utilized with the
`present invention;
`FIG. 8 illustrates an electrical block diagram of a
`cache memory management unit;
`FIG. 8A shows the translation lookaside buffer sub-
`system (TLB) in more detail;
`FIG. SB shows the hardwired translation lookaside
`buffer (HTLB) in more detail;
`FIG. 9 is a detailed block diagram of the cache mem-
`ory management unit of FIG. 8;
`FIGS. IDA—B illustrate the storage structure within
`the cache memory subsystem 320;
`FIGS. IlA—B illustrate the TLB memory subsystem
`350 storage structure in greater detail;
`FIG. 12 illustrates the cache memory quadword
`boundary organization;
`FIG. 13 illustrates the hardwired virtual to real trans-
`lations provided by the TLB subsystem;
`
`25
`
`

`

`3
`FIG. 14 illustrates the cache memory subsystem and
`affiliated cache-MMU architecture which support the
`quadword boundary utilizing line registers and line
`boundary registers;
`FIG. 15 illustrates the load timing for the cache-
`MMU systems 120 and 130 of FIG. 1;
`FIG. 16 illustrates the store operation for the cache-
`MMU systems 120 and 130 of FIG. 1, for storage from
`the CPU to the cache-MMU in copyback mode, and for
`storage from the CPU to the cache-MMU and the main
`memory for the write-through mode of operation;
`FIG. 17A illustrates the data flow of store operations
`on Copy-Back mode, and FIG. 17-B illustrates the data
`flow of operations on Write-Thru Mode;
`FIG. 18 illustrates the data flow and state flow inter-
`action of the CPU, cache memory subsystem, and TLB
`memory subsystem;
`FIG. 19 illustrates the data flow and operation of the
`DAT and TLB subsystems in performing address trans-
`lation;
`FIG. 20 illustrates a block diagram of the cache-
`MMU system, including bus interface structures inter-
`nal to the cache-MMU;
`FIG. 21 is a more detailed electrical block diagram of
`FIG. 20;
`FIG. 22 is a detailed electrical block diagram of the
`control logic microengine 650 of FIG. 21;
`FIG. 23 illustrates an arrangement of the major con-
`trol and timing circuits for the Cache-MMU;
`FIG. 24 illustrates CPU control circuit 810 of FIG.
`23 in greater detail;
`FIG. 25 illustrates TLB control circuitry 820,
`TLBCTL, of FIG. 23 in greater detail;
`FIG. 26 illustrates the cache control circuit 830,
`CACTL, of FIG. 23 in greater detail; and
`FIG. 27 illustrates the System Bus control circuit 840,
`SYSCTL, of FIG. 23 in greater detail.
`DETAILED DESCRIPTION OF THE
`DRAWINGS
`
`Referring to FIG. 1, a system embodiment of the
`present invention is illustrated. A central processing
`unit 110 is coupled via separate and independent very
`high speed cache/processor buses, an instruction bus
`121 and a data bus 131, coupling to an instruction cache-
`memory management unit 120 and a data cache-mem-
`ory management unit 130, respectively, each having an
`interface to main memory 140 through system bus 141.
`Main memory 140 contains the primary storage for the
`system, and may be comprised of dynamic RAM, static
`RAM, or other medium to high speed read-write mem-
`ory. Additionally, a system status bus 115 is coupled
`from the CPU 110 to each of the instruction cache-
`memory management unit 120 and data cache-memory
`management unit 130.
`Additionally, as illustrated in FIG. 1, other system’s
`elements can be coupled to the system bus 141, such as
`an l/O processing unit, IOP 150, which couples the
`system bus 141 to the I/O bus 151. The I/O bus 151 may
`be a standard bus interface, such as Ethernet, Unibus,
`VMEbus or Multibus. I/O bus 151 can couple to the
`secondary storage or other peripheral devices, such as
`hard disks, floppy disks, printers, etc. Multiple IOPs can
`be coupled to the system bus 141 and thereby can com-
`municate with the main memory 140.
`The CPU 110 is also coupled via interrupt lines 111 to
`an interrupt controller 170. Each of the units contend-
`ing for interrupt priority to the CPU has separate inter-
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`45
`
`50
`
`55
`
`65
`
`4,933,835
`
`4
`rupt lines coupled into the interrupt controller 170. As
`illustrated in FIG. 1, the array processor 188 has an
`interrupt output 165 and the 10? 150 has an interrupt
`output 155. Controller 170 prioritizes and arbitrates
`priority of interrupt requests to the CPU 110.
`A system clock 160 provides a master clock MCLK
`to the CPU 110, instruction cache~memory manage-
`ment unit 120 and data cache-memory management unit
`130 for synchronizing operations. In addition, a bus
`clock BCLK output from the system clock 160, pro-
`vides bus synchronization signals for transfers via the
`system bus 141, and is coupled to all system elements
`coupled to the system bus 141.
`Where multiple devices request access to the system
`bus 141 at the same time, a bus arbitration unit unit 180
`is provided which prioritizes access and avoids colli-
`sxons.
`
`FIG. 2 shows CPU (processor) 110 in greater detail.
`Instructions from instruction cache-MMU 120 enter
`from instruction bus 121 to instruction bus interface unit
`1310 where they are held in prefetch buffer 131] until
`needed for execution by instruction control unit 1320.
`Instructions are also supplied as needed from macro
`instruction unit 1330 which holds frequently used in-
`struction sequences in read only memory. Instructions
`first enter register 102 and then register 104 (instruction
`registers B and C, respectively) which form a two stage
`instruction decoding pipeline. Control signals from
`instruction decoder 103 are timed and gated to all parts
`of the processor for instruction execution. For speed of
`execution, instruction decoder 103 is preferably imple—
`mented in the form of sequential state machine logic
`circuitry rather than slower microcoded logic circuitry.
`Program counter 1321 contains the address of the in-
`struction currently being executed in instruction regis-
`ter C. The execution unit 105, comprising integer execu-
`tion unit 1340 and floating point execution unit 1350,
`executes data processing instructions. Data is received
`from and transmitted to data cache-MMU 130 over data
`cache-MMU bus 131 through data bus interface 109.
`Instruction interface 1310 of processor 110 includes a
`multi-stage instruction bus 1311 which provides means
`for storing, in seriatim, a plurality of instruction parcels,
`one per stage. A cache advance signal ISEND is sent by
`the instruction interface as it has free space. This signals
`instruction cache-MMU 120 to provide an additional
`32-bit word containing two 16-bit instruction parcels
`via instruction bus 121. This multi-stage instruction
`buffer increases the average instruction throughput
`rate.
`
`Responsive to the occurrence of a context switch or
`branch in the operation of the microprocessor system,
`instruction interface 1310 selectively outputs an instruc-
`tion address for storage in an instruction cache-MMU
`120 program counter. A context switch can include a
`trap, an interrupt, or initialization. The cache advance
`signal provides for selectively incrementing the instruc-
`tion cache-MMU program counter, except during a
`context switch or branch.
`In FIG. 3, prefetch buffer 1311 is shown in detail,
`comprising the four prefetch buffer register stages IH,
`IL, IA and IC. The IH register stage holds a lé-bit
`instruction parcel in register 1312 plus an additional bit
`of control information in register 1313, IHD, which bit
`is set to indicate whether IH currently contains a parcel.
`Each of the register stages is similarly equipped to con-
`tain an instruction parcel and an associated control bit.
`Buffer advance logic circuit 1314 administers the parcel
`
`26
`
`26
`
`

`

`4,933,835
`
`6
`
`agement units of the instruction cache-MMU 120 and
`data cache-MMU 130 perform all memory manage-
`ment, protection, and virtual to physical address trans-
`lation.
`-
`As illustrated in FIGS. 1, 7A-C, and 8, the processor
`110 provides virtual address outputs which have a
`mapped relationship to a corresponding physical ad-
`dress in main memory. The memory management units
`of the instruction and data cache-MMUs 120 and 130
`are responsive to the respective virtual address outputs
`from the instruction and data interfaces of the processor
`110, such that the memory management units selec-
`tively provide physical address and the associated
`mapped digital information for the respective virtually
`addressed location. When the requested information for
`the addressed location is not stored in the respective
`cache-MMU memories (i.e. a cache miss), the micro
`engine of the cache-MMUs provides a translated physi-
`cal address for output to the main memory 140. The
`corresponding information is
`thereafter
`transferred
`from the main memory 140 to the respective instruction
`cache-MMU 120 or to or from the data cache-MMU
`130, and as needed to the processor 110.
`The two separate cache interface buses, the instruc-
`tion bus 121 and the data bus 131 are each comprised of
`multiple signals. As illustrated in FIGS. 4 and 5, for one
`embodiment, the signals on both the data cache bus 131
`and the instruction cache bus 121 are as follows:
`
`DATA CACHE BUS
`
`ADF<31:0>: address/data bus
`These lines are bidirectional and provide an address-
`/data multiplexed bus. The CPU puts an address on
`these lines for one clock cycle. 0n store operations, the
`address is followed by the data. On load or TAS (i.e.
`test and set) operations,
`these bus lines become idle
`(floating) after the address cycle, so that these lines are
`ready to receive data from the Data Cache-MMU. The
`Data Cache-MMU then puts the addressed data on the
`lines.
`FC<3=O>= function code/trap code
`The CPU puts “the type of data transfer" on
`FC<3:0> lines for one clock cycle at the address cy-
`cle. The D-CACHE, or I-CACHE, sends back “the
`type of trap" on abnormal operations along with TSTB
`(i.e. Trap Strobe Signal).
`
`
`Transfer tm
`
`On ASF Active
`
`FC < 3
`2
`l
`D
`>
`0
`0
`0
`0
`load singleword mode
`0
`D
`0
`1
`load doubleword mode
`0
`0
`1
`0
`load byte
`0
`D
`l
`I
`load halfword
`O
`l
`O
`0
`Test and set
`1
`X
`0
`0
`store singieword
`1
`X
`0
`1
`store doubleword
`1
`X
`1
`0
`store byte
`
`1 1X1 store halfword
`
`
`
`
`The D-cache puts the TRAP code on PC to respond to
`the CPU.
`
`
`Trap Code
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`45
`
`50
`
`55
`
`65
`
`(on TSTB active!
`FC < 3
`2
`l
`X
`0
`0
`
`0
`
`0
`
`>
`
`5
`and control bit contents of the four register stages. In
`response to the parcel advance control signal PADV
`from instruction decoder 103, buffer advance logic
`circuit 1314 gates the next available instruction parcel
`into instruction register 102 through multiplexer 1315,
`and marks empty the control bit associated with the
`register stage from which the parcel was obtained. In
`response to the control bits of the four stages, circuit
`1314 advances the parcels to fill empty register stages.
`As space becomes available for new instruction parcels
`from the instruction cache-MMU, cache advance logic
`circuit 1316 responds to the control bits to issue the
`ISEND signal on instruction bus 121. Instruction cache-
`MMU responds with a 32-bit word containing two
`parcels. The high order parcel is received in IR, and the
`low order parcel in IL through multiplexor 1319.
`On each MCLK cycle both the buffer advance and
`cache advance circuits attempt to keep the prefetch
`buffer stages full as conditions permit. The buffer ad-
`vance and cache circuits are implemented in combina-
`tional logic in a manner that is evident to those skilled in
`the art. For example, cache advance circuit 1316 pro-
`duces ISEND in response to the negation of the follow-
`ing boolean logic expression: (ICD,IAD,ILD+ICD-
`,IAD,IHD+ICD,ILD,II-ID+IAD,ILD,IHD).
`The
`first two terms indicates that IA and IC are full with
`either IH or IL full. The last two terms indicate that IL
`and 1H are full with either 1C or IA full. In all of these
`cases, there is no available register space in the prefetch
`buffer, while in all other cases, there is space.
`Instruction parcels stored in instruction register 102
`are partially decoded before being sent to instruction
`register 104 to complete the decoding process. Decod-
`ing of branch instructions is done by branch decoder
`1317, a part of decoder 103, in response to instruction
`register 102. In the case of a branch instruction, the
`branch address is set into program counter 1321 from
`the processor S bus, cache advance circuit 1316 is inhib-
`ited from sending ISEND and the prefetch buffer is
`flushed (signal path 1318). Branch decoder 1317 instead
`sends IASF to the instruction cache-MMU. This causes
`instruction cache-MMU 120 to take the new branch
`address from cache bus 121.
`The MCLK is the clock to the entire main clock, (e.g.
`33 MHz), logic. BCLK is the system bus clock, prefera-
`bly at either i or i of the MCLK.
`For the system bus 141 synchronization, BCLK is
`delivered to all the units on the system bus, i.e. IOPs,
`bus arbiter, caches, interrupt controllers, the main mem-
`ory and so forth. All signals must be generated onto the
`bus and be sampled on the rising edge of BCLK. The
`propagation delay of the signals must be within the one
`cycle of BCLK in order to guarantee the synchronous
`mode of bus operation. The phase relationships between
`BCLK and MCLK are strictly specified. In one em-
`bodiment, BCLK is a 50% duty-cycle clock of twice or
`four times the cycle time of MCLK, which depends
`upon the physical size and loads of the system bus 141.
`As illustrated in FIG. 1, the transfer of instructions is
`from the instruction cache-MMU 120 to the processor
`110. The transfer of data is bidirectional between the
`data cache-MMU 130 and processor 110. Instruction
`transfer is from the main memory 140 to the instruction
`cache-MMU 120. Instruction transfer occurs whenever
`an instruction is required which is not resident in the
`cache memory of instruction cache-MMU 120. The
`transfer of data between the data cache-MMU 130 and
`main memory 140 is bidirectional. The memory man-
`
`27
`
`27
`
`

`

`4,933,835
`
`7
`-continued
`
`Trap Code
`
`son TSTB active!
`
`FC < 3
`2
`l
`0
`>
`X
`0
`0
`1
`memory error (MSBE)
`X
`0
`l
`0
`memory error (MDBE)
`X
`0
`l
`l
`X
`l
`0
`0
`X
`l
`0
`1
`X
`l
`l
`O
`X
`l
`l
`l
`
`page fault
`protection fault (READ)
`protection fault (WRITE)
`
`ASF: address strobe
`ASF is activated by the CPU indicating that the ‘ad‘
`dress’ and ‘type of data transfer’ are valid on AD-
`F<3l:10> and FC<3:0> lines, respectively. ASF is
`activated one half a clock cycle prior to the address
`being activated on the ADF bus.
`RSP: response signal
`On load operations, the RSP signal is activated by the
`D-cache indicating that data is ready on the ADF bus.
`RSP is at the same timing as the data on the ADF bus.
`The D-cache sends data to CPU on a load operation.
`On store operations, RSP is activated when the data
`cache-MMU becomes ready to accept the next opera-
`tion.
`On load-double, RSP is sent back along with each
`data parcel transf