throbber
U.S. Patent No. 5,463,750
`Petition for Inter Partes Review, Declaration of V. Thomas Rhyne, Ph. D
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`
`
`
`ARM Inc.
`Petitioner
`
`v.
`
`VANTAGE POINT TECHNOLOGY, INC.
`Patent Owner
`
`
`
`U.S. Patent No. 5,463,750
`Issue Date: October 31, 1995
`
`Title: METHOD AND APPARATUS FOR TRANSLATING VIRTUAL
`ADDRESSES IN A DATA PROCESSING SYSTEM HAVING MULTIPLE
`INSTRUCTION PIPELINES AND SEPARATE TLB’S FOR EACH PIPELINE
`
`
`
`
`
`
`DECLARATION OF V. THOMAS RHYNE, PH.D., P.E., R.P.A.
`
`
`
`
`
`
`
`
`
`
`Case No. IPR2014-TO BE ASSIGNED
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`ARM_VPT_IPR_00000419
`
`ARM Ex. 1009
`IPR Petition - USP 5,463,750
`
`

`
`
`U.S. Patent No. 5,463,750
`Petition for Inter Partes Review, Declaration of V. Thomas Rhyne, Ph. D
`
`
`
`
`
`I, Vernon Thomas Rhyne, declare:
`
`1. I have been retained by Wiley Rein LLP to provide my opinions
`
`concerning the background of the computer art as related to the validity
`
`of U.S. Patent No. 5,463,750 (“the ’750 Patent”). In particular, in this
`
`Declaration I provide my opinions regarding the state of that art as of
`
`November 1993 for processor architectures that used virtual memory
`
`and mapping caches (known as “translation lookaside buffers” or
`
`“TLB’s”) to perform a translation which mapped virtual addresses to
`
`physical addresses used to access memory in a computer system. I am
`
`being compensated for my work in preparing this Declaration at the rate
`
`of $695 per hour, plus reimbursement of reasonable direct expenses. I
`
`have no other interest in this matter or the parties involved in this
`
`matter.
`
`I. QUALIFICATIONS
`
`2. My qualifications for forming the opinions set forth in this Declaration
`
`are summarized in the following paragraphs and explained in more
`
`detail in my curriculum vitae which is attached as part of Exhibit A to
`
`this report. Exhibit A also includes a list of my publications and a
`
`listing of my testimony during the past four years.
`
`
`
`1
`
`ARM_VPT_IPR_00000420
`
`

`
`
`U.S. Patent No. 5,463,750
`Petition for Inter Partes Review, Declaration of V. Thomas Rhyne, Ph. D
`
`
`
`
`
`3. I have studied, taught, and practiced electrical engineering for over fifty
`
`years. I hold degrees from Mississippi State University (Bachelors of
`
`Science in Electrical Engineering with Honors, 1962), the University of
`
`Virginia (Masters of Electrical Engineering, 1964), and the Georgia
`
`Institute of Technology (Ph.D. in Electrical Engineering, 1967). I have
`
`been a registered Professional Engineer in the State of Texas since 1969
`
`(TX, No. 28,728). I have been a Registered Patent Agent since 1999
`
`(No. 45,041).
`
`4. I taught electrical engineering, computer engineering, computer
`
`architecture, and computer science at the undergraduate and graduate
`
`levels full-time at Texas A&M University from 1967 to 1983 and part-
`
`time at the graduate level at the University of Texas from 1983 to 1991.
`
`My twenty-plus years of industrial experience include work for the
`
`Electric Power Research Institute, Texas Instruments, Control Data
`
`Corporation, NASA, Texas Digital Systems, Inc. (a company I co-
`
`founded to produce microprocessor-based computer peripherals in
`
`1976), the Microelectronics and Computer Technology Corporation
`
`(MCC), and Motorola, Inc.
`
`5. I have extensive experience with computer technology, including
`
`design and teaching experience with a variety of computer systems,
`2
`
`
`
`ARM_VPT_IPR_00000421
`
`

`
`
`U.S. Patent No. 5,463,750
`Petition for Inter Partes Review, Declaration of V. Thomas Rhyne, Ph. D
`
`
`
`microcomputer systems, and microcontrollers. I have participated in
`
`the design of several computer systems and microprocessors, and have
`
`designed systems which made use of those devices as control elements.
`
`I am an experienced programmer in a variety of programming
`
`languages as well as assembly-level language on a number of different
`
`computers and microprocessors.
`
`6. During my academic career I authored thirty technical papers and
`
`research reports; as I noted above, those papers and reports are listed in
`
`Exhibit 1. I also presented papers at a number of technical conferences
`
`and authored an award winning textbook, Fundamentals of Digital
`
`System Design, published by Prentice-Hall in 1973 and adopted at over
`
`thirty-five U.S. and international universities during its lifetime. My
`
`textbook has also been cited as a reference by the U.S. Patent and
`
`Trademark Office. I have also served as a technical reviewer for
`
`Prentice-Hall, the IEEE Transactions on Computing, and IEEE
`
`Spectrum.
`
`7. I have been a member of the IEEE for over fifty years and am a Life
`
`Fellow of that professional organization. I was elected to serve on the
`
`IEEE Board of Directors for two terms representing the engineering
`
`
`
`
`
`3
`
`ARM_VPT_IPR_00000422
`
`

`
`
`U.S. Patent No. 5,463,750
`Petition for Inter Partes Review, Declaration of V. Thomas Rhyne, Ph. D
`
`
`
`education community and the IEEE Computer Society. I was also
`
`elected to two terms as the IEEE Treasurer.
`
`8. I have extensive experience with the accreditation of engineering and
`
`computer science programs in the U.S. and abroad, an activity which
`
`provided me an excellent opportunity to become familiar with the
`
`program curricula, faculties, and graduates from a large number of U.S.
`
`and international colleges and universities. I represented the IEEE for
`
`five years on the Engineering Accreditation Commission and for six
`
`years on the Board of Directors of the Accreditation Board for
`
`Engineering and Technology (ABET). I have assisted Japanese
`
`universities and industries in the establishment of the Japanese
`
`Accreditation Board for Engineering Education, and have led several
`
`other international accreditation missions.
`
`9. I was appointed by the U.S. National Research Council to the Panel of
`
`Assessment for the Electronics and Electrical Engineering Laboratory
`
`of the U.S. National Institute of Standards and Technology. I served on
`
`that Panel for seven years, including three terms as its chair; based on
`
`that work I was invited to provide testimony before the U.S. Congress
`
`regarding the status of the Laboratory.
`
`
`
`
`
`4
`
`ARM_VPT_IPR_00000423
`
`

`
`
`U.S. Patent No. 5,463,750
`Petition for Inter Partes Review, Declaration of V. Thomas Rhyne, Ph. D
`
`
`
`10. My experience and qualifications have been recognized by the Texas
`
`Society of Professional Engineers (Young Engineer of the Year in
`
`Texas, 1973); the American Society for Engineering Education
`
`(Terman Awardee as the “Outstanding Young Electrical Engineering
`
`Educator in the U.S.,” 1980); the Institute of Electrical and Electronics
`
`Engineers (IEEE Fellow, 1990, recognizing my contributions to
`
`“computer engineering and computer engineering education”); the
`
`Accreditation Board for Engineering and Technology (ABET Fellow,
`
`1992); and the IEEE Computer Society (Golden Core Awardee, 2000).
`
`11. Based on my academic and consulting experience, I am familiar with a
`
`variety of computer-based user interfaces, database technologies, and
`
`data-communications protocols. I have managed large and complex
`
`software-development programs and have been and am familiar with
`
`the development of software systems for supporting complex
`
`operations.
`
`12. My experience has also included the use of a variety of communications
`
`systems such as the dial-up telephone network to carry data; the use of
`
`leased-line telephone connections to carry data; the use of the
`
`ARPANET (the precursor to the Internet) to carry data; and extensive
`
`
`
`
`
`5
`
`ARM_VPT_IPR_00000424
`
`

`
`
`U.S. Patent No. 5,463,750
`Petition for Inter Partes Review, Declaration of V. Thomas Rhyne, Ph. D
`
`
`
`
`
`use of the Internet itself as that system came into being in the early
`
`1990’s.
`
`13. While at MCC I also managed MCC’s research and development
`
`programs dealing with graphical user interfaces, natural-language
`
`interfaces, and early website development tools. I also managed
`
`distributed database development for several years at MCC, as well as
`
`MCC’s successful research program on Internet-based credit card fraud
`
`detection using neural networks. While working at MCC in 1994 I was
`
`assigned to represent MCC and its participating companies in the initial
`
`planning efforts of the U.S. Technology Policy Working Group
`
`addressing the technical challenges associated with the planned
`
`National Information Infrastructure (“NII”), a national effort being
`
`promulgated, in a large part, by Al Gore through the U.S. Department
`
`of Commerce. The report of that initial planning effort is available at
`
`www.cra.org/govaffairs/archives/niireport/.
`
`14. My teaching and industrial experience has included the architectural
`
`design of a number of computers ranging from microprocessors to
`
`supercomputers. As part of that experience I have worked with the
`
`design of high-speed instruction pipelines and with virtual memory
`
`systems which made use of translation look-aside buffers. I taught
`6
`
`
`
`ARM_VPT_IPR_00000425
`
`

`
`
`U.S. Patent No. 5,463,750
`Petition for Inter Partes Review, Declaration of V. Thomas Rhyne, Ph. D
`
`
`
`computer architecture at the graduate level at both Texas A&M and the
`
`University of Texas. At the latter institution I used the Hennessey and
`
`Patterson textbook for my graduate-level class.
`
`15. I retired from full-time work as of 1997 and draw retirement benefits
`
`from Texas A&M University. In addition to the work described above
`
`and in my curriculum vitae which is attached to this expert report as
`
`Exhibit 1, I have worked part-time as a consulting engineer for the past
`
`thirty years doing computer systems design, application-specific system
`
`design, and expert witness work in intellectual property litigation.
`
`16. I have read and am familiar with the ’750 patent and the file history of
`
`that patent.
`
`17. As part of my preparation for forming the opinions set forth in this
`
`Declaration, I have reviewed and relied upon Exhibits 1001, 1002, and
`
`1006-1013 as identified in the Exhibit list attached to the Requests for
`
`inter partes Review to which this Declaration is also attached. In
`
`particular, I reviewed and relied upon the following:
`
`• The ’750 patent;
`
`• The prosecution history of the ’750 patent;
`
`• United States Patents Nos. 3,947,823 (“the ’823 patent”);
`
`
`
`
`
`7
`
`ARM_VPT_IPR_00000426
`
`

`
`
`U.S. Patent No. 5,463,750
`Petition for Inter Partes Review, Declaration of V. Thomas Rhyne, Ph. D
`
`
`
`• 4,935,835 (“the ’835 patent”); and 4,920,477 (“the ’477 patent”);
`
`• A well-known computer textbook entitled Computer Architecture: A
`
`Quantitative Approach by John L. Hennessy and David A. Patterson,
`
`Morgan Kaufman, 1990 (“Hennessy and Patterson”);
`
`• DEC VAX 8800, Digital Technical Journal, Number 4, February 1987,
`
`ISBN 1-55558-001-7. The Digital Technical Journal is published by
`
`Digital Equipment Corporation, 77 Reed Road, Hudson,
`
`Massachusetts 01749. Copyright © 1987 Digital Equipment Corporation
`
`(the “VAX 8800” reference);
`
`• “A VLIW Architecture for a Trace Scheduling Compiler,” Colwell et al,
`
`IEEE Transactions On Computers, Vol. 37, No. 8, August 1888 (IEEE)
`
`(“Colwell”);
`
`• The “Decision Denying Institution of Inter Partes Review” for
`
`IPR2014-00467 dated September 5, 2014 (the “Board Decision”);
`
`• Vantage Point’s Infringement Contentions for the Cortex A8 and Cortex
`
`A9 processors;
`
`• The PowerPC 601 Microprocessor, Moore, IEEE Proc. Compcon,
`
`Feb. 1993, pp. 109-116. (“Moore”); and
`
`
`
`
`
`8
`
`ARM_VPT_IPR_00000427
`
`

`
`
`U.S. Patent No. 5,463,750
`Petition for Inter Partes Review, Declaration of V. Thomas Rhyne, Ph. D
`
`
`
`
`
`• “The 68040 Processor: Part 2, Memory Design and Chip Verification,”
`
`Robin W. Edenfield, et al., IEEE Micro, June 1990. (“Edenfield”).
`
`II. BACKGROUND OF THE ART
`
`18. I have reviewed the “Technical Introduction To The ’750 Patent”
`
`presented in the Request for inter partes Review to which my
`
`Declaration is attached. I agree with and adopt that summary herein.
`
`For brevity, my declaration does not repeat that summary. However,
`
`my Declaration does add some additional information of relevance to
`
`that introduction.
`
`19. By the time of the filing of the ’750 patent in November 1993, the
`
`technology for TLB’s was well-known to the art. The ’750 patent
`
`appears to acknowledge this in its descriptions of Figures 1-4 which are
`
`all identified as being part of conventional prior art systems. However,
`
`the ’750 patent does not provide any specific details about the structure
`
`or operation of TLB’s. Instead, the patent appears to rely on a prior art
`
`patent cited during prosecution (U.S. Patent No. 4,933,835) to provide
`
`the technical details of TLB technology.
`
`
`
`
`
`9
`
`ARM_VPT_IPR_00000428
`
`

`
`
`U.S. Patent No. 5,463,750
`Petition for Inter Partes Review, Declaration of V. Thomas Rhyne, Ph. D
`
`
`
`
`
`III. THE VAX 8800
`
`20. I have reviewed the claim charts showing the correspondence between
`
`the VAX 8800 reference and claims 8-12 of the ’750 patent which are
`
`located in the Request for inter partes Review to which this Declaration
`
`is attached. I agree that that those charts show that the architecture of
`
`the VAX 8800 discloses to one of skill in the art all of the elements of
`
`claims 8-12 of the ’750 patent and therefore either anticipates or renders
`
`obvious those claims.
`
`21. I note that some aspects of the VAX 8800 use slightly different
`
`terminology from that used in the ’750 patent. For example, as shown
`
`in the following figure taken from page 43 of the VAX 8800 reference,
`
`the VAX 8800 uses the terms “translation buffer” or “TB” for the same
`
`component referenced in the ’750 patent as the “translation lookaside
`
`buffer” or “TLB.”
`
`
`
`10
`
`ARM_VPT_IPR_00000429
`
`

`
`
`
`
`U.S. Patent No. 5,463,750
`Petition for Inter Partes Review, Declaration of V. Thomas Rhyne, Ph. D
`
`
`
`
`22. One of skill in the art would understand that the lower box shown above
`
`is depicted with three parallel lines which together form the common
`
`mathematical symbol for congruence or equivalence.1 Based on these
`
`symbols and the usage of the box in the above diagram, one of skill in
`
`the art would understand this box to represent a comparator which
`
`compared its two inputs (portions of virtual addresses) and output a
`
`signal indicating whether or not those addresses matched (the “TB
`
`HIT” output signal which, when TRUE, indicated that a given virtual
`
`address was found in the “TB” buffer).
`
`23. On page 41 of the VAX 8800 reference there is a discussion of the
`
`“Characteristics of the Translation Buffer.” One of skill in the art
`
`
`1 See, for example, http://en.wikipedia.org/wiki/Table_of_mathematical_symbols.
`11
`
`
`
`ARM_VPT_IPR_00000430
`
`

`
`
`U.S. Patent No. 5,463,750
`Petition for Inter Partes Review, Declaration of V. Thomas Rhyne, Ph. D
`
`
`
`
`
`would understand that “direct mapped” is a term of art used to describe
`
`a family of caches. These caches are addressed by the input address
`
`being searched for (in this instance, the “tags” for the virtual address).
`
`Direct mapped caches are addressed by selecting only a single entry
`
`based on a subset of bits from a virtual address – the “tag.” Alternative
`
`cache types include “set-associative” and “fully-associative.” Those
`
`caches use a different approach to determining whether or not a given
`
`data item is currently held within them.
`
`IV. U.S. PATENT NO. 4,920,477
`
`24. I have reviewed the ’477 patent and believe it discloses all of the
`
`elements, either implicitly or explicitly, of claims 8-12 of the ’750
`
`patent. I have also reviewed the claim charts showing the
`
`correspondence between the ’477 patent reference and claims 8-12 of
`
`the ’750 patent which are within the Request for inter partes Review to
`
`which this Declaration is attached. I agree that those charts show that
`
`the ’477 patent discloses all of the elements of those claims to one of
`
`skill in the art.
`
`25. The ’477 patent shows a system with multiple instruction pipelines in
`
`which each pipeline includes its own data TLB for performing
`
`
`
`12
`
`ARM_VPT_IPR_00000431
`
`

`
`
`U.S. Patent No. 5,463,750
`Petition for Inter Partes Review, Declaration of V. Thomas Rhyne, Ph. D
`
`
`
`translations of virtual address to physical address for data being
`
`accessed.
`
`26. Figure 1 of the ‘477 patent as copied below shows such a system with
`
`multiple pipelines each with its own data TLB.
`
`
`
`
`27. Each of the “integer processors” denominated as 20, 22, 24, and 26 in
`
`Figure 1 is an instruction pipeline. The “Background Of The
`
`Invention” provided in the ’477 patent states that “[t]he invention
`
`relates generally to pipelined computer apparatus….” 1:7-8. That
`
`section of the ’477 patent then continues as “[i]n a Trace computer,
`
`such as that described hereinafter …, the data processor has a pipelined
`
`
`
`13
`
`ARM_VPT_IPR_00000432
`
`

`
`
`U.S. Patent No. 5,463,750
`Petition for Inter Partes Review, Declaration of V. Thomas Rhyne, Ph. D
`
`
`
`CPU….” 1: 22-25. Also, as stated in the ’477 patent, “program
`
`execution and memory operations herein are all pipelined.” 25:24-25.
`
`These passages indicate to one of skill in the art that the processors
`
`described in the ’477 patent operate as instruction “pipelines.”
`
`28. Additionally, as shown in Figure 3 of the ’477 patent, each “integer
`
`processor” is a pipeline having two ALUs, Integer ALU 0 and Integer
`
`ALU 1, both of which are connected to a TLB. ALU0 is responsible
`
`for generating memory addresses for load and store operations.
`
`See 23:15-26. “The integer processor, in the illustrated embodiment,
`
`includes two independent arithmetic logic units 70, 72 (designated
`
`ALUO and ALU1 respectively), 64 X 32-bit register file 74, a virtual to
`
`physical address data translation lookaside buffer 76 [TLB] …”
`
`(5:9-13). Thus, each TLB is associated with an integer processor that
`
`has its own pipeline and thus each TLB is associated with its own
`
`instruction pipeline.
`
`29. In Fig 12 of the ’477 patent, Element 76, a “TLB Ram” as discussed at
`
`23:33-43 and 24:10-29, is a translation buffer, and as shown in Fig. 1 of
`
`the patent, and the item marked “DTLB” in Integer Processor 3,
`
`Element 20, is a first translation buffer that is associated with the
`
`
`
`
`
`14
`
`ARM_VPT_IPR_00000433
`
`

`
`
`U.S. Patent No. 5,463,750
`Petition for Inter Partes Review, Declaration of V. Thomas Rhyne, Ph. D
`
`
`
`instruction pipeline contained in the Integer Processor, an example of
`
`which is shown in Fig 3.
`
`30. Similar to the ’750 patent, the ’477 patent relies upon the knowledge of
`
`one skilled in the art regarding some of the details of TLB’s. For
`
`example, the ’477 patent simply notes that “the translation lookaside
`
`buffer translates virtual memory addresses from the ALU's to physical
`
`memory addresses using a table lookup mechanism well known to those
`
`practiced in the art, … ” 5:20-23.
`
`31. By the time of the filing of the ’477 patent in April 1987, and certainly
`
`by the time of the filing of the ’750 patent in November 1993, the
`
`structure and functionality of TLB’s was well known to one of skill in
`
`the art. See, e.g., the ’477 patent at 5:20-23 (“Functionally, the
`
`translation lookaside buffer translates virtual memory addresses from
`
`the ALU's to physical memory addresses using a table lookup
`
`mechanism well known to those practiced in the art”)
`
`32. For example, one of skill in the art would have understood that the TLB
`
`used in the ’477 patent would necessarily include storing a subset of
`
`translation data from the master translation memory, e.g., a page table
`
`located in main memory, because the whole purpose of a TLB is to act
`
`as a cache memory for the translation data in order to accelerate the
`15
`
`
`
`
`
`ARM_VPT_IPR_00000434
`
`

`
`
`U.S. Patent No. 5,463,750
`Petition for Inter Partes Review, Declaration of V. Thomas Rhyne, Ph. D
`
`
`
`virtual-to-physical translation process. This is noted in many textbooks
`
`including Hennessy and Patterson, which describes a TLB as a “special
`
`cache” of the “page tables” that “are stored in main memory.” See
`
`pages 437-48. This is particularly true given the reference to “a table
`
`lookup mechanism well known to those practiced in the art” made in
`
`the ’477 patent as noted above.
`
`33. Additionally, one of skill in the art would understand the reference to
`
`“TLB RAM 76” to include a plurality of addressable storage locations –
`
`just as in the ’750 patent. “RAM” (a well-known acronym for
`
`“Random Access Memory”) is an addressable memory. The ’477
`
`patent identifies TLB 76 as “[a] high speed cache random access
`
`memory which can store for example 4,096 … thirty-two bit entries.”
`
`23:26-42. Similarly, the ’477 patent, in several locations discusses a
`
`“TLB entry” or the “TLB RAM entry.” See 24:10-29. The discussion
`
`of such entries indicates to one of skill in the art that the TLB includes
`
`multiple entries (as would be understood to be in a TLB by one of skill
`
`in the art) which are searched for the pending virtual-to-physical
`
`address translation and which can be addressed by the update
`
`mechanism to store the cached virtual-to-physical address translations.
`
`
`
`
`
`16
`
`ARM_VPT_IPR_00000435
`
`

`
`
`U.S. Patent No. 5,463,750
`Petition for Inter Partes Review, Declaration of V. Thomas Rhyne, Ph. D
`
`
`
`
`
`34. The instruction pipelines (the “integer processors”) in the ’477 patent
`
`all receive their instructions from a common instruction issuing unit. In
`
`the Background of the Invention, the ’477 patent indicates that the
`
`system described therein “provides for parallel processing a very long
`
`instruction word having a length of, for example, 1000 or more bits….”
`
`1:28-33. This indicates that the different integer processors are separate
`
`pipelines working on different instructions (or portions of the larger
`
`1000-bit instruction) received from the same instruction unit.
`
`35. The ’477 system describes a “four cluster” system. “This is referred to,
`
`in the illustrated embodiment, as a “four-wide system” representing the
`
`four clusters which each have an integer processor. See 5:59-65. The
`
`’477 then continues on to describe how the 1024-bit instruction “very
`
`long” words for the four-wide system can be reduced proportionately
`
`for one-wide and two-wide systems to 256 and 512 bits respectively.
`
`See 6:4-23. Thus, each integer processor would receive 256 bits of the
`
`wide instruction word and the integer processors would all receive the
`
`instructions from the same instruction issuing unit.
`
`36. The ’477 patent both depicts and discusses a single “ITLB” which is the
`
`TLB used for fetching instructions. See Figure 1, Element 40; 4:57-5:4;
`
`and 17:35-65. Moreover, a single program counter is used for fetching
`17
`
`
`
`ARM_VPT_IPR_00000436
`
`

`
`
`U.S. Patent No. 5,463,750
`Petition for Inter Partes Review, Declaration of V. Thomas Rhyne, Ph. D
`
`
`
`
`
`instructions for all of the clusters. See 15:30-60 and 16:38-68. These
`
`portions of the ’477 patent indicate to one of skill in the art that the
`
`“integer processors” all receive their instructions (in the case of the
`
`preferred embodiment, their portion of the overall 1024-bit instruction)
`
`from a common instruction issuing unit.
`
`V. U.S. PATENT NO. 4,933,835
`
`37. I have also reviewed the ’835 patent. I agree with the statements the
`
`applicant made during the prosecution of the ’750 patent that the ’835
`
`patent describes TLB technology that was well known by the filing date
`
`of the ’750 patent. See the Amendment dated 9/24/94 at pp. 1-2)
`
`(“address translators are well known and may be constructed in
`
`accordance with [the ’835 patent]”).
`
`38. I have reviewed the claim charts showing the correspondence between
`
`the ’835 patent reference and certain elements of claim 8 of the ’750
`
`patent which are within the Request for inter partes Review to which
`
`this Declaration is attached. I agree that as explained in those claim
`
`charts, the ’835 patent discloses those corresponding elements of those
`
`claims to one of skill in the art.
`
`
`
`18
`
`ARM_VPT_IPR_00000437
`
`

`
`
`
`
`U.S. Patent No. 5,463,750
`Petition for Inter Partes Review, Declaration of V. Thomas Rhyne, Ph. D
`
`
`
`VI. COLWELL
`
`39. I also have reviewed the claim charts showing the correspondence
`
`between Colwell and certain elements of claim 8 of the ’750 patent
`
`which are located in the Request for inter partes Review to which this
`
`Declaration is attached. I agree that those charts show that Colwell
`
`discloses those corresponding elements of those claims to one of skill in
`
`the art.
`
`40. Colwell appears to describe a preferred embodiment of the ’477 patent.
`
`It uses much of the same terminology and was written by the inventors
`
`of the ’477 patent. It also appears to reference the same underlying
`
`computer design (the “Trace”) as is referenced in the ’477 patent.
`
`Thus, one of skill in the art would have readily combined the teachings
`
`of the ‘477 and Colwell as they appear to describe the same system.
`
`VII. COMBINING THE ‘835 PATENT WITH EITHER THE VAX 8800
`OR THE ‘477 PATENT IN COMBINATION WITH COLWELL
`
`41. In my opinion, one of skill in the art would readily combine the
`
`teachings of the ’835 patent with either the VAX 8800 reference or the
`
`’477 patent.
`
`42. During the course of the prosecution of the ’750 patent, the examiner
`
`rejected the pending claims and noted that “[i]t would have been
`
`
`
`19
`
`ARM_VPT_IPR_00000438
`
`

`
`
`U.S. Patent No. 5,463,750
`Petition for Inter Partes Review, Declaration of V. Thomas Rhyne, Ph. D
`
`
`
`obvious to a person of ordinary skill in the art at the time the invention
`
`was made that employing plural units of identical function to assist
`
`plural function is commonly practiced, and the person would have
`
`employed separate TLB's for each pipeline to assist in address
`
`translation.” See the Office Action dated 7/28/94 at p. 4. I agree with
`
`the examiner’s statement that employing plural units of identical
`
`function (“parallelism”) to assist with the performance of plural
`
`functions was commonly practiced as of the date of the ’750 patent
`
`application. Moreover, one of skill in the art would have understood
`
`that separate TLB’s could be used in each instruction pipeline to assist
`
`in address translation when an architecture provided multiple
`
`instruction pipelines.
`
`43. The VAX 8800 and the ’477 patent provide good examples of using
`
`“plural units of identical function to assist plural function” by their use
`
`of separate TLB’s in each pipeline as discussed in the Requests for inter
`
`partes Review to which my Declaration is attached. As noted by the
`
`examiner, this was common practice at the time of the invention.
`
`44. United States Pat. No. 3,947,823 also provides another good example of
`
`the use of multiple pipelined processors, each containing their own
`
`TLB. The ’823 patent discloses multiple CPU’s where “[e]ach CPU
`20
`
`
`
`
`
`ARM_VPT_IPR_00000439
`
`

`
`
`U.S. Patent No. 5,463,750
`Petition for Inter Partes Review, Declaration of V. Thomas Rhyne, Ph. D
`
`
`
`includes … a dynamic address translation mechanism (DATM) which
`
`includes a translation lookaside buffer (TLB).” 2:57-64. Using separate
`
`TLB’s in separate instruction processing pipelines merely reflects the
`
`common, long-used, practice of replicating identical units of identical
`
`function within a parallelized computing system.
`
`45. As noted above, the technology for TLB’s and the structure and
`
`operation of TLB’s were known for at least 20 years before the filing of
`
`the ’750 patent. While different companies used different names for the
`
`functionality of the TLB’s, the basic functionality of those TLB’s was
`
`essentially the same. The TLB’s were used to translate virtual
`
`addresses into physical addresses. In a virtual-memory system this
`
`translation was performed by searching through a virtual-to-physical
`
`translation table which matched the virtual addresses to physical
`
`addresses. When an entry was located that matched the virtual address,
`
`then the physical address was read from that entry of the table. TLB’s
`
`merely employed one long-known computer idea (using small “cache”
`
`memories to speed access to particular data elements) to store portions
`
`of the translation table. While minor variations may exist between
`
`different virtual memory systems (e.g., the number of bits used to store
`
`the virtual and physical addresses, or the techniques used to search the
`21
`
`
`
`
`
`ARM_VPT_IPR_00000440
`
`

`
`
`U.S. Patent No. 5,463,750
`Petition for Inter Partes Review, Declaration of V. Thomas Rhyne, Ph. D
`
`
`
`table), the basic operations of TLB’s involved a finite number of
`
`identified, predictable solutions known long before the filing of
`
`the ’750 patent. The claims of the ’750 patent merely recite well-
`
`known structures which were used to perform the translation of virtual
`
`addresses to physical addresses and to update the translation cache
`
`known as the TLB.
`
`46. To the extent that the VAX 8800 alone did not disclose all of the
`
`structural elements of the TLB’s recited in the claims of the ’750 patent,
`
`one of skill in the art would have readily considered, and substituted,
`
`the structural details of the TLB described in the ’835 patent for the
`
`“translation buffer” (“TB”) used and discussed in the VAX 8800
`
`reference. The VAX 8800 reference merely reflects the common
`
`functionality of TLB’s and does not require any particular functionality
`
`of the “TB” outside of that which was known in the prior art. A person
`
`skilled in the art in 1993 would have understood that the basic structure
`
`for the TLB disclosed in the ’835 patent could readily have been
`
`adapted to the VAX 8800. The substitution of the TLB’s disclosed in
`
`the ’835 patent for the “TB’s” disclosed in the VAX 8800 would have
`
`been obvious to one of skill in the art and could readily be
`
`implemented. One would have been motivated to make such a solution
`22
`
`
`
`
`
`ARM_VPT_IPR_00000441
`
`

`
`
`U.S. Patent No. 5,463,750
`Petition for Inter Partes Review, Declaration of V. Thomas Rhyne, Ph. D
`
`
`
`by the very small number of different solutions known and used to
`
`solve this problem which had been solved for 20+ years before the ’750
`
`patent.
`
`47. While the specific algorithm for translating virtual addresses to physical
`
`addresses might be different between the ’835 patent and the VAX
`
`8800 (meaning, the specific manipulation of bits used to calculate the
`
`correspondence between virtual and physical addresses), the claims of
`
`the ’750 patent do not pertain to this difference. Rather those claims
`
`pertain to a specific higher-level architecture and the basic process of
`
`checking the TLB for a TLB “hit,” searching the page table for a TLB
`
`“miss,” and updating the TLB cache memory as part of the TLB “miss”
`
`processing. The ’835 patent and the VAX 8800 reference disclose
`
`those same basic processes, and the structure used to perform these
`
`processes would have been known by one of skill in the art to be
`
`interchangeable.
`
`48. To the extent that the disclosure of the different execution units in the
`
`VAX 8800 does not meet the construction of the term “instruction
`
`pipeline,” it would have been obvious to apply the teachings of the
`
`VAX 8800 to separate “instruction pipelines.” The point of using
`
`separate TLB’s in the VAX 8800 execution units was to permit each
`23
`
`
`
`
`
`ARM_VPT_IPR_00000442
`
`

`
`
`U.S. Patent No. 5,463,750
`Petition for Inter Partes Review, Declaration of V. Thomas Rhyne, Ph. D
`
`
`
`execution path to operate independently and efficiently with respect to
`
`the addressing of virtual memory. Such an approach of using a
`
`plurality of known, commonly used functional blocks for known
`
`functions in different portions of a computer architecture would have
`
`been obvious to one of skill in the art by November 1993.
`
`49. To the extent that the ’477 patent in combination with Colwell does not
`
`disclose all of the structural elements of the TLB’s recited in the claims
`
`of the ’750 patent, one of skill in the art would have readily considered,
`
`and substituted, the TLB described in the ’835 patent for “TLB 76” as
`
`disclosed and discussed in the ’477 patent and the TLB disclosed in
`
`Colwell. The ’477 patent merely reflects the common function

This document is available on Docket Alarm but you must sign up to view it.


Or .

Accessing this document will incur an additional charge of $.

After purchase, you can access this document again without charge.

Accept $ Charge
throbber

Still Working On It

This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.

Give it another minute or two to complete, and then try the refresh button.

throbber

A few More Minutes ... Still Working

It can take up to 5 minutes for us to download a document if the court servers are running slowly.

Thank you for your continued patience.

This document could not be displayed.

We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.

Your account does not support viewing this document.

You need a Paid Account to view this document. Click here to change your account type.

Your account does not support viewing this document.

Set your membership status to view this document.

With a Docket Alarm membership, you'll get a whole lot more, including:

  • Up-to-date information for this case.
  • Email alerts whenever there is an update.
  • Full text search for other cases.
  • Get email alerts whenever a new case matches your search.

Become a Member

One Moment Please

The filing “” is large (MB) and is being downloaded.

Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.

Your document is on its way!

If you do not receive the document in five minutes, contact support at support@docketalarm.com.

Sealed Document

We are unable to display this document, it may be under a court ordered seal.

If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.


Access Government Site

We are redirecting you
to a mobile optimized page.





Document Unreadable or Corrupt

Refresh this Document
Go to the Docket

We are unable to display this document.

Refresh this Document
Go to the Docket