FILE HISTORY
`US 5,463,750
`
`5,463,750
`PATENT:
`INVENTORS: Sachs, Howard G.
`
`TITLE:
`
`Method and apparatus for translating virtual
`addresses in a data processing system
`having multiple instruction pipelines and
`separate TLB's
`
`APPLICATION
`NO:
`FILED:
`ISSUED:
`
`US1993146818A
`
`02 NOV 1993
`31 OCT 1995
`
`COMPILED:
`
`11 NOV 2013
`
`ARM_VPT_IPR_00000247
`
`ARM Ex. 1008
`IPR Petition - USP 5,463,750
`
`

`

`
`
` ,5UECLASSIFICATION
`
` SERIAL nuraaee'.
`08/ 1 46, 813
`
` gHowARo e. SACHs, HELvEDERE, CA.
`
`
`
`41.421;
`
`**CDNTINUINEIDRTA**1$**$**t**t*t*$$$¢*
`VERIFIED
`
`3 -
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`*rFOREIoN/PCT APPLICATIONS************
`VERIFIED
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`
`
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`goon-rev DRWGS. gums
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` A'r'roaoiEv's
`TOTAL. moss.
`.FILING FEE
`DOCKET no;
`cmrus
`RECEIVED
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`
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`'
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`FOREIGN FILING LICENSE GRQNTED 12/09/93.
`
`sTATE on SHEET
`Foreign priority claimed
`i we
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`[ii/no
`as use no condition: not
`[I] you
`
`
`Verrrmanu Acknowlodud
`no “It as
`
`
`ROBERT C. COLWELL
`TOWNSEND & TOWNSEND KHUURIE Awe CREW
`
`ONE MARKET PLAZA
`STEUART STREET TONER, 2UTH.FLDUR
`
`SAN FRANCISCO CA 94105
`
`
`ETHOD 9ND QPF’PIRGTLIS FEIR TRANSLATING VIRTUAL ADDRESSES IN 9
`,3. PROCESSING magi/grammeMU TIPLE IN'STRIJCTIUN PIPELINES WM
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`7A3“; #44”
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`:‘AHTSOFAPPUCAHON
`LEDSEPARATELY
`
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`-_ NOTICE OF ALLOWANCE MAILED
`
`ed Unauthorized disclosure may be prohibited
`WARHIHG: The information disclosed herein rosy be res
`
`
`by the Uniled States Code Title 35 Secti- ~ 122 131 and 368. Possession outside the U S 1
`Patent a Trademark OfficeIs restricted . authorized employees and contractors only.
`
`ARM_VPT_IPR_00000248
` VPT_IPR_00000248
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`'
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`_
`
`(FACE)
`
` Assistant Examiner Tolai Claims
`Figs Drwg.o
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`/ fl
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`DRAWING
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`SheetsA.Drwg
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`

`5,463,750
`
`METHOD AND APPARATUS FOR TRANSLATING VIRTUAL
`
`ADDRESSES IN A DATA PROCESSING SYSTEM HAVING MULTIPLE
`
`INSTRUCTION PIPELINES AND SEPARATE TLB'S FOR EACH
`
`PIPELINE
`
`Transaction History
`
`
`Transaction Description
`Date
`
`'1213-1993 Application Captured on Microfilm
`
`12-23-1 993 Case Docketed to Exarniner1n GAU
`
`07—22-1994 Nn-F1nal Rejection
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`07-28-1994 Mail Non-Final Rejection
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`
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`03-06-1995 :
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`
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`03-30-1995
`'Datc Forwarded to Examiner
`
`
` Mail Notice of Allowance
`05-03—1995
`
`
`
`053995-0-1
`I: Not1ce of Allowance Data Ver1cat1onCompleted
`I
`
`
`
`
`
`
`03-04—1995
`_...._..__
`_...-
`_....1
`Issue Fee Payment Verified
`
`
` —__ Ia_..-.—_._..-..n__. 13—...
`
`
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`09-25-1995 Issue Notification Mailed
`
`
`
`
`Recordation of Patent Grant Mailed .
`
`ARM_VPT_IPR_00000249
`ARM_VPT_IPR_00000249
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`

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`ARM_VPT_IPR_00000250
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`PT_IPR_00000250
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`'
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`

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`ARM_VPT_IPR_00000251
`ARM_VPT_IPR_00000251
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`Staple Issue Slip Here .
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`'m'
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`POSITION
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`CLASSIFIER
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`VERIFIER
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`m-__
`_———_
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`INDEX OF CLAIMS
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`ARM_VPT_IPR_00000252
`RM_VRT IPR 00000252
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`(LEFT INSIDE)
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`ARM_VPT_IPR_00000253
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`(RIGHT OUTSIDE}
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`

`

`KENNETH S. KIM
`
`05-04-95
`
`01:57pm _ Text Search.1ranscript
`
`"
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`Page
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`:2» Id his
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`{FILE ’USPAI’ ENTERED AT 12:52:02 ON 04 MAY 95)
`SET PAGELENGTH 62
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`1310 s mun (1A) ADDRESSM‘
`205 S (MAIN 0R MASTER)
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`533 S TLB 0R DAT 0'! MB '
`62 5 (L1 0R L4)-N~EJ-(L2 0R L3)
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`SET HIG-ILIGHTI OFF
`2100 S (L1 0R L4)
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`SET __HIGI-ILIG-[1' ON
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`44 s (MAIN 0R mm) (20') L6
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`1'6 3 L7 AND L8
`93568 s (PLURAL? 0R MULTIP? 0R SECOND)
`105 3 L7 AND L10
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`ARM_VPT_IPR_00000254
`_ ARM_YPT_IPR_00000254
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`- KENNETH S. KIM
`
`05—04-95
`
`01:17pm
`
`Text Search Transcript
`
`Page
`
`=> d 1-16 ti
`
`US PAT N0:
`.TITLE:
`
`1 of 16
`L9:
`5,390,309 [IMAGE AVAILABLE]
`Virtual address translation in three level yirtual machine
`
`as PAT N0:
`TITLE:
`
`L9: 2 of 16
`5,386,530 [IMAGE AVAILABLE]
`Address translation device capable of obtaining a real address
`from a virtual address in a shorter time
`
`US PAT NO:
`TITLE:
`
`L9: 3 of 16
`5,325,507 [IMAGE AVAILABLE]
`Translation lookaside buffer_shutdown scheme
`
`us PAT NO:
`TITLE:
`
`us PAT N0:
`TITLE:
`.
`
`L9: 4 0501.6
`5, 282,274 [IMAGE AVAILABLE)
`Translation of multiple virtual pages upon a.TLB“miss
`
`19: 5 of 15
`‘
`-- 5,255,324 [IMAGE AVAILABLE]
`Memory address translation system having modifiable and
`non—modifiable translation mechanisms
`
`US PAT N0:
`' TITLE:
`
`L9: 6 of 16
`3
`-
`5,237,671 [IMAGE AVAILABLE]
`Translation lookaside buffer shutdown scheme
`
`us PAT no;
`TITLE:
`
`US PAT NO:
`TITLE:
`
`L9: 7 of 16
`5,091,846 [IMAGE AVAILABLE]
`Cache providing caching/non-caching write-through and copyback
`modes for virtual addresses and including bus snooping to
`maintain coherency
`'
`
`8 of 16
`L9:
`5,023,777 [IMAGE AVAILABLE]
`Information processing system using domain table address
`extension for address translation without software
`modification
`
`US PAT N0:
`TITLE:
`
`L9: 9 of 16
`_
`4,992,936 [IMAGE AVAILABLE]
`Address translation method and apparatus therefor
`
`US PAT NO:
`TITLE:
`
`'
`
`L9: 10 of 16
`4,980,816 [IMAGE AVAILABLE]
`Translation look—aside buffer control system with multiple
`prioritized buffers
`
`US PAT N0:
`TITLE:
`
`L9: 11 of 16
`-
`4,933,835 [IMAGE AVAILABLE]
`Apparatus for maintaining consistency of a cache memory with a
`primary memory
`
`US PAT N0:
`TITLE:
`
`4,899,275 [IMAGE AVAILABLE]
`Cache-MMU system
`'
`
`L9: 12 of 16
`
`US PAT N0:
`TITLE:
`
`L9: 13 of 16
`4,884,197 [IMAGE AVAILABLEJ
`Method and apparatus for addressing a cache memory
`
`US PAT No:
`_TITLE:
`
`4,860,192 [IMAGE AVAILABLE]
`Quadword boundary cache system
`
`-
`
`L9: 14 of 16
`
`I
`
`_4,779,188 [IMAGE AVAILABLE]
`US PAT N0:
`Selective guest system purge control
`TITLE:
`13:17:21 COPY AND CLEAR PAGE, PLEASE
`.
`04 MAY 95 13:17:31
`U.S. Patent & Trademark Office
`
`L9: 15 of 16
`
`P0011
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`ARM_VPT_IPR_00000255
`ARM_VPT_IPR_00000255
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`

`

`mm s. KIM
`
`05—04—95
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`01:17pm
`
`Text Search éranscript
`
`Page
`
`2
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`US PAT NO:
`TITLE:
`
`L9: 16 of 16
`4,179,039 {IMAGE AVAlLABLEJ
`Virt'iml address translation speed up technique
`
`=>
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`
`
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`ARM_VPT_IPR_00000256
`ARM_VPT_IPR_00000256
`
`

`

`KENNETH S. KIM
`
`.1) d 1-20 ti.
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`US PAT NO:
`TITLE:
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`US PAT NO:
`TITLE:
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`US PAT N0:
`TITLE:
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`US PAT N0:
`TITLE:
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`US PAT N0:
`TITLE:
`'
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`US PAT NO:
`TITLE:
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`US PAT N0:
`TITLE:
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`US PAT N0:
`TITLE:
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`05—04-95
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`01:37pm
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`Text Search Iranscript
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`.
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`Page
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`1 of 20
`L12:
`5,392,409 [IMAGE AVAILABLE]
`[/0 execution method for a virtual machine system and system
`therefor
`
`L12: 2 of 20
`5,390,309 [IMAGE AVAILABLE]
`Virtual address translation in three level virtual machine
`
`L12: 3 of 20
`-
`5,386,530 [IMAGE AVAILABLE]
`Address translation device capable of obtaining a real address
`from a virtual address in a shorter time
`
`L12: 4 of 20
`5,367,686 [IMAGE AVAILABLE]
`Method for automated complex multilevel softward ifistallation
`in a data processing system
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`L12: 5 of 20
`_
`5,363,502 [IMAGE AVAILABLE]
`Hot stand-by method and computer system for implementing hot
`stand—by method
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`L12: 6 of 20
`_
`5,325,507 [IMAGE AVAILABLE]
`Translation lookaside buffer shutdown.scheme
`
`L12: 7 of 20
`5,255,384 [IMAGE AVAILABLE]
`Memory address translation system having modifiable and
`non—modifiable translation mechanisms
`
`L12: 3 of 20
`5,237,671 [IMAGE AVAILABLE]
`Translation loohaside buffer shutdown scheme,
`
`"
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`US PAT NO:
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`5,134,698 [IMAGE AVAILABLE]
`13:37:24 COPY AND CLEAR PAGE, PLEASE
`04 MAY 95 13:37:33
`U.S. Patent & Trademark_0ffice
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`L12: 9 of 20
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`_
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`P0015
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`US PAT N0:
`TITLE:
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`US PAT N0:
`TITLE:
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`US PAT N0:
`TITLE:
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`US PAT N0:
`TITLE:
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`US PAT N0:-
`TITLE:
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`US PAT N0:
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`L12: 9 of 20
`5,134,698 [IMAGE AVAILABLE]
`Data processing system having a storage controller for
`transferring an arbitrary amount of data at an arbitrary
`address boundary between storages
`
`L12: 10 of 20
`5,109,489 [IMAGE AVAILABLE]
`1/0 execution method for a virtual machine system and system
`therefor
`
`L12: 11 of 20
`5,091,846 [IMAGE AVAILABLE]
`cache providing caching/non—caching write-through and copyback
`modes for virtual addresses and including bus snooping to
`maintain coherency
`-’
`
`L12: 12 of 20
`4,933,835 [IMAGE AVAILABLE]
`Apparatus for maintaining consistency of a cache memory with a
`primary memory
`
`_
`
`4,899,275 [IMAGE AVAILABLE]
`Cache-MMU system
`
`L12: 13 of 20
`
`4,384,197 [IMAGE AVAILABLE]
`
`L12: 14 of 20
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`
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`
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`ARM_VPT_IPR_00000257
`ARM_VPT_IPR_00000257
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`

`

`KENNETH S.
`
`KIM
`
`05-04-95
`
`01:37pm [Text Search -ranscript
`
`Page
`
`2 .
`
`TITLE:
`
`US PAT NO:
`TITLE:
`
`US PAT N0:
`TITLE:
`'
`
`US PAT NO:
`TITLE:
`
`US PAT NO:
`TITLE:
`
`US PAT NO:
`TITLE:
`
`US PAT NO:
`TITLE:
`
`=>
`
`Method and apparatus for addressing a cache memory
`
`.4,860,192 [IMAGE AVAILABLEJ
`Quadword boundary cache system
`
`L12: 15 of 20
`
`L12: 16 of 20,
`_
`4,831,515 [IMAGE AVAILABLE]
`Information processing apparatus for determining sequence of
`parallel executing instructions in response to storage
`requirements thereof
`
`L12: 1? of 20
`.
`4,714,653 [IMAGE AVAILABLE]
`Hybrid-hardware/software method and apparatus For virtual
`memory address translatidn using primary and secondary
`translation buffers
`
`is of 20
`L12:
`_4,747,044 [IMAGE AVAILABLE]
`Direct execution of software on microprogrammable hardware
`
`L12: 19 of 20
`4,332,010 [IMAGE AVAILABLE]
`Cache synonym detection and handling-mechanism
`
`3,764,996 [IMAGE AVAILABLE]
`STORAGE CONTROL AND ADDRESS TRANSLATION
`
`L12: 20 of 20
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`
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`ARM_VPT_IPR_00000258
`ARM_VPT_IPR_00000258
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`

`
`
`KENNETH S. KIM
`
`05-04495
`
`01:39pm
`
`Text Search .ranscript
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`Page
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`1
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`=> d 111 1—105 ti
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`us PAT N0:
`TITLE:
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`US PAT N0:
`TITLE:
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`5, "412, 737 [111001; AVAILABLE]
`_
`“level TLB having_ the
`
`cache tag RAMs
`-
`
`1 .01 105
`L11:
`level'TLB implemented in
`'
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`L11: 2 of 105
`.
`I
`5, 404, 478 [IMAGE AVAILABLE]
`Method of managing a virtual storage for a multi-processor
`system
`
`5,401,476 {IMAGE AVAILABLE]
`US PAT No:
`13:37:55 COPY AND CLEAR PAGE, PLEASE
`04 MAY 95 13:38:08
`.H
`U.S. Patent G Trademark Office
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`L11: 3 of 105
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`__
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`P0016
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`us PAT No:
`TITLE:
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`US PAT Np:
`TITLE:
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`L11: 3 of 105
`'
`5,400,476 [IMAGE AVAILABLE]
`'Multiprocessing system having a single translation lookaside
`buffer with reduced processor overhead'
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`L11: 4 of 105
`_
`5,404,467 [IMAGE AVAILABLE]
`CPU having pipelined instruction unit and effective address
`calculation unit with retained virtual address capability
`
`US PAT N0:_
`TITLE:
`‘
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`L11: 5 of 105
`5,394,545 [IMAGE AVAILABLE]
`System for determination and display of memory used,
`dedicated, and shared by a process at a particular time
`
`US PAT NO:
`TITLE:
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`5,390,312 [IMAGE AVAILABLE]
`Access look—aside facility
`
`L11: 6 of 105
`-
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`US PAT N0:
`TITLE:
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`L11: 7 of 105
`5,390,309 [IMAGE AVAILABLE]
`Virtual address translation in three level virtual machine
`
`us PAT N0:
`TITLE:
`
`L11: 3 of 105
`I
`'
`I5,386,533 [IMAGE AVAILABLE]
`High performance sort hardware accelerator in a data
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`m system including a
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`mo u es
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`1
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`_
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`of comparator
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`'
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`-
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`US PAT NO:
`TITLE:
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`L11: 9 of 105
`.
`5,386,530 [IMAGE AVAILABLE]
`Address translation device capable of obtaining a real address
`from a virtual address in a shorter time
`
`'
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`US PAT N0:
`TITLE:
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`US PAT N0:
`TITLE:
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`US PAT N0:
`TITLE:
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`5,381,535 [IMAGE AVAILABLE]
`_
`L111 10 of 105
`DataM control of Nievel quest virtual.
`_ mac 1nes wit out host intervention
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`_
`
`L11: 11 of 105
`5, 375, 214 [IMAGE AVAILABLE]
`Single translation mechanism for virtual storage dynamic
`address translation with non-uniform page sizes
`5,369,744 [IMAGE AVAILABLE]
`I
`L11: 12 of 105
`Addressmtranslatable graphic processor, data processor and
`_drawing method with employment of the same
`
`US PAT N0:
`TITLE:
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`5,367,660 [IMAGE AVAILABLEJ'
`Line buffer for cache memory
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`L11: 13 of 105
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`-
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`us PAT N0:
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`5,349,678.!IMAGE AVAILABLE]
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`L11: 14 of 105
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`ARM_VPT_IPR_00000259
`ARM_VPT;_IPR_00000259
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`

`

`
`
`KENNETH S. KIM
`
`05-04195
`
`01:39pm
`
`Text Search Transcript
`
`Page
`
`TITLE:
`
`Versatile RF data capture system
`
`US PAT N0:
`TITLE:
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`L11: 15 of 105'
`'
`5,349,652 [IMAGE AVAILABLE]
`Single chip integrated address manager with address
`translating unit
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`US PAT N0:
`TITLE:
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`1 L11: 16 of 105
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`5,341,485 [IMAGE AVAILABLE]
`virtual address translation per computer cycle
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`US PAT N0:
`TITLE:
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`'L11: 17 of 105
`_
`5,325,507 [IMAGE AVAILABLE]
`Translation lookaside buffer shutdown scheme -
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`5,319,758 [IMAGE AVAILABLE]
`US PAT N0:
`13:33:11 COPY AND CLEAR PAGE, PLEASE
`04 MAY 95 13:38:17
`U.S. Patent & Trademark Office
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`L11: 18 of 105
`'*5
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`P0017
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`US PAT N0:
`TITLE:
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`L11:‘18 of 105
`5, 319, 758 [IMAGE AVAILABLE]
`Method for managing multiple virtual storages divided into
`families
`-
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`US PAT N0:
`TITLE:
`
`_
`.L11: 19 of 105
`5,317,754 [IMAGE AVAILABLE]
`Method and apparatus for enabling an interpretive execution
`subset
`'
`'
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`US PAT N0:,
`TITLE:
`'
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`US PAT N0:
`TITLE:-
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`US PAT N0:
`TITLE:
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`L11: 20 of 105
`5,317,705 [IMAGE AVAILABLE]
`Apparatus and method for TLB purge reduction in a multi-level
`machine system
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`-
`5,301,304 [IMAGE AVAILABLE]
`Emulating records in one record format
`format
`‘
`
`L11: 21 of 105
`in another record
`
`'
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`L11: 22 of 105
`5,301,302 [IMAGE AVAILABLE]
`Memory mapping and special write detection in a system and
`method for simulating a CPU processor
`
`_
`'
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`a;
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`US PAT N0:
`TITLE:
`
`'
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`-
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`L11: 23 of 105
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`5, 299, 147 [IMAGE AVAILABLE]
`Decoder scheme for fully associative translation—lookaside
`buffer
`-
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`US PAT N0:
`TITLE:
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`US PAT N0:
`TITLE:
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`US PAT N0:
`TITLE:
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`US PAT N0:
`TITLE:
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`L11: 24 of 105
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`5,237,475 [IMAGE AVAILABLE]
`Data processing apparatus.operable in extended or unextended
`virtual address spaces sithout software modification
`
`L11: 25 of 105
`5, 274, 789 [IMAGE AVAILABLE]
`Multiprocessor system having distributed shared resources and
`dynamic and selective global_ data replication
`5, 265, 227 [IMAGE AVAILABLE]
`L11: 26 of 105
`Parallel protection checking in an address translation
`’look-aside buffer
`
`L11: 27 of 105
`5,255,384 [IMAGE AVAILABLE]
`Memory address translation system having modifiable and
`non-modifiable translation mechanisms
`
`us PAT no:
`
`5,247,513 [IMAGE AVAILABLE]
`
`L11: 2:: of 105
`
`ARM_VPT_IPR_00000260
`ARM_VPT_IPR_00000260'
`
`

`

`
`
`'KENNEIH s. KIM
`
`TITLE:
`
`US PAT N0:
`TITLE:
`I
`
`US PAT NO:
`TITLE:
`
`US PAT N0:
`TITLE:
`
`05-04-95 01:39pm Text Search 1ranscript
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`Page
`
`3
`
`Multiprocessor system having distributed shared resources and
`dynamic global data replication
`
`L11: 29 of 105'
`5,247,632 [IMAGE AVAILABLE]
`Virtual'memory management arrangement for addressing
`'multi-dimensional arrays in a digital data processing system
`
`L11: so of 105
`_
`5,247,629 [IMAGE AVAILABLE]
`Multiprocessor system with global data replication and
`levels of address translation units
`
`.
`
`L11: 31 of 105
`5,237,671 [IMAGE AVAILABLE]
`Translation lookaside buffer shutdown scheme
`
`US PAT N0:
`
`5,230,069 [IMAGE AVAILABLE]
`13:33:19 copy AND CLEAR PAGE, PLEASE
`U.S. Patent & Trademark Olfice
`04 MAY 95 13:33:31
`
`L11: 32 91,105
`
`P0018
`
`US PAT N0:
`TITLE:
`
`US PAT N0:
`TITLE:
`
`US PAT NO:
`TITLE:
`
`Us PAT N0:
`
`IITLE:
`
`US PAT N0:
`TITLE:
`
`US PAT N0:
`TITLE:
`
`US PAT NO:
`TITLE:
`
`US PAT NO:
`TITLE:
`
`US PAT N0:
`TITLE:
`
`US PAT N0:
`TITLE:
`
`L11: 32 of 105
`5,230,069 [IMAGE AVAILABLE]
`Apparatus and method for providing private and shared access
`to host address and data spaces by guest programs in a
`virtual machine Computer system
`
`L11: 33 of 105
`5,226,132 [IMAGE AVAILABLE]
`Multiple virtual addressing using/comparing translation pairs
`of addresses comprising a space address and an origin
`address (8T0) while using space registers as storage devices
`for a data processing system
`
`L11: 34 of'105
`5,224,063 [IMAGE AVAILABLE]
`Address translation in FFT numerical data processor
`
`L11: 35 of 105
`5,214,958 [IMAGE AVAILABLE]
`Misfiring detecting apparatus For an internal combustion
`
`device
`
`5,210,841 [IMAGE AVAILABLE]
`External memory accessing system
`
`L11: 36 of 105
`
`L11: 3? of 105
`5,204,949 [IMAGE AVAILABLE]
`Multi-channel/multi—circuit communication controller
`
`L11: 38 of 105
`5,197,139 [IMAGE AVAILABLE]
`Cache management For multi-processor systems utilizing bulk
`cross-invalidate
`-
`'
`
`L11: 39 of 105
`5,167,023 [IMAGE AVAILABLE]
`Translating a dynamic transfer control_instruction address in
`a simulated CPU processor
`
`L11: 40 of 105
`5,140,681 [IMAGE AVAILABLEJ
`Multi-processing system and cache_apparatus For use in the
`same
`
`'
`
`5,127,094 [IMAGE AVAILABLE]
`Virtual storage type computer system
`
`L11: 41 of 105
`
`ARM_VPT_IPR_00000261
`ARM_VPIT_IPR_00000261
`
`.\
`
`

`

`KENNETH s. KIM
`
`05—04-95
`
`01:39pm
`
`Text Search aranscript
`
`Page
`
`4
`
`US PAT N0:
`TITLE:
`
`US PAT N0:
`TITLE:
`
`US PAT N0:
`TITLE:
`
`US PAT NO:
`TITLE:
`
`L11: 42 of 105-
`5,123,101 [IMAGE AVAILABLEJ
`Multiple address space mapping technique for shared memory
`wherein a processor operates a fault handling routine upon a
`translator miss
`
`5,119,290 [IMAGE AVAILABLE}
`Alias address support
`
`L11: 43 of 105
`
`L11: 44 of 105
`5,117,350 [IMAGE AVAILABLE]
`Memory address mechanism in a distributed memory architecture
`
`L11: 45 of 105
`5,099,415 [IMAGE AVAILABLE]
`Guess mechanism for virtual address translation
`
`US PAT N0:
`TITLE:
`
`L11: 46 of 105
`”5,091,846 [IMAGE AVAILABLE}
`Cache providing caching/non—caching write~through and capyback
`modes for virtual addresses and including bus snooping to
`maintain coherency
`13:38:34 COPY AND CLEAR PAGE, PLEASE
`v.3. Patent a Trademark Office
`04 MAY 95 13:33:3T
`
`00019
`
`
`
`US PAT N0:
`TITLE:
`
`US PAT N0:
`TITLE:
`
`US PAT N0:
`TITLE:
`
`US PAT N0:
`TITLE:
`
`us PAT N0:
`TITLE:
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`US PAT N0:
`TITLE:
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`'US PAT N0:
`TITLE:'
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`US PAT N0:
`TITLE:
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`L11: 41 of 105
`5,003,462 [IMAGE AVAILABLE]
`Apparatus and method for implementing precise interrupts on a
`W with W functional units
`w t
`separate a
`ress trans at on interrupt means
`
`L11: 48 of_105
`4,999,770 {IMAGE AVAILABLE]
`Command controlled multi-storage space protection key
`pretesting system permitting access regardless of test
`result iF selected key is predetermined value
`
`4,991,090 [IMAGE AVAILABLE]
`Posting out-oF-sequence fetches
`
`L11: 49 of 105
`
`'
`
`L11: 50 of 105
`4,991,083 [IMAGE AVAILABLE]
`Method and system for extending address space For vector
`processing
`
`L11: 51 of 105
`_
`4,979,098 [IMAGE AVAILABLE]
`Multiple address space token designation, protection controls,
`designation translation and lookaside
`
`4,964,129.11MAGE AVAILABLE]
`Memory controller with error logging
`
`L11: 52 of 105
`
`L11: 53 of 105
`.
`4,945,480 [IMAGE AVAILABLE]
`Data domain switching on program address space switching and
`return
`
`L11: 54 of 105
`4,933,835 [IMAGE AVAILABLE]
`Apparatus for maintaining consistency of a cache memory with a
`primary memory
`
`US PAT NO:
`TITLE:
`
`4,399,275 [IMAGE AVAILABLE]
`Cache-MMU system
`
`L11: 55 of 105
`
`ARM_VPT_IPR_00000262
`ARM_VPT'_IPR_00000262
`
`W
`
`

`

`
`
`IKENNETH s. KIM
`
`05-04-95
`
`01:59pm
`
`Text Search -ranscript
`
`Page
`
`,5
`
`us PAT N0:
`TITLE:
`
`US PAT N0:
`TITLE:
`
`US PAT N0:
`TITLE:
`
`US PAT N0:
`TITLE:
`
`US PAT N0:
`TITLE:
`
`L11: 56 OF 105
`4,890,220 [IMAGE AVAILABLE!
`Vector processing apparatus for incrementing indices of vector
`operands of.different length according to arithmetic
`Operation results
`'
`
`L11: 5? of 105
`4,884,197 [IMAGE AVAILABLE].
`Method and apparatus for addressing a_cache memory
`
`L11: 58 of 105
`4,363,738 {IMAGE AVAILABLE]
`Operating system independent virtual memory computer system
`
`4,860,192 [IMAGE AVAILABLE]
`_1Quadword boundary cache system
`
`L11: 59 o_f_
`
`.105
`
`"'4, 853,840 [IMAGE AVAILABLE]
`Instruction prefetching device including a circuit for
`checking prediction of a branch instruction before the
`instruction is executed
`
`L11: 60 of 105
`
`US PAT N0:
`TITLE:
`
`L11: 61 of 105
`4,843,541 [IMAGE AVAILABLE]
`Logical resource partitibning oF a data processing system
`
`
`
`US PAT N0:
`
`' 4,311,208 [macs AVAILABLE]
`13:38:40 COPY AND CLEAR PAGE, PLEASE
`04 MAY 95 13:38:44
`U.S. Patent 8 Trademark Office
`
`L11: 52 of 195
`
`P0020
`
`US PAT N0:
`TITLE:
`
`US PAT N0:
`
`TITLE:
`
`US PAT N0:
`TITLE:
`
`US PAT N0:
`TITLE:
`
`US PAT N0:
`TITLE:
`
`US PAT N0:
`TITLE:
`
`US PAT NO:
`TITLE:
`
`us PAT N0:
`TITLE:
`
`US PAT N0:
`TITLE:
`
`L11: 62 of 105
`4,811,208 [IMAGE AVAILABLE]
`‘Stack frame cache on a microprocessor chip
`'
`
`4,802,084 [IMAGE AVAILABLE]
`Address translator
`
`L11: 63 of 105
`
`L11: 64 of 105
`4,192,395 [IMAGE AVAILABLE]
`Instruction processing in higher level virtual machines by a ~;
`real machine
`
`4,731,739 [IMAGE AVAILABLE]
`Eviction control apparatus
`
`_L11: 65 of 105
`
`4,694,395 [IMAGE AVAILABLE]
`System for performing virtual
`
`L11: 66 OF 105
`look—ahead memory operations
`
`L11: 6? of 105
`4,682,281 [IMAGE AVAILABLEI'
`Data storage unit employing translation lookaside buFfer
`pointer
`
`- L11: 68 of 105
`4,680,700 [IMAGE AVAILABLEI
`Virtual memory address translation mechanism with combined
`hash_address table and inverted page table
`
`L11: 69 of 105
`4,638,426 [IMAGE AVAILABLE]
`Virtual memory address translation mechanism with controlled
`data persistence
`
`4,618,926 [IMAGE AVAILABLE]
`Buffer storage control system
`
`L11: 70 of 105
`
`ARM_VPT_IPR_00000263
`ARM_VPT_IIPR_00000263
`
`
`
`

`

`' KENNETH s. KIM
`
`05-04—95
`
`01:39pm
`
`Text SearcL aranscript
`
`Page
`
`US PAT N0:
`TITLE:
`
`US PAT N0:
`TITLE:
`
`US PAT N0:
`TITLE:
`
`US PAT N0:
`TITLE:
`
`US PAT N0:
`TITLE:
`
`us PAT N6:
`TITLE:
`
`4,612,612 [IMAGE AVAILABLE]
`Virtually addressed cache
`
`L11: 71 of 105
`
`”L11: 72 of 105
`4,597,041 [IMAGE AVAILABLE]
`Method and apparatus for enhancing the operation of a data
`processing system
`
`' L11: 73 of 105
`4,594,537 [IMAGE AVAILABLE]
`Character oriented RAM mapping system and method therefor
`
`L11: 74 of 105
`4,577,274 [IMAGE AVAILABLE]
`Demand paging scheme-for a multi-ATB shared memory processing
`system
`‘
`
`L11: 75 of 105
`4,569,018 [IMAGE AVAILABLE]
`Digital data processing system having dual-purpose scratchpad
`and address translation memory
`
`. L11: 75 of 105
`4,539,531 [IMAGE AVAILABLE]
`Method and apparatus for handling interprocessor calls in a
`multiprocessor system _
`
`US PAT N0:
`TITLE:
`
`L11: 77 of 105
`4,525,780 [IMAGE AVAILABLE}
`Data processing system having a—memory using object-based
`information and-a protection scheme for determining access
`rights to such information
`13:38:48 COPY AND CLEAR PAGE, PLEASE
`U.S. Patent 8 Trademark Office
`04 MAY 95.13:38:51
`
`'
`
`P0021
`
`
`
`US PAT N0:
`TITLE:
`
`US PAT N0:
`TITLE:
`
`US PAT N0:
`TITLE:
`
`US PAT N0:
`TITLE:
`
`us PAT N0:
`TITLE:
`
`US PAT N0:
`TITLE:
`
`US PAT N0:
`TITLE:
`
`L11: 78 of 105
`4,521,848 [IMAGE AVAILABLE]
`Intersystem fault detection and bus cycle completion Iogic_
`system“
`.
`
`‘_
`
`L11: 79 of 195
`,
`4,500,952 [IMAGE AVAILABLE]
`Mechanism for control of address translation by a program
`using a plurality of translation tables
`
`'
`
`-1
`
`L11: so 01.105
`4,493,027 {IMAGE AVAILABLE]
`Method of performing a call operation in a digital data
`processing system having microcode call and return
`operations
`
`'
`
`L11: 81 of 105
`4,481,573 [IMAGE AVAILABLE]
`Shared virtual address translation unit for a multiprocessor
`system
`
`L11: 82 of 105
`4,456,954 [IMAGE AVAILABLE]
`Virtual machine system with guest architecture emulation using
`hardware '[LB’s for
`level address translations
`
`L11: 83 of 105
`4,455,602 [IMAGE AVAILABLE]
`Digital data processing system having an 1/0 means using
`unique address providing and access priority control
`-techniques
`
`'L11: 84 of 105
`4,445,177 [IMAGE AVAILABLE]
`Digital data processing system utilizing a unique arithmetic
`
`ARM_VPT_IPR_00000264
`ARM_VPT_IPR_00000264
`
`
`
`
`
`

`

`-KENNETH S. KIM
`
`05-04-95
`
`01:39pm
`
`Text Search Iranscript
`
`Page
`
`7_
`
`logic unit for handling uniquely identifiable addresses for
`operands and instructions
`
`us PAT no:
`TITLE:
`
`US PAT N0:
`TITLE:
`
`US PAT N0:
`TITLE:
`
`4,433,376 [IMAGE AVAILABLE]
`Intersystem translation logic system
`
`L11: 85 of 105
`
`L11: 86 of 105
`4,430,705 [IMAGE AMAILABLE]
`Authorization mechanism for establishing addressahility to
`information in another address space
`
`' L11: 87 of 105
`l
`I
`4,386,402 [IMAGE AVAILABLE]
`Computer with dual vat buffers for accessing a common memory
`shared by a cache and a processOr interrupt stack
`
`US PAT N0:
`TITLE:
`
`4,384,327 [IMAGE AVAILABLE]
`Intersystem cycle control
`logic
`
`L11: 88 of 105
`:1:'
`
`US PAT N0:
`TITLE:
`
`“Lll: 89 of 105
`-=4,384,322 [IMAGE AVAILABLE]
`Asynchronous multi-communication bus sequence
`
`US PAT No:
`TITLE:
`5
`
`US PAT N0:
`TITLE:
`'
`
`4,376,297 [IMAGE AVAILABLE]
`Virtual memory addressing'device
`
`L11: 90 of 105
`
`L11: 91 of 105
`I
`4,370,708 [IMAGE AVAILABLE]
`Logic system For selectively reconfiguring an intersystem
`communication link
`'
`
`4,366,537 [IMAGE AVAILABLE]
`US PAT N0:
`13:38:55 COPY AND CLEAR PAGE, PLEASE
`04 MAY 95 13:38:57
`U.S. Patent 8 Trademark Office
`
`'L11: 92 of 105
`
`.
`
`P0022
`
`us PAT N0:
`TITLE:'
`
`L11: 92 of 105_'
`'
`4,366,537 [IMAGE AVAILABLE]
`Authorization mechanism for transfer of program control or
`data between different address spaces having different
`_
`.storage protect keys
`
`US PAT N0:
`TITLE:
`
`4,282,584 [IMAGE AVAILABLE]
`Mini-programmable controller
`
`L11: 93 of 105
`
`
`
`L11: 94 of 105
`-
`4,236,209 [IMAGE AVAILABLE]
`Intersystem transaction identification logic
`
`US PAT No:
`TITLE:
`
`us PAT no:
`TITLE:
`
`4,236,208 [IMAGE AVAILABLE]
`Test mode control
`logic system
`
`US PAT N0:
`,TITLE:
`
`4,234,919 [IMAGE AVAILABLE]
`Intersystem communication link
`
`L11: 95 of 105
`
`-L11: 96 of.105
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`us PAT N0:
`TITLE:
`
`US PAT N0:
`TITLE:
`
`US PAT NO:
`TITLE:
`
`. 4,231,086 [IMAGE AVAILABLE]
`Multiple CPU control system '
`
`,1.
`
`L11: 9? of 105
`_
`
`4,149,242 [IMAGE AVAILABLE].
`Data interface-apparatus for
`
`L11: 98 of 105
`1
`
`iI‘CICessm‘s
`sequential
`
`L11: 99 of 105
`4,145,738 {IMAGE AVAILABLE]
`virtual address space processing 'system
`
`
`ARM_VPT_IPR_00000265
`
` ARM_VPT_IPR_00000265
`
`

`

`KENNETH s. KIM
`
`05-04-95 01:39pm Text SearcL.1?anscript
`
`Page
`
`3
`
`US.PAT NO:
`
`TITLE:
`
`US PAT NO:
`TITLE:
`
`. L11: 100 of 105
`'
`4,130,870 IIMAGE AVAILABLEJI
`Hierarchially arranged menory system for a data processing
`arrangement having virtna! addressing
`
`L11: 101 of 105
`4,068,303 [IMAGE AVAILABLE]
`Address translation managing system with translation pair
`purging
`
`US.PAT N0:
`TITLE:
`
`3,329,340 [IMAGE AVAILABLE]
`VIRTUAL mow SYSTEM _
`
`'
`
`L11: 102 of 105
`.
`
`US PAT NO:
`'TITLE:
`
`'
`
`L11: 103 of 105
`3,828,327 {IMAGE AYAILABLE]_
`SIMPLIFIED STORAGE PROTECTION AND ADDRESS TRANSLATION UNDER
`SYSTEM MODE CONTROL IN A.DATA PROCESSING SYSTEM“
`
`US PAT N0:
`TITLEi
`
`us PAT no:
`TITLE:
`
`' 3,825,904 [IMAGE AVAILABLE]
`VIRTUAL MEMORY SYSTEM
`
`L11: 104 of 105
`
`L11: 105 of 105
`-
`-
`3,693,165 [IMAGE AVAILABLE]
`PARALLEL ADDRESSING OF A STORAGE HIERARCHY IN A DATA
`PROCESSING SYSTEM USING VIRTUAL ADDRESSING
`
`
`
`ARM_VPT_IPR_00000266
`ARM_VPT_IPR_OO_000266
`
`
`
`

`

`KWETH s. KIM
`
`J—19-94
`
`03:12pm
`
`Text Search 1;
`
`..nscript
`
`'Page
`
`1
`
`=> (1 111-5
`
`‘
`
`_
`
`' L1
`L2
`L3 .
`L4 -
`L5"
`L6
`L7
`
`L8
`L9
`L10
`L11
`L12
`
`1
`1
`i
`i
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`.
`
`(FILE ’USPAT’ ENTERED AT 14:04:56 ON 19 OCT 94)
`SET PAGELENGTH 62
`SET LINELENGTH 78
`1140 S VIRTUAL ADDRESS##
`626 S L1 (15A) TRANSLAT?
`2218 S DAT 0R TLB
`258 S L3 AND L1
`19 S L4 AND PIPELINES
`30 S L2 AND PIPELINES
`5593 S L3 OR TRANSLAT?
`
`(3A)
`
`(BUFFER 0R TABLE 0R ADDRESS)
`
`140 S L? (5A)
`(INDIVIDUAL 0R SEPARATE 0R SEVERAL 0R PLURAL?) AND
`328 S L? (5A)
`(MULTIPL? 0R DIFFERENT 0R SECOND ORIMAIN'OR MASTER)
`85 S (L8 OR L9) AND PIPELINfl
`'
`71 S'L10 NOT L5 NOT L6
`2?2 S (L8 0R L9) NOT L10
`
`ARM_VPT_IPR_00000267
`ARM_VPT_IPR_00000267
`
`
`

`

`
`
`KENNETH S. KIM
`
`.0—19—94
`
`02:22pm
`
`Text Search 1
`
`inscript
`
`Page
`
`=> d 15 1—19 ti
`
`US PAT No:
`TITLE:
`
`1 of 19
`L5:
`5,347,648 [IMAGE AVAILABLE]
`Ensuring write ordering under writeback cache error conditions
`
`5,309,383 [IMAGE AVAILABLE]
`US PAT No:
`Floating-point division circuit
`TITLE:
`14:22:30 COPY.AND CLEAR PAGE, PLEASE
`19 OCT 94 14:22:32
`U.S. Patent 8 Trademark Office-
`
`L5: 2 of 19
`
`'P0007
`
`US PAT No:
`TITLE:
`
`'L5: 3 of 19
`5,307,506 [IMAGE AVAILABLE]
`High bandwidth multiple computer bus apparatus
`
`US PAT N0:
`TITLE:
`
`5,307,477 [IMAGE AVAILABLE]
`Two-level cache memory system
`
`L5: 4 of 19
`
`us PAT N0:
`TITLE:
`
`L5: 5 of 19
`5,241,635 [IMAGE AVAILABLE]
`' Method For parallel
`instruction execution in a computer
`
`US PAT N0:
`TITLE:
`K
`
`US PAT N0:
`TITLE:
`
`US PAT N0:
`TITLE:
`
`US PAT N0:
`TITLE:
`
`US PAT No:
`TITLE:
`
`L5: 6 of 19
`‘
`-
`5,179,680 [IMAGE AVAILABLE]
`Instruction storage and cache miss recovery in a high Speed
`multiprocessing parallel processing apparatus
`
`L5: 7 of 19
`5,157,777 [IMAGE AVAILABLE]_
`Synchronous communication between execution environments in a
`data processing system employing an object-oriented memory
`protection mechanism
`
`L5: 8.0F 19
`5,150,469 [IMAGE AVAILABLE]
`System and method for processor pipeline control byselective
`signal deassertion
`'
`
`L5: 9 of 19
`5,101,341 [IMAGE AVAILABLE]
`Pipelined system For reducing instruction access time by
`accumulating predecoded instruction bits a FIFO
`
`L5: 10 of 19
`5,075,842 [IMAGE AVAILABLE]
`Disabling tag bit.recognition and allowing privileged
`operations to occur in an object—oriented memory protection
`mechanism
`
`us PAT No:
`TITLE:
`
`L5: 11 o: 19
`.
`5,057,837 [IMAGE AVAILABLE]
`Instruction storage method with a compressed Format using a
`mask word
`
`US_PAT No:
`TITLE:
`
`4,926,323 [IMAGE AVAILABLE]
`Streamlined instruction processor
`
`L5: 12 of 19
`-‘
`
`US PAT N0:
`4,920,477.[IMAGE AVAILABLE]
`_.
`L5: 13 of 19
`TITLE: m m table look aside buffer miss recovery
`met'o an
`apparatus
`
`US PAT No:
`TITLE:
`
`L5: 14 of 19
`4,894,824 [IMAGE AVAILABLE]
`Control network for a rapid connection circuit switch
`
`US PAT NO:
`TITLE:
`
`L5: 15 of 19
`4,833,599 [IMAGE AVAILABLE]
`Hierarchical priority branch handling For parallel execution
`
`ARM_VPT_IPR_00000268
`ARM_VPT;IPR_00000268
`
`
`
`

`

`KENNETH s. KIM
`
`J-19-94 02:22pm Text Search 1.
`
`.nscript
`
`Page
`
`2
`
`in a parallel processor
`
`US PAT N0:
`_TITLE:
`
`_
`
`L5:
`4,811,203 [IMAGE AVAILABLE]
`Stack frame cache on a microprocessor chip
`
`'16 of 19
`
`US PAT N0:
`TITLE:
`
`4,731g739 [IMAGE AVAILABLE]
`Eviction control apparatus
`
`L5: 17 0F 19
`
`US PAT N0:
`TITLE:
`
`L5: 18 of 19
`4,682,281 [IMAGE AVAILABLE]
`Data storage unit employing translation lookaside buffer
`pointer
`.
`14:22:35 COPY AND CLEAR'PAGE, PLEASE
`19 OCT 94 14:22:41
`- U.S. Patent & Trademark Office
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`P0008
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`US PAT N0:
`TITLE:
`
`4,612,612 [IMAGE AVAILABLE!
`Virtually addressed cache
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`L5: 19 0F 19“
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`=>
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`ARM_VPT_IPR_00000269
`ARM_VPT_IPR_00000269
`
`

`

`KENNETH S. KIM
`
`.0~19-94
`
`02:20pm
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`Text Search 1 Jnscript
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`Page
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`multiprocessing parallel processing apparatus
`14:19:42 COPY AND CLEAR PAGE, PLEASE
`19 OCT 94 14:20:30
`- U.S. Patent a Trademark OfFice
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`P0006
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`US PAT N0:
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`L5: 7 of 19
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`5,157,777 [IMAGE AVAILABLE]
`Synchronous communication between execution environments in a
`data processing system employing an object—oriented memory
`protection mechanism
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`5,150,469 [IMAGE AVAILABLE]
`System and method For processor pipeline control by selective
`signal deassertion
`.,1
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`L5: 9 of 19
`5,101,341 [IMAGE AVAILABLE]
`Pipelined system for reducing instruction access time by
`accumulating predecoded instruction bits a FIFO
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`5,075,842 [IMAGE AVAILABLE]
`Disabling tag bit recognition and allowing privileged
`Operations to occur in an object-oriented memory protection
`mechanism
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`L5: 11 of 19
`5,057,337 [IMAGE AVAILABLE]
`Instruction storage method with a compressed format using a
`mask word
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`4,926,323'IIMAGE AVAILABLE]
`Streamlined instruction processor
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`L5: 12 0F 19'
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`4,920,477 [IMAGE AVAILABLE]
`.L5: 13 of 19
`m table look aside buFl-‘er miss recovery .
`met 0
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`apparatus
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`'4,894,824 [IMAGE AVAILABLE]
`Control network For a rapid connection circuit switch
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`L5: 15 of 19
`4,833,599 [IMAGE AVAILABLE]
`Hierarchical priority branch handling for parallel execution
`in a parallel processor
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`L5: 16 oF 19
`4,811,203 [IMAGE AVAILABLE]
`‘ Stack frame cache on a microprocessor chip
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`4,731,739 [IMAGE AVAILABLE]
`Eviction control apparatus
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`L5: 17 of 19
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`L5:-18 of 19
`I
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`4,682,281 [IMAGE AVAILABLE]
`Data storage unit employing translation lookaside buffer
`pointer
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`4,612,612 [IMAGE AVAILABLE]
`Virtually addressed cache
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`L5: 19 of 19
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`ARM_VPT_IPR_00000270
`ARM_VPT_IPR_0000027_O
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`

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`'EENNEIH s. KIM
`
`. 0-19-94
`
`02:19pm
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`Text Search 1
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`1 of 30
`L6:
`5,333,296 [IMAGE AVAILABLE]
`Combined queue for invalidates and return data in
`multiprocessor system
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`L6: 2 of 30
`J'_
`5,317,720 [IMAGE AVAILABLE]
`Processor system with writeback cache using writeback and non
`writeback transactions stored in separate queues
`
`5,309,383 [IMAGE AVAILABLE]
`US PAT N0:
`Floating-point division circuit
`TITLE:
`14:18:59 COPY AND CLEAR PAGE, PL