UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`APPLE INC., HTC CORPORATION, HTC AMERICA, INC., SAMSUNG
`ELECTRONICS CO. LTD, SAMSUNG ELECTRONICS AMERICA, INC., AND
`AMAZON.COM, INC.,
`Petitioners,
`
`v.
`
`MEMORY INTEGRITY, LLC,
`Patent Owner.
`____________
`
`Case IPR2015-00163
`Patent 7,296,121
`____________
`
`
`
`
`
`PETITIONERS’ REPLY TO PATENT OWNER RESPONSE
`PURSUANT TO 37 C.F.R. § 42.23
`
`
`
`
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`APPLE INC., HTC CORPORATION, HTC AMERICA, INC., SAMSUNG
`ELECTRONICS CO. LTD, SAMSUNG ELECTRONICS AMERICA, INC., AND
`AMAZON.COM, INC.,
`Petitioners,
`
`v.
`
`MEMORY INTEGRITY, LLC,
`Patent Owner.
`____________
`
`Case IPR2015-00163
`Patent 7,296,121
`____________
`
`
`
`
`
`PETITIONERS’ REPLY TO PATENT OWNER RESPONSE
`PURSUANT TO 37 C.F.R. § 42.23
`
`
`
`
`
`Patent No. 7,296,121
`Petitioner’s Reply to Patent Owner Response
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`
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`
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`Attorney Docket No. 39521-0007IP4
`IPR2015-00163
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`TABLE OF CONTENTS
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`I.
`
`INTRODUCTION .............................................................................................. 1
`
`II. CLAIM CONSTRUCTIONS ............................................................................. 1
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`A. “States” ........................................................................................................ 2
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`B. “Programmed” ............................................................................................. 5
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`III. THE INSTITUTED GROUNDS ANTICIPATE OR RENDER OBVIOUS
`CLAIMS 4–6, 11, 12, AND 19–24 ............................................................................ 8
`
`A. Koster Discloses the Claimed “States” ........................................................ 8
`1. MI’s Focus on Koster’s Tags is Inapposite ................................................ 9
`2. Koster’s Snoop Filter Filters Requests Based on State Information
`Contained in the Local State Memory ............................................................. 11
`
`B. Koster Discloses that Each of its Processing Nodes is Programmed in the
`Manner Recited in Claim 11 ............................................................................ 13
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`C. Koster Discloses the Temporary Storage Recited in Claim 12 ................. 15
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`D. Koster in Combination with Smith Discloses Claims 19-24 ..................... 19
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`IV. CONCLUSION ................................................................................................ 20
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`1
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`EXHIBITS
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`APPL-1001
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`APPL-1002
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`APPL-1003
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`APPL-1004
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`APPL-1005
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`U.S. Patent Number 7,296,121 to Morton et al. (“the ‘121
`Patent”)
`
`Excerpts from the Prosecution History of the ‘121 Patent (“the
`Prosecution History”)
`
`U.S. Patent Application Publication Number 2002/0053004 to
`Pong (“Pong”)
`
`David Chaiken et al., “Directory-Based Cache Coherence in
`Large-Scale Multiprocessors,” Computer vol. 24, issue 9 (Jun
`1990) (“Chaiken”)
`
`Daniel Lenoski et al., “The Directory-Based Cache Coherence
`Protocol for the DASH Multiprocessor,” ISCA ‘90 Proceedings
`of the 17th annual international symposium on Computer
`Architecture, pp. 148-159 (May 1990) (“Stanford DASH”)
`
`APPL-1006
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`U.S. Patent Number 6,490,661 to Keller et al (“Keller”)
`
`APPL-1007
`
`APPL-1008
`
`Excerpts from Jose Duato et al., INTERCONNECTION NETWORKS
`– AN ENGINEERING APPROACH (1997) (“Duato”)
`
`Michael John Sebastian Smith, APPLICATION-SPECIFIC
`INTEGRATED CIRCUITS (1997) (“Smith”)
`
`APPL-1009
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`U.S. Patent No. 7,698,509 to Koster et al. (“Koster”)
`
`APPL-1010
`
`U.S. Patent No. 7,315,919 to O’Krafka et al. (“O’Krafka”)
`
`APPL-1011
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`U.S. Patent No. 6,338,122 to Baumgartner et al.
`(“Baumgartner”)
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`2
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`Patent No. 7,296,121
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`APPL-1012
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`Anant Agarwal et al., “An Evaluation of Directory Schemes for
`Cache Coherence,” Conference Proceedings of 15th Annual
`International Symposium on Computer Architecture (1988)
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`APPL-1013
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`Louis G. Johnson, “Multiprocessors,” ECEN 6253 Lecture
`Notes (April 28, 2003)
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`APPL-1014
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`Declaration of Dr. Robert Horst
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`APPL-1015
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`APPL-1016
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`APPL-1017
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`APPL-1018
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`APPL-1019
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`Excerpts from Merriam-Webster's Collegiate Dictionary - 10th
`Ed. (2001)
`
`Redacted Letter of March 28, 2014 from Memory Integrity’s
`Counsel to Samsung’s Counsel in Memory Integrity LLC v.
`Samsung Electronics Co., Ltd. et al., Case No. 1:13-cv-01808-
`GMS, including “Response to Samsung’s Allegation of a Rule
`11 Violation”
`
`Luca Benini and Giovanni De Micheli, “Networks on chips: a
`new SoC paradigm,” Computer vol. 35, issue 1 (Jan. 2002)
`(“Benini”)
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`“HyperTransport™ Technology I/O Link - A High-Bandwidth
`I/O Architecture” (Jul. 20, 2001) (“HyperTransport”)
`
`U.S. Publication No. 2005/0228952 to Mayhew et al.
`(“Mayhew”)
`
`APPL-1020
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`U.S. Patent No. 6,662,277 to Gaither (“Gaither”)
`
`APPL-1021
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`U.S. Patent Application Serial No. 10/966,161, as filed
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`APPL-1022
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`U.S. Patent Application Serial No. 10/288,347, as filed
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`APPL-1023
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`U.S. Patent No. 7,003,633 to Glasco (“Glasco”)
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`APPL-1024
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`
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`Affidavit of Mr. Michael Rueckheim in Support of Petitioner
`Apple Inc.’s Motion for Pro Hac Vice Admission
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`APPL-1025
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`Reply Declaration of Dr. Robert Horst
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`APPL-1026
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`APPL-1027
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`Deposition Transcript of Dr. Vojin G. Oklobdzija Vol. 1, November
`23, 2015
`Deposition Transcript of Dr. Vojin G. Oklobdzija Vol. 2, November
`23, 2015
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`APPL-1028
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`David E. Culler et al., Parallel Computer Architecture: A
`Hardware/software Approach (1st Ed.) (1998)
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`APPL-1029
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`APPL-1030
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`
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`"InfiniBand Architecture Specification Volume 1 Release 1.0.a"
`(June 19, 2001)
`James Laudon and Daniel Lenoski, Proceedings of the 24th Annual
`International Symposium on Computer Architecture, "The SGI
`Origin: A ccNUMA Highly Scalable Server" (1997)
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`4
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`Patent No. 7,296,121
`Petitioner’s Reply to Patent Owner Response
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`I.
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`Introduction
`Petitioners submit this Reply to Memory Integrity’s (“MI”) Response (Paper
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`31). MI relies upon improper claim construction proposals that have already been
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`considered and rejected in the Board’s Institution Decision (Paper 18). MI’s
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`proposals ignore the actual claim language and improperly seek to narrow the
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`broadest reasonable construction of the terms without support.
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`MI’s validity arguments are similarly deficient. MI inconsistently argues
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`that the use of the term “state” has a specific meaning in the field of cache
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`coherency (PO Resp. at 5), while, at the same time, argues that the Board should
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`ignore Koster’s (a reference that MI’s expert admitted was written for the cache-
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`coherency field) use of the term “local state memory” (PO Resp. at 23). MI’s
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`validity arguments are also highly attenuated and reflect a flawed understanding of
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`the Koster reference. Indeed, MI’s expert admitted that he is unfamiliar with the
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`relevant technical features of Koster’s “Infiniband” embodiment, an embodiment
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`which moots MI’s validity arguments with respect to the “temporary storage”
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`limitation. Moreover, MI’s expert declaration does not provide support as it fails
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`to identify any legal understanding applied in rendering a patentability opinion.
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`II. Claim Constructions
`In an effort to avoid Koster’s anticipating disclosure, MI “engages in a post
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`hoc attempt to redefine the claimed invention by impermissibly incorporating
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`language appearing in the specification into the claims.” In re Paulson, 30 F.3d
`1
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`1475, 1480 (Fed. Cir. 1994). MI’s proposals should be rejected as there is no clear
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`definition, in the ’121 Patent or elsewhere, that warrants narrowing the terms.
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`A. “States”
`MI’s proposed construction improperly seeks to add the very limitation that
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`MI is trying to add with its Motion to Amend. Motion to Amend at 2 (seeking to
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`add “wherein said states comprise cache coherency states of a cache coherence
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`protocol” to substitute claims). This attempt by MI belies its argument that
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`“states” is already limited to “cache coherence protocol states.” MI should not be
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`allowed to use claim construction to add claim limitations without amendment.
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`Further, the Board has already considered intrinsic and extrinsic evidence
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`and found that the term “states … is not limited to cache coherence protocol states
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`and is broad enough to include the condition of presence—i.e., what is stored in
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`cache memory.” Institution Decision, pp. 11-12. MI effectively repeats its earlier
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`arguments, essentially citing to the same disclosure within the ’121 specification,
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`and has presented no new evidence to diminish the Board’s preliminary findings.
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`Additionally, MI’s proposal contains the word “state” that it seeks to define,
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`exposing MI’s attempt to narrow the broadest reasonable interpretation of this
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`term.
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`“[T]he PTO should only limit the claim based on the specification or
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`prosecution history when those sources expressly disclaim the broader definition.”
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`In re Bigio, 381 F.3d 1320, 1325 (Fed. Cir. 2004). Here, none of the passages
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`cited by MI amount to an express disclaimer. To the contrary, as noted in the
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`Institution Decision, all of the examples in the specification to which MI (again)
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`points are couched in broad language stating that “particular implementations may
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`use a different set of states” and “[t]he techniques of the present invention can be
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`used with a variety of different possible memory line states.” Institution Decision,
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`p. 11.
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`Moreover, the claims at issue recite “states associated with selected ones of
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`the cache memories.” This recital is broader than the individual “memory line”
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`states described in each of the ’121 Patent passages quoted by MI. PO Resp., pp.
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`6-7 (“the cache state for a specified line”; “memory line state information”; and
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`“the memory line states are modified, owned, shared, and invalid”) (emphasis
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`added). MI does not and cannot explain why the meaning of states for individual
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`“line” content (these passages), which may be present in a variety of states, should
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`be the same as the state of the whole cache memories (as claimed). Indeed, MI’s
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`expert admitted that MI’s proposal (which he did not help in developing) “would
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`not apply” when referring to entire “cache memories.” Ex. 1026, 113:15-114:13;
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`112:13-16; 16:15-17:13.
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`Additionally, the dependent claims reveal that the patentee used express
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`language when seeking to limit a term to the context of cache coherency, and it
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`3
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`clearly omitted such language with respect to the term “states.” In particular, claim
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`3, which depends indirectly from independent claim 1, recites that the probe
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`filtering unit corresponds to an additional node that “comprises a cache coherence
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`controller.” Claim 3 demonstrates that, where MI intended for a claim term to be
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`limited to the context of cache coherency, MI explicitly used the term “cache
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`coherence” in the claim language. The omission of “cache coherence” from claim
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`1 is telling, and, under the broadest reasonable interpretation standard should be
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`read in contrast with claim 3 to preserve the breadth of claim 1.
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`MI also relies upon extrinsic evidence as supportive of its position, citing to
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`two references by Daniel Sorin, one of which was published nearly nine years after
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`the priority date sought by MI. PO Resp., pp. 4-5. However, “the fact that [MI]
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`can point to definitions or usages that conform to their interpretation does not make
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`the PTO’s definition unreasonable when the PTO can point to other sources that
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`support its interpretation.” In re Morris, 127 F.3d 1048, 1056 (Fed. Cir. 1997).
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`Here, the Board cited to the Microsoft Computer Dictionary for support of its
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`construction. Institution Decision, p. 12. MI’s criticism of this source is hardly
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`credible as MI endorses the use of the same Microsoft Computer Dictionary, as
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`well as a general purpose dictionary, for its “programmed” proposal. PO Resp.,
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`pp. 14-15. Moreover, far from simply being the “broad” technical dictionary
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`alleged by MI, the Microsoft Computer Dictionary is a source consistent with the
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`background of a POSITA to which both experts agreed: a bachelor’s degree in
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`electrical engineering, computer engineering, or computer science, and at least two
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`years of experience in the design of multiprocessor systems. See Ex. 1014, ¶ 8; Ex.
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`2016, ¶ 8.
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`Finally, the Petition contends that, even within the specific field of cache
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`coherence, the scope of the term “states” is “broad enough to include the condition
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`of presence,” as found by the Board. See, e.g., Petition, p. 10 (identifying the
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`Chaiken reference’s use of “status” to reference presence condition). The ‘121
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`patent accords by also using the term “state” to refer to presence. See ’121 patent
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`at 13:60-61 (“In the invalid state, a memory line is not currently available in cache
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`associated with any remote cluster.”). Indeed, the Sorin and Culler references that
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`MI cites also identify a “Not Present State.” Ex. 2010 at 89; Ex. 2002 at 4; see Ex.
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`1026 at 38:3-39:11 (Sorin and Culler are reliable references).
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`Accordingly, it is reasonable, for purposes of this proceeding in which the
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`broadest reasonable construction standard applies, to consider the term “states” as
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`being broad enough to encompass the condition of presence.
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`B. “Programmed”
`MI advanced arguments regarding the term “programmed” in its preliminary
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`response, without explicitly construing the term. MI now improperly seeks to
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`effectively amend the claim to overcome the Board’s preliminary endorsement of
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`the Koster reference, by advancing a narrowing interpretation of this term. MI
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`asserts that “the term ‘programmed’ should be construed to refer to a device that
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`has been ‘configured by a sequence of instructions’” (PO Resp., p. 13) and argues
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`that “‘programmed’ is not broad enough to encompass hardwired logic” (PO Resp.,
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`p. 17). However, these proposals are not supported by the evidence. See Ex. 1025,
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`¶¶ 2-6.
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`The ’121 Patent does not use the words “instruction” or “execute.” The ’121
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`Patent makes no distinction between hardwired logic and the relevant portion of
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`the processors that dictate the completion of a memory transaction. MI has not
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`cited to any language in the ’121 Patent which provides a clear limitation to the
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`nature of the programming. See PO Resp., pp. 13-14. Indeed, the ’121 Patent is
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`clear that these cited sections are “merely exemplary for the purpose of describing
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`a specific embodiment of the present invention.” Ex. 1001, 28:2-5. Further, even
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`the dictionaries that MI cites include reasonable definitions for programming that
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`defy MI’s proposal, such as “to work out a sequence of operations to be performed
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`by (a mechanism).” Ex. 2014, p. 931.
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`Indeed, hardwired logic is designed to perform a sequence of operations.
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`For example, a field programmable gate array (FPGA) is effectively an array of
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`logic gates that can be interwired in different configurations according to a
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`manufacturer’s programming. Ex. 1025, ¶ 3. Contrary to MI’s contention that the
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`term “programmed” is limited to devices that execute a series of instructions, a
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`field programmable gate array does not execute any instructions. Id. Rather, a
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`designer uses an interface to program the physical interconnections between the
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`logic gates, and the logic gates within the FPGA each perform a logical operation
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`corresponding to the gate’s type and its input signals. Id. Indeed, MI’s expert
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`admitted that “everybody use[s]” the term “programmable” with respect to an
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`FPGA. Ex. 1026, 123:12-124:11.
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`MI’s evidence states that “in hardwired logic systems the physical
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`interconnections of the elements govern the routes by which data flows between
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`the processing elements and thus the sequence of processing operations performed
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`on the data.” Ex. 2015 at 15/3. Yet, this is entirely consistent with the operation of
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`the aforementioned field programmable gate array. Ex. 1025, ¶ 5. By its very
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`name a field programmable gate array is “programmed” by a designer. Indeed,
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`MI’s own specification uses the term “programmable” when referring to devices
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`that do not execute instructions, teaching that “the cache coherence controller 230
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`is a specially configured programmable chip such as a programmable logic device
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`or a field programmable gate array.” Ex. 1001, 7:49-52 (emphasis added).
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`Accordingly, MI’s attempt to narrow the term “programmed” to exclude
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`hardwired systems is inconsistent with the use of the term “programmable” in the
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`’121 Patent and with the extrinsic evidence cited by MI. Indeed, to read the
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`limited passages of the ‘121 Patent cited by MI any differently would be a clear
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`violation of In re Bigio, as the section of the ‘121 Patent in which these passages
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`appear are clear that the examples given are not meant to be limiting. See Ex.
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`1001, 28:2-5. Instead, consistent with its usage in the context of FPGAs and the
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`dictionary cited by MI, the term “programmed” should be construed at least
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`broadly enough to encompass “designed to perform a sequence of operations,”
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`regardless of whether this design is in hardware or software. See Ex. 1025, ¶ 6.
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`III. The Instituted Grounds Anticipate or Render Obvious Claims 4–6, 11, 12,
`and 19–24
`In its Response, MI largely reiterates arguments raised in its Preliminary
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`Response. These arguments amount to attempts to improperly import limitations
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`from the specification into the claims, as discussed above in Section II supra, and
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`to otherwise misinterpret the plain teachings of the Koster reference. The Board
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`properly found such arguments deficient in its Institution Decision and should do
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`so again, as none of the evidence now proffered by MI establishes a valid legal
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`basis for altering the Board’s initial findings.
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`A. Koster Discloses the Claimed “States”
`MI’s argument rests entirely upon its claim construction of the term “state,”
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`which is improperly narrow for the reasons described above. See Ex. 1027,
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`186:17-24 (admitting that Koster discloses “states” under the Board’s preliminary
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`construction). The Board should uphold its preliminary determinations of the
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`scope of the term “state,” and, in so doing, the Board should reject MI’s arguments
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`as moot. However, even if the Board were to reverse its preliminary
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`determinations—which it should not—for reasons noted below, the Board should
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`find that Koster meets the claims by describing even MI’s narrow definition of
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`“states.”
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`As noted in the Petition, “Koster specifically describes the shadow tag
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`memory 164 as ‘local state memory . . . that stores the tags of data stored in the
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`local cache memories.’” Petition, p. 28 (citing Ex. 1009 at 6:11-13) (emphasis
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`added). In particular, Koster discloses that the “shadow tag memory ... may use a
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`MOESI (Modified Owner Exclusive Shared Invalid) cache coherency protocol.”
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`Ex. 1009 at 6:33-38. As acknowledged by the ‘121 Patent, the five components of
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`the MOESI protocol (Modified, Owner, Exclusive, Shared, and Invalid) are
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`“memory line states.” See Ex. 1001, 14:30-36. Thus, Koster’s shadow tag
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`memory 164 includes probe filtering information representative of states associated
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`with selected ones of the cache memories. MI’s arguments to the contrary can be
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`dismissed for either of at least two reasons.
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`1. MI’s Focus on Koster’s Tags is Inapposite
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`MI initially attempts to draw attention away from Koster’s explicit teaching
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`of a “local state memory” that “uses a MOESI . . . cache coherency protocol” by
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`focusing on Koster’s additional teaching of “tags” stored in that memory and
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`comparing MI’s incomplete description of these tags to its own narrow
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`construction of “states.” However, regardless of whether these “tags” meet MI’s
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`narrow construction of “states,” MI’s own logic in construing the term “states”
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`dictates that information representative of cache coherency states is stored by
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`Koster’s “local state memory.”
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`Under MI’s logic, because the field of the ‘121 Patent is cache coherency,
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`the ‘121 Patent’s use of the term “state” would necessarily be understood by a
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`person of ordinary skill in the art to mean a “cache coherency state.” Specifically,
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`in Section II(A) of its Response, MI cites to use of the phrase “cache coherency”
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`within the background section and within various portions of the detailed
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`description as proof that “the teachings of the ’121 Patent make it clear that its
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`inventions are directed to the specific field of cache coherency.” PO Resp., pp. 3-
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`4. MI then argues that “the term ‘state’ connotes a specific meaning in the field of
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`cache coherency—a cache coherency state.” PO Resp., p. 4.
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`By the same logic, because Koster is directed to the specific field of cache
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`coherency, its use of the word “state” is equally applicable to a “cache coherency
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`state.” Koster is titled “Snooping-Based Cache-Coherence Filter for a Point-To-
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`Point Connected Multiprocessing Node.” Ex. 1009, Title (emphasis added).
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`Indeed, Koster uses the term “cache-coheren[ce/cy/t]” over thirty times throughout
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`its specification. See, e.g., Ex. 1009, title, 3:15, 3:17, 3:44, 3:49, 3:51, 3:55, 4:22,
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`4:26, 4:28, 4:43, 4:51, 4:54, 4:58, 4:60, 4:64, 5:1, 5:7, 5:9, 5:15, 5:17, 5:18, 5:21,
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`6:7, 6:10, 6:37, 9:15, 10:36. Koster is no less directed to the specific field of cache
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`coherency than the ’121 Patent. Thus, assuming, arguendo, that MI’s construction
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`argument is correct, Koster’s description of a “local state memory” would
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`necessarily be read to be a local cache coherent state memory. This is consistent
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`with the title, which specifies that the snoop filter 162 is a cache-coherence filter.
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`See Ex. 1026 at 147:14-148:15 (Koster is written in the field of cache coherency
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`and claims use of MOESI protocol).
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`2.
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`Koster’s Snoop Filter Filters Requests Based on State
`Information Contained in the Local State Memory
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`MI’s attempts to explain away Koster’s use of the word “state” and
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`description that the local state memory “may use a MOESI . . . cache-coherency
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`protocol” are inconsistent with the logic underpinning its own narrow
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`interpretation of the teachings of Koster. MI argues that “despite Koster’s
`
`reference to such tags as ‘state’ information, the tags merely indicate an address
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`and are not representative of cache coherency states.” PO Resp., p. 23. However,
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`Koster doesn’t reference the tags as “state information,” as implied by MI. Rather,
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`Koster discloses that “the snoop filter 162 has local state memory (referred to and
`
`shown in FIG. 7 as ‘shadow tag memory’) 164 that stores the tags of data stored in
`
`the local cache memories.” Ex. 1009, 6:11-13. This description indicates one of
`
`two things: (1) the local state memory stores information representative of cache
`11
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`
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`Patent No. 7,296,121
`Petitioner’s Reply to Patent Owner Response
`
`coherency states in addition to the tags; or (2) Koster’s tags themselves would have
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`Attorney Docket No. 39521-0007IP4
`IPR2015-00163
`
`
`
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`been understood by a skilled artisan to represent cache coherency state information
`
`in addition to location information. See Ex. 1025, ¶ 39.
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`Regarding the latter, Koster’s tags do not merely provide the snoop filter
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`with addresses identifying locations of copies of requested data. Instead, they
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`provide the snoop filter with addresses identifying locations of copies of requested
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`data that are in a valid cache coherency state. After all, a person of ordinary skill
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`in the art would understand that Koster’s snoop filter 162 uses the tags to forward
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`data requests only to those processors known by the snoop filter 162 to have valid
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`copies, i.e., only those processors able to productively respond to the data request.
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`In only identifying the location of valid copies, Koster’s tags themselves reflect
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`cache coherency state information in addition to location information. See 1025, ¶
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`40.
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`MI further argues that “Koster does not disclose that shadow tag memory
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`164 stores the MOESI information. Nor does Koster disclose that the snoop filter
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`uses the MOESI information in the process of determining where to send a probe.”
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`PO Resp., pp. 23-24. However, a person of ordinary skill in the art would
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`understand that, in order to “use a MOESI . . . cache-coherency protocol,” the
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`shadow tag memory 164 would store information about the protocol (i.e., “MOESI
`
`information”). See 1025, ¶ 41. Moreover, Koster discloses the only functionality
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`12
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