IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`In re Patent of: Morton er al.
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`U.S. Patent No.:
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`7,296,121
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`Case No. IPR2015—00l63
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`Issue Date:
`< Appl. Serial No.:
`Filing Date:
`Title:
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`Nov. 13, 2007
`10/966,161
`Oct. 15, 2004
`REDUCING PROBE TRAFFIC IN MULTIPROCESSOR
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`Attorney Docket No. 39521-0007IP4
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`I
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`SYSTEMS
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`Mail Stop Patent Board
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
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`P.O. Box 1450
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`Alexandria, VA 22313-1450
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`PETITION FOR INTER PARTES REVIEW OF UNITED STATES PATENT
`NO. 7,296,121 PURSUANT TO 35 U.S.C. §§ 311-319, 37 C.F.R. § 42
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`

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`Attorney Docket No 39521—0007IP4
`Case No. IPR2015—00163
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`TABLE OF CONTENTS
`
`MANDATORY NOTICES UNDER 37 C.F.R § 42.8(a)(1) ........................ .. 1
`A. Real Party—In-Interest Under 37 C.F.R. § 42.8(b)(1) ............................. .. 1
`B. Related Matters Under 37 C.F.R. § 42.8(b)(2) ...................................... .. 1
`C. Lead And Back—Up Counsel and Service Information .......................... .. 2
`
`PAYMENT OF FEES — 37 C.F.R. § 42.103 ................................................ .. 2
`
`III.
`
`REQUIREMENTS FOR IPR UNDER 37 C.F.R. § 42.104 ......................... .. 2
`A. Grounds for Standing Under § 42.104(a) ............................................... .. 2
`B. Challenge Under § 42.l04(b) and Relief Requested.............................. .. 3
`C. Claim Construction under 37 C.F.R. §§ 42.104(b)(3) ........................... .. 4
`
`IV.
`
`SU1\/IMARY OF THE ‘ 121 PATENT ........................................................ .. 14
`
`A. Brief Technology Overview ................................................................. .. 14
`B. Brief Description of the ‘121 Patent .................................................... .. 17
`C. Summary of the Prosecution History of the ‘ 121 Patent ..................... .. 18
`D. Priority Date of the ‘ 121 Patent ........................................................... .. 19
`
`MANNER OF APPLYING CITED PRIOR ART TO EVERY CLAIM FOR
`
`WHICH IPR IS REQUESTED, THUS ESTABLISHING A REASONABLE
`LIKELIHOOD THAT AT LEAST ONE CLAIM OF THE ‘ 121 PATENT IS
`
`UNPATENTABLE ..................................................................................... .. 23
`
`A. Koster Anticipates Claims 1-6, 8, 11, 12 and 16 ................................. .. 23
`1.
`Koster Anticipates Claim 1 ......................................................... .. 26
`2.
`Koster Anticipates Claim 2 ......................................................... .. 29
`3.
`Koster Anticipates Claim 3 ......................................................... .. 30
`4.
`Koster Anticipates Claim 4 ......................................................... .. 31
`5.
`Koster Anticipates Claim 5 ......................................................... .. 32
`6.
`Koster Anticipates Claim 6 ......................................................... .. 33
`7.
`Koster Anticipates Claim 8 ......................................................... .. 34
`8.
`Koster anticipates Claim 11 ........................................................ .. 34
`9.
`Koster Anticipates Claim 12 ....................................................... .. 36
`10. Koster Anticipates Claim 16 ....................................................... .. 37
`B. Koster in view of Duato Renders Claims 9 and 10 Obvious ............... .. 38
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`C. Koster in view of O’Krafl<a Renders Claims 15 and 25 Obvious ........ .. 41
`
`1.
`
`2.
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`Koster in view of O’Krafl<a Renders Claim 15 Obvious ........... .. 44
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`Koster in view of O’Krafl<a Renders Claim 25 Obvious ........... .. 45
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`D. Koster in View of Smith Render Claims 17-24 Obvious .................... .. 51
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`VI.
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`REDUNDANCY ......................................................................................... .. 55
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`

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`VII. CONCLUSION ........................................................................................... .. 56
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`Attorney Docket No 39521-0007IP4
`Case No. IPR2015—O0163
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`

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`Attorney Docket No 39521-0O07]P4
`Case No. lPR20l5—00163
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`EXHIBITS
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`APPL—1001
`
`U.S. Patent Number 7,296,121 to Morton et al. (“the ‘12l Pa-
`ten ”)
`
`APPL-1002
`
`APPL-1003
`
`APPL— 1 004
`
`APPL-1005
`
`Excerpts from the Prosecution History of the ‘121 Patent (“the
`Prosecution History”)
`
`U.S. Patent Application Publication Number 2002/0053 004 to
`Pong (“Pong”)
`
`David Chaiken et al., “Directory—Based Cache Coherence in
`Large—Scale Multiprocessors,” Computer V01. 24, issue 9 (Jun
`1990) (“Chaiken”)
`
`Daniel Lenoski et al., “The Directory—Based Cache Coherence
`Protocol for the DASH Multiprocessor,” ISCA ‘90 Proceedings
`ofthe 17th annual international symposium on Computer Ar-
`chitecture, pp. 148-159 (May 1990) (“Stanford DASH”)
`
`APPL-1006
`
`U.S. Patent Number 6,490,661 to Keller et al (“Keller”)
`
`APPL-1007
`
`Excerpts from Jose Duato et al. , INTERCONNECTION NETWORKS
`— AN ENGINEERING APPROACH (1997) (“Duato”)
`
`APPL—1008
`
`Michael John Sebastian Smith, APPLICATION-SPECIFIC INTE-
`GRATED CIRCUITS (1997) (“Smith”)
`
`APPL—1009
`
`U.S. Patent No. 7,698,509 to Koster et al. (“Koster”)
`
`APPL-1010
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`U.S. Patent No. 7,315,919 to O’Krafl<a et al. (“O’Krafl<a”)
`
`APPL-1011
`
`U.S. Patent No. 6,338,122 to Baumgartner et al. (“Baumgart-
`ner”
`
`APPL—1012
`
`Anant Agarwal et al., “An Evaluation of Directory Schemes for
`Cache Coherence,” Conference Proceedings of] 5th Annual In-
`ternational Symposium on Computer Architecture (1988)
`
`iii
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`

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`Attorney Docket No 3952 l—0O07IP4
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`APPL—1013
`
`Louis G. Johnson, “Multiprocessors,” ECEN 6253 Lecture
`Notes (April 28, 2003)
`
`APPL-1014
`
`Declaration of Dr. Robert Horst
`
`APPL-1015
`
`APPL—1016
`
`Excerpts from Merriam—Webster's Collegiate Dictionary — 10th
`Ed. (2001)
`
`Redacted Letter of March 28, 2014 from Memory lntegrity’s
`Counsel to Samsung’s Counsel in Memory Integrity LLC 12.
`Samsung Electronics Co., Ltd. et al., Case No. 1:l3—cV—01808—
`GMS, including “Response to Samsung’s Allegation of a Rule
`11 Violation”
`
`APPL—10l7
`
`Luca Benini and Giovanni De Micheli, “Networks on chips: a
`new SoC paradigm,” Computer Vol. 35, issue 1 (Jan. 2002)
`(“Benini”)
`
`APPL—1018
`
`“HyperTransportTM Technology I/O Link - A High—Bandwidth
`I/O Architecture” (Jul. 20, 2001) (“HyperTransport”)
`
`APPL—1019
`
`U.S. Publication No. 2005/0228952 to Mayhew et al. (“May-
`hew”)
`
`APPL-1 020
`
`U.S. Patent No. 6,662,277 to Gaither (“Gaither”)
`
`APPL- 1 021
`
`U.S. Patent Application Serial No. 10/966,161, as filed
`
`APPL—1 022
`
`U.S. Patent Application Serial No. 10/288,347, as filed
`
`APPL—1023
`
`U.S. Patent No. 7,003,633 to Glasco (“G1asco”)
`
`iv
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`

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`Attorney Docket No 39521-00071134
`Case No. lPR20 l 5-00163
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`Apple Inc.; HTC Corporation and HTC America, Inc. (collectively “HTC”);
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`Samsung Electronics Co. Ltd, Samsung Electronics America, Inc., and Samsung
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`Telecommunications America, LLC (collectively “Samsung”); and Amazon.com,
`
`Inc. (collectively “Petitioners”) petition for Inter Partes Review (“IPR”) under 35
`
`U.S.C. §§ 311-319 and 37 C.F.R. § 42 of claims 1-6, 8-12, and 15-25 (“the Chal-
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`lenged Claims”) of U.S. Patent No. 7,296,121 (“the ‘121 Patent”). As explained
`
`below, there exists a reasonable likelihood that Petitioners will prevail in demon-
`
`strating unpatentability of at least one Challenged Claim based on teachings set
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`forth in the references presented in this petition.
`
`I.
`
`MANDATORY NOTICES UNDER 37 C.F.R § 42.8(a)(1)
`
`A.
`
`Real Party—In-Interest Under 37 C.F.R. § 42.8(b)(1)
`
`Apple Inc.; HTC Corporation and HTC America, Inc. (collectively “HTC”);
`
`Samsung Electronics Co. Ltd, Samsung Electronics America, Inc., and Samsung
`
`Telecommunications America, LLC (collectively “Samsung”); and Amazon.com,
`
`Inc. (collectively “Petitioners”) are the real parties-in—interest.
`
`B.
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`Related Matters Under 37 C.F.R. § 42.8(b)(2)
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`Petitioners are not aware of any disclaimers, reexamination certificates or
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`petitions for inter parres review for the ‘ 121 Patent. The ‘121 Patent is the subject
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`of Civil Action Numbers 1:13-cv— 1795 (Del), 1:13-cv— 1796 (Del.), 1:13-cv— 1797
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`(Del.), 1:13—cv— 1798 (Del.), 1:l3—cv- 1799 (Del), 1:13—cv— 1800 (Del.), 1:13—cv—
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`

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`Attorney Docket No 39521—0007IP4
`Case No. IPR20 1 5—00163
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`1801 (Del.), 1:13—cV— 1802 (Del.), 1:13—cV— 1803 (Del.), 1:13—cV— 1804 (Del.),
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`1:13—cV— 1805 (Del.), 1:13-cv— 1806 (Del.), 1:13—cV— 1807 (Del.), 1:13—cV— 1808
`
`(Del.), 1:13—cV— 1809 (Del.), 1:13—cV— 1810 (Del.), 1:13—cV— 1811 (Del.), all filed
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`November 1, 2013; and Civil Action Numbers 1:13—cV— 1981 (Del.), 1:13—cV— 1982
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`(Del.), 1:13-cv— 1983 (Del.), 1:l3-cv- 1984 (Del.), all filed November 26, 2013.
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`Concurrently with this petition, Petitioners are filing three other petitions for
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`IPR (identified with attorney docket numbers IPR2015-00159, IPR2015-00162,
`
`and IPR2015—00172) of the ‘ 121 Patent. The relationship between the limited
`
`grounds presented in these four petitions is discussed in Section VI.
`
`C.
`
`Lead And Back-Up Counsel and Service Information
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`Petitioners designate W. Karl Renner, Reg. No. 41,265, as Lead Counsel and
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`Roberto Devoto, Reg. No. 55,108, as Backup Counsel, both available at 3200 RBC
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`Plaza, 60 South Sixth Street, Minneapolis, MN 55402 (T: 202-783-5070; F: 202-
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`783-2331), or electronically by email at IPR39521—0007IP4@fr.com.
`
`II.
`
`PAYMENT OF FEES — 37 C.F.R. § 42.103
`
`Petitioners authorize the Patent and Trademark Office to charge Deposit Ac-
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`count No. 06-1050 for the fee set in 37 C.F.R. § 42.15(a) for this Petition and fur-
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`ther authorizes for any additional fees to be charged to this Deposit Account.
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`III. REQUIREMENTS FOR IPR UNDER 37 C.F.R. § 42.104
`
`A.
`
`Grounds for Standing Under § 42.104(a)
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`l\)
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`

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`Attorney Docket No 39521—0007IP4
`Case No. IPR2015-00163
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`Petitioners each certify that the ‘ 121 Patent is available for IPR. The present
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`petition is being filed within one year of service of each of the complaints against
`
`Petitioners, which was no earlier than November 1, 2013. None of the Petitioners
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`is barred or estopped from requesting this review on the below—identified grounds.
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`B.
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`Challenge Under § 42.104(b) and Relief Requested
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`Petitioners request IPR of the Challenged Claims on the grounds set forth in
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`the table shown below, and requests that each of the Challenged Claims be found
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`unpatentable. An explanation of unpatentability under the statutory grounds identi-
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`fied below is provided in the form of detailed description that follows, indicating
`
`where each element can be found in the cited prior art, and the relevance of that
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`prior art. Additional explanation and support for each ground of rejection is set
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`forth in EX. 1014, Declaration of Dr. Robert Horst.
`
`
`
`Ground 1
`1-6, 8, 11, 12 and 16
`Ground 2 i 9 and 10
`Ground 3 I 15 and 25
`Ground 4 I 17-24
`
`§l02: Koster
`§103: Koster and Duato
`t §103: Koster and O’Krafka
`{ §103: Koster and Smith
`
`The ‘ 121 Patent issued from U.S. patent application number 10/966,161,
`
`which was filed as a continuation-in—part (CIP) on October 15, 2004, and includes
`
`a claim of priority to U.S. Application No. 10/288,347, filed on November 4, 2002,
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`now Patent No. 7,003,633. As will be described in greater detail in Section
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`

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`Attorney Docket No 39521—0007IP4
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`(1V)(D), priority claim is not valid for claims challenged by this petition, and there-
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`fore, the earliest effective filing date for those claims is no earlier than the filing
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`date of the CIP application, October 15, 2004.
`
`Koster and O’Krafl<a each qualify as prior art at least under 35 U.S.C. §
`
`102(e). Specifically, Koster (EX. 1009) was filed July 13, 2004 and O’Krafl<a (EX.
`
`1010) was filed June 15, 2004, which are both before the priority date of the ‘ 121
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`Patent. Duato, and Smith each qualify as prior art at least under 35 U.S.C. §
`
`102(b). Specifically, Duato (EX. 1007) and Smith (EX. 1008) were each published
`
`in 1997, which are all more than a year before even the earliest proclaimed priority
`
`date of the ‘ 121 Patent.
`
`C.
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`Claim Construction under 37 C.F.R. §§ 42.104(b)(3)
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`Each term of a claim subject to IPR is given its “broadest reasonable con-
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`struction in light of the specification of the patent in which it appears.” 1 37 C.F.R.
`
`§ 42.100(b). Accordingly, for purposes of this proceeding only, Petitioners submit
`
`constructions for the following terms, and submits that all remaining terms should
`
`1 Because the standards of claim interpretation applied in litigation differ from
`
`PTO proceedings, any interpretation of claim terms in this IPR is not binding upon
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`Petitioners in any litigation(s) related to the subject patent. See In re Zletz, 13
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`USPQ2d 1320, 1322 (Fed. Cir. 1989).
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`

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`be given their plain meaning.
`
`1. “processing node” (claims 1, 2, 8, 11, 14-16, 25)
`
`The ‘ 121 Patent does not provide an explicit definition for the term “pro-
`
`cessing node.” However, on its face, the word “processing” indicates the presence
`
`of a “processor” and, in modifying the word “node” indicates that the node in-
`
`cludes or is otherwise associated with a processor. See EX. 1014, 1] 24. The ‘ 121
`
`Patent supports this notion in its description and usage of the terms “processor”
`
`and “node.” In particular, the ‘121 Patent notes that “the terms node and processor
`
`are often used interchangeably herein.” EX. 1001, 6:52-54. “However, it should
`
`be understood that, according to Various implementations, a node (e.g., processors
`
`202a-202d) may comprise multiple sub—units, e.g., CPUS, memory controllers, I/O
`
`bridges, etc.” Ex. 1001, 6:54-57. FIG. 19 illustrates one exemplary implementa-
`
`tion of such a processing node. See Ex. 1001, 27:25-28. Based on this example
`
`and the aforementioned description of “node” as encompassing, in some imple-
`
`mentations, multiple subunits that may be processors (e.g., CPUS), the ‘ 121 Patent
`
`describes a processing node that includes at least one processor. See EX. 1014, 1]
`
`24.
`
`The ‘ 121 Patent further describes these processing nodes as end—points with-
`
`in a larger interconnected system. Ex. 1001, 27:32-40. Indeed, independent claims
`
`1, 16, and 25 recite the plurality of processing nodes as being “interconnected by a
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`first point-to-point architecture” and as being included in “a computer system” and,
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`hence, as being a computer subsystem. See EX. 1014, 11 25.
`
`The Baumgartner reference (U.S. Patent No. 6,338,122) (EX. 1011), which is
`
`in the same field of art as the ‘ 121 Patent, demonstrates common usage of the term
`
`“processing node,” and in doing so reveals that persons of skill would have under-
`
`stood the term in a manner consistent with the aboVe—noted interpretation: “B1r()_—
`
`cessing nodes 8a-8n may Q include M (M Z 1) processors 10, a local intercon-
`
`nect 16, and a system memory 18. . .” (emphasis added). EX. 1011, 3:17-19 and
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`Fig. 1. See Ex. 1014, 11 26.
`
`Accordingly, it is reasonable, for purposes of this proceeding in which the
`
`broadest reasonable construction standard applies, to consider the term “processing
`
`node” as broad enough to encompass “an interconnectable computer subsystem
`
`comprising at least one processor.” See EX. 1014, 11 23.
`
`2. “interconnected by a first point-to-point architecture”
`(claims 1, 16, 25)
`
`In a co—pending litigation, the Patent Owner has asserted that the term “in-
`
`terconnected by a first point-to-point architecture” reads on any system of proces-
`
`sors that uses point—to—point links and they have contrasted this with “a shared-bus
`
`architecture.” See EX. 1016, pp. 1-2. In particular, in response to questions asked
`
`about the scope of the claimed point-to-point architecture, the Patent Owner indi-
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`

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`cated that the claimed point—to—point architecture is broad enough to cover Figure
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`1B of the ‘121 Patent by stating:
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`Attomey )ocket No 39521-0O07lP4
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`Indeed, this is consistent with what the ‘121 Patent shows in Figure
`
`1B, which the Patent's specification describes as a point—to—point ar-
`
`chitecture that can use the techniques of the patented invention. See
`
`I‘ 121 Patent, Fig. 1B and 6:24-35. Further, the patent notes that the
`
`use of a switch as shown in Figure 1B is advantageous because it “al-
`
`lows implementation with fewer point—to—point links.”
`
`See id. at 2 (emphasis added).
`
`In View of the Patent Owner’s assertions, for purposes of this proceeding in
`
`which the broadest reasonable construction standard applies, it is appropriate to
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`construe the term “interconnected by a first point—to—point architecture” as broad
`
`enough to encompass “connected to each other using point—to—point links.”
`
`3. “probe” (claims 1-3, 6, 8-17, 19, 20, 22, 24, 25)
`
`The ‘121 Patent specification defines the term “probe” as a “mechanism for
`
`eliciting a response from a node to maintain cache coherency in a system.” Ex.
`
`1001, 5:45-47 (“A mechanism for eliciting a response from a node to maintain
`
`cache coherency in a system is referred to herein as a probe”). Consistent with
`
`this definition, the ‘ 121 Patent specification uses the term probe broadly to de-
`
`scribe messages used for snooping cache, as well as messages that carry infor-
`
`mation for maintaining cache coherency in a system. EX. 1001, 5:47-48 (“In one
`
`example, a mechanism for snooping a cache is referred to as a probe”) and 11-66-
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`67 (“any message for snooping a cache can be referred to as a probe.”) and 11: 20-
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`23 (“While probes and probe responses carry information for maintaining cache
`
`coherency in the system, read responses can carry actual fetched data”). See EX.
`
`1014, 11 27.
`
`Accordingly, it is reasonable, for purposes of this proceeding in which the
`
`broadest reasonable construction standard applies, to consider the term “probe” as
`
`broad enough to encompass “a mechanism that elicits a response from a node to
`
`maintain cache coherency in a system.” See EX. 1014, 11 27.
`
`4. “probe filtering information” (claims 1, 3, 6, 16, 25)
`
`The ‘ 121 Patent defines the term “probe filtering information” as “[a]ny cri-
`
`terion that can be used to reduce the number of clusters or nodes probed.” EX.
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`1001, 14:50-52 (“[a]ny criterion that can be used to reduce the number of clusters
`
`or nodes probed is referred to herein as probe filter information”). The ‘121 Pa-
`
`tent uses the term probe filtering information consistent with this definition. For
`
`instance, when describing its figures, the ‘121 Patent specification points out that
`
`Fig. 8 shows a diagram representing probe filter information, and, consistent with
`
`its definition for that term, the ‘ 121 Patent specification points out that the Fig. 8
`
`probe filtering information “can be used to reduce the number of transactions in a
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`multiple or single cluster system.” EX. 1001, 14:48-50. Similarly, according to
`
`claim 3, the probe filtering information may comprise a cache coherence directory
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`Attorney Docket No 3952 l—0007IP4
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`which includes entries corresponding to memory lines stored in the selected cache
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`memories. Ex. 1001, 31:12-16. See Ex. 1014, 1111 28-29.
`
`Accordingly, it is reasonable, for purposes of this proceeding in which the
`
`broadest reasonable construction standard applies, to consider the term “probe fil-
`
`tering information” as broad enough to encompass “any criterion that can be used
`
`to reduce the number of clusters or nodes probed.” See EX. 1014, 1] 28.
`
`5. “states associated with selected ones of the cache
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`memories” (claims 1, 16, 25)
`
`The ‘ 121 Patent does not provide an explicit definition for the term “states
`
`associated with selected ones of the cache memories.” In fact, the ‘ 121 Patent fails
`
`to limit the recited “states” to a specific type of state nor even to a particular group
`
`of states, such as standard coherence protocol states. See Ex. 1001, 14:30-36. To
`
`illustrate, rather than limiting states to standard coherence protocol states, the ‘ 121
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`Patent notes that “[t]he techniques of the present invention can be used with a vari-
`
`ety of different possible memory line states.” See id.
`
`Merriam Webster’s Dictionary defines the word “state” as “mode or condi-
`
`tion of being,” which is exemplified by presence. See Ex. 1015, pp. 1145, 919 (de-
`
`fining “presence” as “the fact or condition of being present” (emphasis added)).
`
`The ‘ 121 Patent uses the term “state” consistent With this definition. For example,
`
`the ‘ 121 Patent describes that a “directory of shared states .
`
`.
`
`. indicates Where par-
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`ticular memory lines are cached within the cluster.” Ex. 1001, 28:29-34.
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`Attorney Docket No 39521—0007IP4
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`Furthermore, the Chaiken reference (Ex. 1004), which is in the same field of
`
`art as the ‘ 121 Patent, uses the Word “status” to reference state in a manner con-
`
`sistent with the above-noted interpretation, and, thus, further supports the assertion
`
`that presence is one example of a type of state: “The full—map protocol uses direc-
`
`tory entries with one bit per processor and a dirty bit. Each bit represents the status
`
`ofthe block in the corresponding processor’s cache (present or absent).” EX. 1004,
`
`p. 50.
`
`Accordingly, it is reasonable, for purposes of this proceeding in which the
`
`broadest reasonable construction standard applies, to consider the term “states as-
`
`sociated With selected ones of the cache memories” as being broad enough to en-
`
`compass “any modes or conditions of selected ones of the cache memories.” See
`
`Ex. 1014,1111 30-32.
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`6. “transmit the probes only to selected ones of the pro-
`cessing n0des” (claims 1 and 16)
`
`Independent claims 1 and 16 recite transmitting “probes only to selected
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`ones of the processing nodes.” Applying the broadest reasonable interpretation,
`
`this phrase should be construed broadly enough to cover transmission of each
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`probe to one or more selected processing nodes. In particular, claims 1 and 16 re-
`
`cite that multiple “probeg” are transmitted to “selected one_s_ of the processing
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`nodes.” Because the claims describe the transmission of multiple “probes” instead
`
`of a single “probe,” the claim language does not require that a single probe be
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`Attorney Docket No 3952l—0007IP4 ‘
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`transmitted to more than one selected processing node, despite the claims’ use of
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`the plural form of “selected ones.” See Ex. 1014, 11 34. Rather, each probe could
`
`be transmitted to a single selected processing node and still satisfy the require-
`
`ments of claims 1 and 16. See id. For example, if probe A is transmitted to a se-
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`lected processing node X and probe B is transmitted to a selected processing node
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`Y, probes (i.e., probes A and B) are transmitted to selected ones of the processing
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`nodes (i.e., processing nodes X and Y) despite the distribution of the nodes among
`plural processing nodes. See id.
`I
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`Accordingly, it is reasonable, for purposes of this proceeding in which the
`
`broadest reasonable construction standard applies, to consider the term “transmit
`
`the probes only to selected ones of the processing nodes” as broad enough to en-
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`compass “transmit each of the multiple probes only to one or more selected pro-
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`cessing nodes.” See Ex. 1014, W 33-34.
`
`7. “cache coherence controller” (claim 3)
`
`The ‘ 121 Patent defines the term “cache coherence controller” as any mech-
`
`anism or apparatus that can be used to provide communication between multiple
`
`processing nodes while maintaining cache coherence. See EX. 1001, 722-6. The
`
`‘ 121 Patent uses the term cache coherence controller consistent with this defini-
`
`tion. For instance, the ‘ 121 Patent specification points outwith regard to Fig. 2,
`
`which shows a diagram of a multiple processor cluster that includes a cache coher-
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`ence controller, the ‘ 121 Patent illustrates the cache coherence controller may be
`
`connected to processors within the cluster and with other clusters of processors. In
`
`such a configuration, “cache coherence controller 230 communicates with both
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`processors 202a-d as well as remote clusters using a point-to-point protocol.” Ex.
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`1001, 7:10-12.
`
`Though FIGS. 4-12 focus on such inter-cluster communications, the ‘ 121
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`Patent also describes the use of the cache coherence controller for filtering intra-
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`cluster communications. See EX. 1001, 25:24-57, 26:36-57; see also Ex. 1014, 11
`
`37. Specifically, the ‘ 121 Patent specification describes that “the filtering of
`
`probes within a cluster, i.e., local probe filtering, may be implemented in systems
`
`having multiple clusters as well as systems having a single cluster of processors.”
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`EX. 1001, 26:36-39. Thus, a cache coherence controller may filter probes between
`
`clusters and/or between processors within a cluster. See Ex. 1014, 1] 37.
`
`Accordingly, it is reasonable, for purposes of this proceeding in which the
`
`broadest reasonable construction standard applies, to consider the term “cache co-
`
`herence controller” as broad enough to encompass “any mechanism or apparatus
`
`that can be used to provide communications between multiple processing nodes
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`while maintaining cache coherence.” See EX. 1014, W 35-37.
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`8. “cache coherence directory” (claim 3)
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`The ‘121 Patent does not provide an explicit definition of the term “cache
`
`coherence directory,” but does describe that, “according to some embodiments, a
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`cache coherence directory is a mechanism that facilitates the tracking by that cache
`
`coherence controller of Where particular memory lines Within its cluster’s memory
`
`are being cached in remote clusters.” Ex. 1001, 18:43-47. The ‘121 Patent uses
`
`the term cache coherence directory consistent with this description. See Ex. 1014,
`
`1] 38. For example, the ‘ 121 Patent describes that the cache coherence directory
`
`“indicates the existence and location of any remotely cached copies of the
`
`memory.” Ex. 1001, 2127-8.
`
`Accordingly, it is reasonable, for purposes of this proceeding in which the
`
`broadest reasonable construction standard applies, to consider the term “cache co-
`
`herence directory” as broad enough to encompass “a mechanism that facilitates the
`
`tracking of where particular memory lines are being cached.” See EX. 1014, 1] 38.
`
`9. “the probes” (claim 8)
`
`Claim 8 recites that “each of the processing nodes is operable to transmit E
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`p_r_o__b_c_:§ only to the probe filtering unit” (emphasis added). The term “the probes”
`
`employs the definite article “the,” which particularizes the subj ect “probes” by re-
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`ferring to an antecedent for that term. See NTP, Inc. v. Research in Motion, Ltd. ,
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`418 F. 3d 1282, 1306 (Fed. Cir. 2005). The only antecedent for “probes” is recit-
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`ed in independent claim 1, from which claim 8 depends. Claim 1 recites “a probe
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`filtering unit which is operable to receive rm corresponding to memory lines
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`from the processing nodes and to transmit the probes only to selected ones of the
`
`processing nodes?” Ex. 1001, 3 l : 1-5. Thus, the term “the probes” recited in claim
`
`8 explicitly refers to probes received by the probe filtering unit from the processing
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`nodes.
`
`Notably, this means that claim 8 does not require the processing nodes to be
`
`operable to send a_ll probes only to the probe filtering unit. Rather, claim 8 simply
`
`requires that those probes received by the probe filtering unit from the processing
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`nodes be transmitted only to the probe filtering unit (as opposed to, for example,
`
`the processing nodes broadcasting those probes received by the probe filtering unit
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`to other processing nodes).
`
`IV.
`
`SUMMARY OF THE ‘121 PATENT
`
`A.
`
`Brief Technology Overview
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`A shared—memory multiprocessor is a computer system in which multiple
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`processors share memory. See Ex. l0l4, 1] l2. Memory (and I/O devices) are
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`2 In interpreting this feature of claim 1, it is Worth noting that dependent claim 14
`
`of the ‘I21 Patent clarifies that “the probes” transmitted to selected ones of the
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`processing nodes by the probe filtering unit need not be exact copies of the probes
`
`received by the probe filtering unit but rather may instead be modified Versions of
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`the probes received by the probe filtering unit.
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`shared by each of the processors via a local interconnection network. Ex. 1013, p.
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`1. “Each processor has access to its own memory and all the memory of all the
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`other processors.” Id “Memory becomes a common resource which must be
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`shared between execution threads running simultaneously (really simultaneously,
`
`not time shared) on different processors in the multiprocessor system.” Id.
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`One way to increase the speed of a multiprocessor is to associate a cache
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`memory with each processor. See Ex. 1014, 11 13. Cache memories are signifi-
`
`cantly faster than standard main memory (e. g., RAM and ROM). However, be-
`
`cause cache memories have significantly smaller capacity than main memory, each
`
`processor can use a cache memory to store a copy of only a portion of the data
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`stored in main memory (e. g., the portion most recently or most commonly accessed
`
`by the processor). See id. Moreover, because threads are executed simultaneously
`
`across the processors within the multiprocessor share memory, more than one pro-
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`cessor may store a copy of a particular memory location in its cache. See id.
`
`Each of these simultaneously executed threads has the ability to cause its
`
`processor to both load the data stored in its cache and store updates to the data
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`back into its cache. See id. at 11 14. As such, inconsistencies may arise between
`
`copies of data that are stored in different of the cache memories. See id. For ex-
`
`ample, in the case where multiple processors store a copy of a memory location in
`
`their respective caches, one of the processors may update the copy stored in its
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`cache, causing the copy within the cache of that processor to become inconsistent
`
`or incoherent with respect to non—updated copies of the data that remain in the
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`cache of other of the processors. See id. Because coherency is Valued, the updated
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`copy of the memory location stored in the updating processor’s cache is known as
`
`a “dirty” copy of the memory location, because it differs from what is in main
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`memory. See Ex. 1012, p. 280; see also EX. 1014, 11 14. The other processors that
`
`store stale copies of the now—updated memory location must be notified in some
`
`manner of the existence of a dirty copy, and thus of an update, to prevent the other
`
`processors from operating with/on that stale data. See EX. 1014, fll 14.
`
`A number of schemes have been proposed for maintaining coherency be-
`
`tween the caches within a shared—memory multiprocessor. See id. at 11 15. As de-
`
`scribed in a 1988 paper that compares several of these schemes:
`
`A cache coherency protocol is the mechanism by which the coherency
`
`of the caches is maintained. Maintaining coherency entails taking spe-
`
`cial action when one processor writes to a block of data that exists in
`
`other caches. The data in the other caches, which is now stale, must be
`
`either invalidated or updated with the new value, depending on the
`
`protocol. Similarly, if a read miss occurs on a shared data item and
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`memory has not been updated with the most recent value (as would
`
`happen in a copy—back cache), that most recent value must be found
`
`and supplied to the cache that missed. These two actions are the es-
`
`sence of all cache coherency protocols. The protocols differ primarily
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`in how they determine Whether the block is shared, how they find out
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`Where block copies reside, and how they invalidate or update copies.
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`Ex. 1012, p. 280.
`
`Two classes of these cache coherency protocols are “snoopy—based” and “di—
`
`rectory—based.” See id. at 11 16.
`
`In snoopy-based protocols, “each cache in the sys-
`
`tem must watch all coherency transactions to determine when consistency-related
`
`actions should take place for shared data.” See id. On the other hand, directory-
`
`based protocols, “keep a separate directory associated with main memory that
`
`stores the state of each block of main memory.” See id This directory is refer-
`
`enced and, if necessary, updated to account for coherency transactions that occur
`
`and to trigger corresponding consistency—related actions for shared data. See id.
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`Some systems combine aspects from each of these protocols. See id.
`
`B.
`
`Brief Description of the ‘121 Patent
`
`The ‘ 121 Patent aims to “provide techniques for improving data access and
`
`cache coherency in systems having multiple processors connected using point—to—
`
`point links.” EX. 1001, 2:39-42. According to the ‘121 Patent, “cache coherency
`
`proble