Patent No. 7,296,121
`IPR2015-00163
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`
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`
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`APPLE INC., HTC CORPORATION, HTC AMERICA, INC., SAMSUNG
`ELECTRONICS CO. LTD, SAMSUNG ELECTRONICS AMERICA, INC.,
`SAMSUNG TELECOMMUNICATIONS AMERICA, LLC AND
`AMAZON.COM, INC.
`Petitioners
`
`v.
`
`MEMORY INTEGRITY, LLC
`Patent Owner
`
`U.S. Patent No. 7,296,121
`
`
`
`Inter Partes Review Case No. 2015-00163
`
`
`
`MEMORY INTEGRITY, LLC’S PATENT OWNER
`RESPONSE PURSUANT TO 37 CFR § 42.120
`
`
`
`
`
`

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`Patent No. 7,296,121
`IPR2015-00163
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`TABLE OF CONTENTS
`
`
`I. INTRODUCTION .................................................................................................. 1 
`
`II. MEMORY INTEGRITY’S CLAIM CONSTRUCTIONS ................................... 1 
`
`A. 
`
`B. 
`
`C. 
`
`“states” ..................................................................................................... 2 
`
`“programmed” ....................................................................................... 12 
`
`“read response data” .............................................................................. 19 
`
`III. PETITIONERS HAVE NOT MET THEIR BURDEN TO SHOW
`UNPATENTABILITY OF THE INSTITUTED CLAIMS........................... 20 
`
`A.  Petitioners Failed to Demonstrate That Koster Anticipates Claims
`4-6 and 11-12 ......................................................................................... 20 
`
`1.  Koster Does Not Disclose “Probe Filtering Information
`Representative Of States Associated With Selected Ones Of
`The Cache Memories” As Required By Claims 4-6 and 11-12 .... 21 
`
`2.  Koster Does Not Disclose That “Each Of The Processing
`Nodes Is Programmed To Complete A Memory Transaction
`After Receiving A First Number Of Responses” As Recited In
`Claims 11 and 12 ........................................................................... 25 
`
`3.  Koster Does Not Disclose “Temporary Storage Associated
`Therewith For Holding Read Response Data” As Recited in
`Claim 12 ........................................................................................ 30 
`
`B.  Petitioners Failed To Demonstrate That Claims 19-24 Are Obvious
`Over Koster In View of Smith .............................................................. 34 
`
`1.  The Petition Fails To Demonstrate That The Combination Of
`Koster And Smith Teaches The “Probe Filtering Information
`Representative Of States” Limitation Of Claims 19-24 ............... 34 
`
`IV. CONCLUSION .................................................................................................. 35
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`Patent No. 7,296,121
`IPR2015-00163
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`EXHIBIT LIST
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`
`
`Exhibit No.
`Memory Integrity-2001
`
`Description
`Plaintiff Memory Integrity, LLC’s Initial Identification
`of Asserted Claims And Accused Products, served on
`Petitioners in Memory Integrity LLC v. Amazon.com
`Inc., et al., Nos. 1:13-cv-01795, -01796, -01802,
`-01808 (D. Del. served Oct. 13, 2014)
`Excerpts from D. E. Culler, J. P. Singh, and A. Gupta
`PARALLEL COMPUTER ARCHITECTURE, pp. 279-280
`(1999)
`Sorin et al. , “Specifying and Verifying a Broadcast and
`a Multicast Snooping Cache Coherence Protocol,”
`IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED
`SYSTEMS, Vol. 13, No. 6, pp. 1-23(June 2002)
`Excerpts from Merriam-Webster’s Collegiate
`Dictionary (10th ed. 1999)
`Excerpts from David A. Patterson, et al., COMPUTER
`ORGANIZATION AND DESIGN (3d ed. 2005)
`Memory Integrity-2006  Declaration of Jonathan D. Baker in Support of Patent
`Owner’s Opposition to Petitioner’s Motion to Correct
`Exhibit 1007 Pursuant to 37 C.F.R. § 42.104(c) 
`Memory Integrity-2007  U.S. Patent Application No. 10/288,347 
`Memory Integrity-2008  U.S. Patent No. 7,107,408 to Glasco 
`Memory Integrity-2009  U.S. Patent No. 7,107,409 to Glasco
`Memory Integrity-2010 
`Sorin, et al., A PRIMER ON MEMORY CONSISTENCY AND
`CACHE COHERENCE (2011)
`Excerpts from D. E. Culler, J. P. Singh, and A. Gupta
`PARALLEL COMPUTER ARCHITECTURE, pp. 302, 307-310
`(1999)
`Excerpts from Microsoft Computer Dictionary (1999)
`Excerpts from Modern Dictionary of Electronics (7th
`ed. 1999)
`
`Memory Integrity-2002
`
`Memory Integrity-2003
`
`Memory Integrity-2004
`
`Memory Integrity-2005
`
`Memory Integrity-2011 
`
`Memory Integrity-2012 
`Memory Integrity-2013 
`
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`ii
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`Patent No. 7,296,121
`IPR2015-00163
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`Exhibit No.
`Memory Integrity-2014 
`
`Memory Integrity-2015 
`
`Description
`Excerpts from Merriam-Webster’s Collegiate
`Dictionary (10th ed. 1999)
`Excerpts from Laughton et al., ELECTRICAL ENGINEER’S
`REFERENCE BOOK, pp. 15/3 (16th ed. 2003)
`Memory Integrity-2016  Declaration of Vojin G. Oklobdzija, PhD in Support of
`Patent Owner’s Responses
`Curriculum Vitae of Vojin G. Oklobdzija, PhD
`
`Memory Integrity-2017 
`
`
`
`iii
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`TABLE OF AUTHORITIES
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`Patent No. 7,296,121
`IPR2015-00163
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`Page(s)
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`Cases
`CAE Screenplates, Inc. v. Heinrich Fiedler GmbH & Co. KG,
`224 F.3d 1308 (Fed. Cir. 2000) .......................................................................... 17
`
`Microsoft Corp. v. Proxyconn, Inc.,
`789 F.3d 1292 (Fed. Cir. 2015) ........................................................................ 2, 3
`
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005) (en banc) .......................................................... 16
`
`Therasense, Inc. v. Becton, Dickinson & Co.,
`593 F.3d 1325 (Fed. Cir. 2010) ........................................................ 23, 25, 26, 34
`
`Statutes
`
`35 U.S.C. § 316(e) ................................................................................................... 20
`
`Other Authorities
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`37 C.F.R. § 42.1(d) .................................................................................................. 20
`
`Jose Duato, et al., INTERCONNECTION NETWORKS – AN ENGINEERING
`APPROACH (1997) ............................................................................................... 32
`
`M.A. Laughton, et al., ELECTRICAL ENGINEER’S REFERENCE BOOK (2003) ........... 17
`
`MERRIAM-WEBSTER’S COLLEGIATE DICTIONARY .................................................... 15
`
`MICROSOFT COMPUTER DICTIONARY ................................................................. 14, 17
`
`MODERN DICTIONARY OF ELECTRONICS ................................................................... 15
`
`NEWTON’S TELECOM DICTIONARY (20th ed. 2004) ........................................... 13, 14
`
`Michael John Sebastian Smith, APPLICATION-SPECIFIC INTEGRATED CIRCUITS
`(1997) .................................................................................................................... 1
`
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`Patent No. 7,296,121
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`Sorin, et al., A Primer on Memory Consistency and Cache Coherence (2011) ........ 4
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`Sorin, et al., Specifying and Verifying a Broadcast and a Multicast Snooping
`Cache Coherence Protocol, by (2002) ................................................................. 5
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`I. INTRODUCTION
`Patent Owner Memory Integrity LLC (“Memory Integrity” or “MI”) submits
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`Patent No. 7,296,121
`IPR2015-00163
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`this Response to the Petition for Inter Partes Review (“the Petition”) of U.S. Patent
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`No. 7,296,121 (“the ’121 patent”) filed by the Petitioners, the Patent Trial and
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`Appeal Board (“the PTAB” or “the Board”) Decision on Institution of Inter Partes
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`Review (Paper No. 18, “Institution Decision”), and the Board’s Decision on
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`Request for Rehearing (Paper No. 22, “Rehearing Decision”). The Board
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`instituted review of claims 4-6, 11-12 and 19-24 (the “instituted claims”). In
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`particular, the Board instituted review of claims 4-6 and 11-12 as anticipated by
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`U.S. Patent No. 7,698,509 to Koster et al. (“Koster”), and claims 19-24 as obvious
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`over Koster in view of Michael John Sebastian Smith, APPLICATION-SPECIFIC
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`INTEGRATED CIRCUITS (1997) (“Smith”). As explained in more detail below, the
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`Petitioner’s arguments rely on incorrect claim constructions and inadequate
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`inherency theories. As such, the Petitioners have not carried their burden to
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`demonstrate by a preponderance of the evidence that the instituted claims are
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`unpatentable.
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`II. MEMORY INTEGRITY’S CLAIM CONSTRUCTIONS
`Memory Integrity proposes the following claim constructions for the
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`purposes of this inter partes review proceeding.
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`1
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`A.
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`“states”
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`The term “states” is recited in independent claims 1 and 16 of the ’121
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`Patent as part of the longer phrase “probe filtering information representative of
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`states associated with selected ones of the cache memories.” The term “states” is
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`also recited in independent claim 25 in the similar phrase “probe filtering
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`information . . . representative of states associated with selected ones of the cache
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`memories.”
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`In its decision on institution, the Board did not provide a specific
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`construction for “states,” but preliminarily determined that “states” in the claims of
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`the ’121 Patent are not limited to “cache coherence protocol states,” and that such
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`states may consist of mere presence. IPR2015-00163, Paper 18 (“Institution
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`Decision”) at 12. This was despite the fact that the Board determined that the term
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`“probe” in the claims should be construed as “a mechanism for eliciting a response
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`from a node to maintain cache coherency in a system.” Id. at 8. Patent Owner
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`submits, as further demonstrated in the declaration of Dr. Vojin Oklobdzija filed
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`herewith, that the appropriate construction of states is limited to cache coherence
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`states, and does not include mere presence.
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`As the Federal Circuit recently held, the Board may not “construe claims
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`during IPR so broadly that its constructions are unreasonable under general claim
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`construction principles.” Microsoft Corp. v. Proxyconn, Inc., 789 F.3d 1292 (Fed.
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`Cir. 2015). In particular, “giving claims their broadest reasonable interpretation
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`does not include giving claims a legally incorrect interpretation . . . [r]ather, claims
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`should always be read in light of the specification and teachings in the underlying
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`patent.” Id. (citations and quotations omitted). “Even under the broadest
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`reasonable interpretation, the Board’s construction cannot be divorced from the
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`specification and the record evidence and must be consistent with the one that
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`those skilled in the art would reach.” Id. “A construction that is unreasonably
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`broad and which does not reasonably reflect the plain language and disclosure will
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`not pass muster.” Id.
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`Patent Owner respectfully submits that the construction of “states”
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`advocated by Petitioners, as well as the construction adopted by the Board in its
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`decision on institution, are incorrect because they do not properly account for
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`important teachings of the ’121 Patent and are divorced from the particular
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`technical field from which the ’121 Patent arises—the field of cache coherency.
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`Indeed, the teachings of the ’121 Patent make it clear that its inventions are
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`directed to the specific field of cache coherency. Ex. 2016 (“Oklobdzija Decl.”) ¶¶
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`11-29. For example, from the very beginning of the “Background of the
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`Invention” section, the ’121 Patent states that “Data access in multiple processor
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`systems can raise issues relating to cache coherency.” IPR2015-00163, Ex. 1001
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`(“’121 Patent”) at 1:26-27. Similarly, the ’121 Patent describes the primary
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`problem to be solved as “to provide techniques for improving data access and
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`cache coherency in systems having multiple processors connected using point-to-
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`point links.” Id. at 2:39-42.
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`Petitioners argue that “states” in the ’121 Patent is not limited “even to a
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`particular group of states, such as standard coherence protocol states” but instead
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`may be “any modes or conditions of selected ones of the cache memories.” Pet. at
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`9-10. Petitioners’ construction relies primarily on a definition from a Merriam
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`Webster dictionary, a general purpose dictionary and generally ignores the
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`teachings of the ’121 Patent. Similarly, the Board’s decision on institution
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`primarily relied on the “Microsoft Computer Dictionary”—a technical dictionary
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`that is broadly directed to the entire field of computing rather than to the specific
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`technical fields at issue in the ’121 Patent. Oklobdzija Decl. ¶ 14.
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`As Dr. Oklobdzija opines, although “state” may have many broad and
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`different meanings in both general English usage, as well as in the general field of
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`computers, the term “state” connotes a specific meaning in the field of cache
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`coherency—a cache coherency state. Oklobdzija Decl. ¶ 15. As an example of
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`this, in one of the treatises on cache coherency, Sorin et al., A Primer on Memory
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`Consistency and Cache Coherence (2011), the author equates the term “state” with
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`cache coherence protocol states. For example, in a section on cache coherence
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`protocol states, the author merely labels the section “States” as the heading for the
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`section, and then immediately discusses various characteristics of cache coherence
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`states, such as validity, dirtiness, exclusivity, and ownership. Ex. 2010 at 88-89;
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`Oklobdzija Decl. ¶ 15. This treatise also states that “[m]any coherence protocols
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`use a subset of the classic five state MOESI model first introduced by Sweazey and
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`Smith” and that “[t]he MOESI states, although quite common, are not an
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`exhaustive set of stable states. . . . [t]here are many possible coherence states, but
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`we focus our attention in this primer on the well-known MOESI states.” Id. at 89-
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`91; Oklobdzija Decl. ¶ 15. This interchangeable use of the term “states” and
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`“coherence states” and, use of the term “state” alone to discuss the states of a
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`particular cache coherence protocol, demonstrates that the term “state” means a
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`cache coherence protocol state in the field of cache coherency.
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`Additionally, the usage of the term “state” also dates back to the filing of the
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`patent. For example, in Specifying and Verifying a Broadcast and a Multicast
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`Snooping Cache Coherence Protocol, by Sorin et al. (2002), the author states that
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`“[a] processor’s access to a cache block is determined by the state of that block in
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`its cache, and this state is generally one of the five MOESI (Modified, Owned,
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`Exclusive, Shared, Invalid) states.” Oklobdzija Decl. ¶ 16; IPR2015-00163, Ex.
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`2003 at 1. Again, this demonstrates that, in the field of cache coherency, the term
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`“state” is equated with and means a cache coherence protocol state.
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`The teachings of the ’121 Patent also demonstrate that the use of the term
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`“state” in the patent is directed to cache coherence protocol states. Oklobdzija
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`Decl. ¶ 17. For example, the ’121 Patent states that: “[A] coherence protocol can
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`contain several types of messages . . . includ[ing] . . . probes,” that “[p]robes are
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`used to query each cache in the system, and that “[t]he probe packet can carry
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`information that allows the caches to properly transition the cache state for a
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`specified line.” ’121 Patent at 9:21-29 (emphasis added). Here, the term “state” is
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`plainly described in the context of a “coherence protocol,” and the probe’s method
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`of maintaining coherency in this embodiment is to inform the cache how to
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`transition from one cache state to another. The reference to “transition[ing]” states
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`makes it clear that the relevant state is a cache coherence protocol state.
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`Oklobdzija Decl. ¶ 18_.
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`Similarly, the ’121 Patent explains that “[b]y using a coherence directory,
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`global memory line state information (with respect to each cluster) can be
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`maintained and accessed by a memory controller or a cache coherence controller in
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`a particular cluster.” ’121 Patent at 13:4-7 (emphasis added). Again, this section
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`does not specifically state that the “memory line state information” is referring to
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`states in a cache coherence protocol—that is because, as Dr. Oklobdzija opines,
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`one of skill in the art would already understand that the term “state” in a reference
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`discussing cache coherency would refer to cache coherence protocol states.
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`Oklobdzija Decl. ¶ 19. However, the passage would make no sense if a
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`“coherence directory” was concerned with states other than coherence states. As
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`Dr. Oklobdzija opines, one of skill in the art would expect that if the phrase
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`“memory line state information” was referring to cache coherence protocol states
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`as well as other states, the patent would describe what those other “states” are—but
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`no description of “states” other than cache coherence protocol states is provided.
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`Id. Rather, the only thing described in the discussion of the coherence directory
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`using the term “states” are cache coherence protocol states.
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`Figures 7 and 8 are strongly illustrative that the ’121 Patent uses “state” to
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`mean cache coherence protocol states. In particular, in describing Figure 7, the
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`patent simply states “the coherence directory 701 includes state information 713”
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`and “[i]n some embodiments, the memory line states are modified, owned, shared,
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`and invalid.” ’121 Patent at 13:55-59 (emphasis added); Oklobdzija Decl. ¶ 20.
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`Again, the patent is equating the word “state” with coherence states. Moreover,
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`Figure 7 of the ’121 Patent itself shows that the “State” field of the “Coherence
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`Directory” stores the traditional cache coherence protocol states of “Invalid,”
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`“Shared,” “Owned,” and “Modified.” ’121 Patent at Fig. 7; Oklobdzija Decl. ¶ 20.
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`Additionally, presence is not a cache coherence protocol state and mere
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`presence should not be construed as satisfying the “state” limitation. As Dr.
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`Oklobdzija opines, there is no cache coherence protocol that operates with mere
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`presence as any state, and Dr. Oklobdzija does not believe any such protocol could
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`7
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`work. Oklobdzija Decl. ¶ 21. In addition, Dr. Oklobdzija opines that a cache
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`coherence protocol state is concerned with the states of lines which are stored in
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`the cache, but presence merely indicates whether a line is stored in cache. Id.
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`Dr. Oklobdzija’s opinions are confirmed and supported by the teachings of
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`the ’121 Patent. For example, the ’121 Patent teaches that “because the cache
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`coherence directory provides information about where [i.e., in which cluster the
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`line is present] memory lines are cached as well as their states, probes only need
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`be directed toward the clusters in which the requested memory line is cached” and
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`“[t]he state of a particular cached line will determine what type of probe is
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`generated.” ’121 Patent at 19:36-43 (emphasis added). This passage plainly
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`indicates not only that the “state” of a memory line is different from “where” the
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`memory line is (i.e. in which cluster it is present), but also that a “state” only exists
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`for a cached line, i.e., one that is stored in a cache. This confirms that the relevant
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`“state” as used in the ’121 Patent is a state of a line that is “cached,” i.e. it is
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`already known that the line is present in one of the caches. On the other hand, the
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`“state” provides additional information about “a particular cached line” that is
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`known to already be “somewhere” (i.e. it is already known to be present).
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`Oklobdzija Decl. ¶ 22. Dr. Oklobdzija also notes that because the cache coherence
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`directory is implemented using an associative memory in the ’121 Patent, if a line
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`were not present, searching the coherence directory’s associative memory for the
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`cache line’s tag would simply result in a cache miss, rather than returning some
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`particular row containing a state field. Oklobdzija Decl. ¶ 23. Thus, presence in a
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`cache is distinct from and a pre-condition to the existence of state for that cache
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`line. Id.
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`The ’121 Patent’s discussion of an “occupancy vector” also demonstrates
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`that the ’121 Patent does not consider mere presence to be a “state.” The ’121
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`Patent explains that “[a]ny mechanism for tracking what clusters hold a copy of the
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`relevant memory line in cache [i.e., in which clusters the memory line is present] is
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`referred to herein as an occupancy vector.” ’121 Patent at 14:2-4; Oklobdzija Decl.
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`¶ 24. The patent provides the example of the occupancy vector “implemented as
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`an N-bit string, where each bit represents the availability of the data in the cache of
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`N clusters.” ’121 Patent at 13:67-14:2. The ’121 Patent’s discussion of “state
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`information” and “occupancy vector” expressly treats them as different, stating that
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`“the coherence directory 701 includes state information 713, dirty data owner
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`information 715, and an occupancy vector 717 associated with the memory lines
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`711.” ’121 Patent at 13:55-57. The “State” field and the “Occupancy Vector”
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`field are also depicted as two different fields in the coherence directory in Figure 7
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`of the ’121 Patent. ’121 Patent at Fig. 7. It would be peculiar for the ’121 Patent
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`to refer to the “occupancy vector” and “state” in this way if the patent envisioned
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`the term “state” to also potentially include presence information. Oklobdzija Decl.
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`¶ 24. If “State” could include presence information, one would expect that Figure
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`7 would say “Protocol State” instead of “State” to make clear that the “Occupancy
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`Vector” also held the “state” for a line. But it does not, instead indicating that the
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`’121 Patent understands presence and “state” to be different, and that “state”
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`exclusively refers to cache coherence protocol states. Oklobdzija Decl. ¶ 24.
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`Figure 8 of the ’121 Patent also demonstrates that “states” refers to cache
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`coherence protocol states. Figure 8 shows “Probe filter information” and lists
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`various cache coherence protocol states of the MOSI protocol, corresponding to
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`the same states depicted in Figure 7’s “State” column. This demonstrates that the
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`claimed “probe filtering information representative of states associated with
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`selected ones of the cache memories” is referring to “probe filtering information
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`representative of” cache coherence protocol states, and not mere presence.
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`Petitioners and the Board rely on a couple of passages in the ’121 Patent as
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`supposedly supporting a broad construction of “state” not limited to cache
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`coherence protocol states. However, these passages do not support this
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`construction. First, the Board and Petitioners point to language in the patent that
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`states:
`
`Although the coherence directory 701 includes the four states of
`modified, owned, shared, and invalid [i.e., the MOSI protocol], it
`should be noted that particular implementations may use a different
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`set of states. In one example, a system may have the five states of
`modified, exclusive, owned, shared, and invalid [i.e., MOESI
`protocol]. The techniques of the present invention can be used with a
`variety of different possible memory line states.
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`See Institution Decision at 11 (quoting ’121 Patent at 14:30-36). However, as Dr.
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`Oklobdzija opines, because this passage should be read from the perspective of one
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`skilled in the art in the field of cache coherency, the reference to “a different set of
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`states” and a “variety of different possible memory line states” merely refers to
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`different sets of cache coherence protocol states—that is, the invention is not
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`limited to using the states of any specific cache coherence protocol. Oklobdzija
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`Decl. ¶ 26.1 This passage does not state or imply that states other than cache
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`coherence protocol states would be encompassed by the invention. Oklobdzija
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`Decl. ¶ 26. Importantly, all discussions and examples in the ’121 Patent of probe
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`filtering based on information representative of states discusses cache coherence
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`protocol states. Oklobdzija Decl. ¶ 26. Moreover, there is no evidence in the
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`record, including any opinions of Petitioners’ expert, explaining how such a system
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`could work. Oklobdzija Decl. ¶ 27.
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`The Board also draws attention to a passage stating that “According to a
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`1 Protocols with different sets of states from the MOESI states are known in the
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`field. An example is the Dragon protocol. Ex. 2010 at 302; Oklobdzija Decl. ¶ 28.
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`11
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`specific embodiment, the directory of shared states may be implemented as
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`described above with reference to FIGS. 7 and 8, and indicates where particular
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`memory lines are cached within the cluster.” See Institution Decision at 12
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`(quoting ’121 Patent at 28:29-34). The Board apparently interprets this language
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`to mean that the “states” “indicate where particular memory lines are cached.”
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`However, the phrase “indicates where particular memory lines are cached” is
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`modifying the term “directory,” not the term “states.” Oklobdzija Decl. ¶ 29. As
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`Figures 7 and 8 depict, in addition to “states,” the directory also stores “dirty data
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`owner” information and an “occupancy vector”—and it is those items, not “states”
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`which “indicate[] where particular memory lines are cached within the cluster.”
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`Oklobdzija Decl. ¶ 29. Indeed, as discussed above, the patent expressly
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`distinguishes “where” a cache line is from its “state,” explaining that: “the cache
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`coherence directory provides information about where [i.e., in which cluster the
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`line is present] memory lines are cached as well as their states.” ’121 Patent at
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`19:36-38.
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`Thus, the teachings of the ’121 Patent and the field of cache coherency as a
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`whole demonstrate that the term “state” in the ’121 Patent refers to cache
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`coherency states, and that mere presence is not a “state.”
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`B.
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`“programmed”
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`The term “programmed” is recited in claim 11 of the ’121 Patent as part of
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`the longer phrase “each of the processing nodes is programmed to complete a
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`memory transaction after receiving a first number of responses to a first probe.”
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`The Board, in its decision on institution in IPR2015-00163 did not adopt any
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`express construction of the term “programmed.” However, the Board did cite to a
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`definition from NEWTON’S TELECOM DICTIONARY (20th ed. 2004) defining
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`“program” as “[i]nstructions given to a computer . . . to perform certain tasks.”
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`IPR2015-00163, Paper 18, at 21-22 n.7.
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`MI submits that the term “programmed” should be construed to refer to a
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`device that has been “configured by a sequence of instructions.” This construction
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`is consistent with the dictionary definition cited by the Board and is supported by
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`the ’121 Patent’s specification, additional dictionary definitions reflecting the
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`ordinary meaning of this term, and by an expert declaration.
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`The specification explains that the operating characteristics of the processing
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`nodes are set using programming. In particular, the specification explains that:
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`According to a specific embodiment, the processing nodes in a
`single cluster are programmed according to their normal setup rules
`with a few exceptions. First, the broadcast routing tables in each of the
`nodes are programmed such that the broadcasts initiated from each
`node go directly to the PFU rather than on all of the node interfaces.
`Second, the broadcast routing table in each node is programmed such
`that broadcasts originating from the PFU enter the node and are not
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`forwarded to any other node. Third, each node is programmed to
`expect only one or two probe responses instead of one from each node
`in the system. More specifically, each node is programmed to expect
`one probe response if the PFU contains temporary storage to hold
`dirty data, and two if it does not.”
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`’121 Patent at 28:8-24 (emphasis added). As another example, the specification
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`states that “As mentioned above, embodiments are contemplated in which the
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`requesting node is programmed to expect two responses from the PFU.” Id. at
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`29:1-3. The references in the patent to “programmed according to their normal
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`setup rules with a few exceptions” refers to the use of instructions executed by the
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`processing nodes to store values in certain configuration registers or other locations
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`to configure their operation. Oklobdzija Decl. ¶ 35. The specification confirms
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`this understanding when it discusses the use of JTAG handshake registers to
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`modify the routing tables. In particular, the specification explains that “routing
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`table entries can be written to the handshake registers 1908 for eventual storage in
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`routing tables1906a-1906c.” ’121 Patent at 27:67-28:2 (emphasis added).
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`Oklobdzija Decl. ¶ 35. Indeed, these JTAG handshake registers and routing tables
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`are located within the processing nodes as shown in Figure 19. Id.
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`Various dictionary definitions confirm the ordinary meaning of the term
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`“programmed.” For example, in its Decision on Institution, the Board cited a
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`definition from NEWTON’S TELECOM DICTIONARY (20th ed. 2004) which defined
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`“program” as “[i]nstructions given to a computer . . . to perform certain tasks.”
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`Patent No. 7,296,121
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`IPR2015-00163, Paper 18, at 21-22 n.7. In addition, the MICROSOFT COMPUTER
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`DICTIONARY defines “program” as “To create a computer program, a set of
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`instructions that a computer or other device executes to perform a series of actions
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`or a particular type of work.” Ex. 2012 at 359 (emphasis added). As a further
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`example, the MODERN DICTIONARY OF ELECTRONICS defines “program” as “1. A
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`sequence of instructions … 3. A prepared list of instructions written in a special
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`language or code, to be carried out in sequence by a computer or other
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`programmable device. 4. To design, write, and test such a set of coded
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`instructions.” Ex. 2013 at 590-91 (emphasis added). As yet a further example, the
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`MERRIAM-WEBSTER’S COLLEGIATE DICTIONARY defines “program” as a noun as
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`“6b: a sequence of coded instructions that can be inserted into a mechanism (as a
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`computer)” and as a verb as “3a: to insert a program for (a particular action) into
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`or as if into a mechanism.” Ex. 2014 at 931 (emphasis added). Notably, each of
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`these dictionary definitions defines “program” in terms of a set or sequence of
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`instructions.
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`Additionally, Dr. Oklobdzija explains that the broadest reasonable
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`interpretation of the term “programmed” in the context of the ’121 Patent refers to
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`a device that has been configured by a sequence of instructions. Oklobdzija Decl.
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`¶¶ 33-39. For example, such instructions may be in the form of machine
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`instructions, an assembly language program, or some other form of instructions,
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`such as microinstructions or microcode. Oklobdzija Decl. ¶ 33.
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`The Petitioners and Dr. Horst have not offered any opinion regarding the
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`meaning of the term “programmed.” However, the Petitioners may attempt to
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`argue that “programmed” should be construed to simply mean “configured”
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`without requiring the use of any sequence of instructions. However, the term
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`“programmed” cannot properly be construed as “configured” even under the
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`broadest reasonable interpretation standard. Oklobdzija Decl. ¶ 37. There are
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`many terms that can be used to refer generically to configuration without use of a
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`sequence of instructions. Examples of such terms are “configured,” “set up,”
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`“arranged,” etc. Id. In contrast, the term “programmed” indicates that some type
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`of “programming”, i.e., a sequence of instructions, has been used. Id.
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`Furthermore, the patentee used the word “configured” when the patentee meant
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`“configured.” Id. For example, claim 9 uses the term “configured” when it states
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`that the “routing table in each of the processing nodes being configured to direct
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`all of the probes to the probe filtering unit.” ’121 Patent at cl. 9 (emphasis added).
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`Similarly, claim 10 uses the term “configured” when it states that the “routing table
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`in each of the processing nodes is configured to direct all broadcasts to the probe
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`filtering unit.” Id. at cl. 10 (emphasis added). In contrast, the patentee used the
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`term “programmed” in claim 11. See id. at cl. 1