throbber
UNITED STATES PATENT AND TRADEMARK OFFICE
`
`In re Patent of: Morton et al.
`U.S. Patent No. 7,296,121
`Issue Date:
`Nov. 13, 2007
`Appl. Serial No.: 10/966,161
`Filing Date:
`Oct. 15, 2004
`Title: REDUCING PROBE TRAFFIC IN MULTIPROCESSOR SYSTEMS
`
`Case Nos. IPR2015-00158
`IPR2015-00159
`IPR2015-00163
`
`DECLARATION OF VOJIN OKLOBDZIJA, Ph.D.
`IN SUPPORT OF PATENT OWNER’S RESPONSES
`PURSUANT TO 37 C.F.R. § 42.120
`
`I, Vojin Oklobdzija,, hereby declare as follows:
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`1. My name is Dr. Vojin Oklobdzija. I submit this declaration in support
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`of Patent Owner’s Responses in IPR2015-00158, -00159, and -00163. I have been
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`asked to offer technical opinions relating to U.S. Patent No. 7,296,121 and the
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`alleged prior art and arguments presented by the Petitioners on the grounds which
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`were instituted, and the reasoning of the Board in the decisions on institution.
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`2.
`
`I received a Dipl. Ing. (equivalent to a Master’s in Electrical
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`Engineering in the U.S.) degree in Telecommunications and Electronics in 1971
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`from the University of Belgrade, Yugoslavia, followed by a Master’s in Computer
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`Science from the University of California, Los Angeles in 1978. I received a Ph.D.
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`in Computer Science with a minor in Electronics from the University of California,
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`Los Angeles in 1982.
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`3.
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`Following my Ph.D. graduation, I spent 9 years at IBM’s T.J. Watson
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`Research Center working on microprocessor architecture, development and design.
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`In my career at IBM, I worked on the early development of RISC (Reduced
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`
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`Patent No. 7,296,121
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`Instruction Set Architecture Computer) architecture and development of a new
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`processor generation for IBM. Most notably, I worked on the first commercial
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`RISC computer, IBM ROMP, as well as the first super-scalar microprocessor, IBM
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`RS/6000.
`4.
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`After leaving IBM, I have held a faculty (Full Professor) position at
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`the University of California, Davis; and visiting positions at the University of
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`California, Berkeley; Sydney University in Australia; EPFL in Switzerland; and
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`others. I have over 20 years of teaching experience, teaching courses in:
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`Computer Architecture, Computer Design, Digital Design, VLSI Circuits as well
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`as advanced post-graduate courses in Computer Architecture and Design. During
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`this time, I served as a consultant with members of the microprocessor industry
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`extensively and was a principal architect in the Siemens/Infineon TriCore
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`processor.
`5.
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`After retiring from the academia, I returned back to industry. In 2013,
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`I became a Senior Director of Microprocessor Development at Skyera Inc., a
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`startup company that was subsequently acquired by Hitachi Ltd. While working at
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`Skyera, I lead a team developing an on-chip processor array consisting of a grid or
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`256 processors, including development of its cache-coherency mechanism and its
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`fast cache memory hierarchy.
`6.
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`Currently I am President and CTO of my own startup company,
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`Silicon Analytics Inc. and I also work as a consultant. I am a named inventor on
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`15 issued U.S. Patents and a similar number of international patents. I have also
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`authored several books on microprocessor design, including a book titled
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`“Computer Engineering Handbook,” published by CRC Press in 2001, which won
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`the CHOICE Outstanding Academic Title Award for 2002, as well as “High
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`Performance Energy Efficient Microprocessor Design” published Springer in 2006.
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`I have attached a true and correct copy of my curriculum vitae as Exhibit 2017,
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`which further sets forth my qualifications.
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`7.
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`I have reviewed and am familiar with the content of U.S. Patent No.
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`7,296,121 (“the ’121 Patent”). Additionally, I have reviewed all of the prior art
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`which provides the basis for the grounds on which the Board has instituted
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`proceedings in IPR2015-00158, -00159, and -00163, including U.S. Patent
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`Application Publication Number 2002/0053004 to Pong (“Pong”), U.S. Patent No.
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`7,698,509 to Koster et al. (“Koster”), Jeffrey Kuskin, et al., The Stanford FLASH
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`Multiprocessor, PROCEEDINGS ON THE 21ST ANNUAL INTERNATIONAL
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`SYMPOSIUM ON COMPUTER ARCHITECTURE, IEEE (1994) (“Kuskin”),
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`Michael John Sebastian Smith, APPLICATION-SPECIFIC INTEGRATED
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`CIRCUITS (1997) (“Smith”), and U.S. Patent No. 7,315,919 to O'Krafka et al.
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`("O'Krafka"). I have also reviewed various other documents which are discussed
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`later herein. I have reviewed these and the other materials from the perspective of
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`one of ordinary skill in the art of the ‘121 Patent at the time of the ’121 Patent’s
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`November 4, 2002 effective filing date.
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`8.
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`I agree with the opinion of Dr. Horst in IPR2015-00159 and -00163,
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`Ex. 1014 (“Horst Decl.”) ¶ 8, that one of ordinary skill in the field of cache
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`coherency as of November 4, 2002 would have a at least a bachelor’s degree in
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`electrical engineering, computer engineering, or computer science, and at least two
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`years of experience in the design of multiprocessor systems.
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`9.
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`I have no financial interest in either party or in the outcome of this
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`proceeding. I am being paid for my work as an expert in these matters on an
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`hourly basis. My compensation is not dependent on the outcome of these
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`proceedings or the content of my opinions. My opinions, as explained below, are
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`based on my education, experience, and background in the fields discussed above,
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`and my review of the materials cited by Petitioners, and the other materials
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`discussed herein.
`10. This declaration is organized as follows:
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`I.
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`Terminology in the claims of the ’121 Patent (page 4);
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`II. Opinions regarding Koster and the Koster combinations (IPR2015-
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`00158 and -00163) (page 22);
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`III. Opinions regarding Pong and the Pong combinations (IPR2015-
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`00159) (page 34).
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`I.
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`THE LANGUAGE OF THE CLAIMS OF THE ’121 PATENT
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`A.
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`“States”
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`11. The term “states” is recited in independent claims 1 and 16 of the ’121
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`Patent as part of the longer phrase “probe filtering information representative of
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`states associated with selected ones of the cache memories.” The term “states” is
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`also recited in independent claim 25 in the similar phrase “probe filtering
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`information . . . representative of states associated with selected ones of the cache
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`memories.”
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`12. Dr. Horst, in IPR2015-00159 and -00163, Ex. 1014 (“Horst Decl.”),
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`opines that “states associated with selected ones of the cache memories’ would be
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`broad enough to cover ‘any modes or conditions of selected ones of the cache
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`memories.’” Horst Decl. ¶ 30. In particular, Dr. Horst opines that “the ‘121 patent
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`does not limit the term 'state' to a specific type of state, such as standard coherence
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`protocol states.” Id. ¶ 31. Dr. Horst also points to a definition in the Merriam
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`Webster dictionary, a general purpose dictionary, of state as a “mode or condition
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`of being.”
`13.
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`I also understand that the Board, in its decisions on institution in
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`IPR2015-00158, -00159, -00163 determined that “state” was not limited to “cache
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`coherence protocol states.” Although the Board did not adopt an express
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`construction of the term “state,” it held that “the term is not limited to cache
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`coherence protocol states and is broad enough to include the condition of
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`presence—i.e., what is stored in cache memory.” E.g., IPR2015-00163, Paper No.
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`18 at 12.
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`14.
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`It is my opinion that the constructions adopted by Dr. Horst and the
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`Board are inconsistent with the broadest reasonable construction of the term “state”
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`in the claims of the ’121 Patent from the perspective of one of ordinary skill in the
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`art informed by the specification and teachings of the patent. In particular, by not
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`construing “state” as cache coherency states, Dr. Horst and the Board divorce the
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`term “state” from its well understood meaning in the field of cache coherency and
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`the teachings of the specification of the ’121 Patent.
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`15. Although the term “state” may have many broad and different
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`meanings in general English usage, as well as in the specific field of computers,
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`the term “state” connotes a specific meaning in the context of the field of cache
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`coherency. In the field of cache coherency, the term “state” is understood to refer
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`to a “cache coherency state.” For example, in Sorin et al., A Primer on Memory
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`Consistency and Cache Coherence (2011), the author equates the term “state” with
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`cache coherency states. The table of contents of the Sorin book simply lists
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`“States” as a heading, even though the section is dedicated to talking about cache
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`coherency states. Ex. 2010 at xi. Additionally, the “states” section of the Sorin
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`book immediately begins discussing states, equating “states” with “cache
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`coherency states”:
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`Id. at 88. The Sorin book also teaches that “Many coherence protocols use a subset
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`of the classic five state MOESI model first introduced by Sweazey and Smith” and
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`that “The MOESI states, although quite common, are not an exhaustive set of
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`stable states. . . . There are many possible coherence states, but we focus our
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`attention in this primer on the well-known MOESI states.” Id. at 89-91. Again,
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`this language reflects that, in the field of cache coherency, “states” are understood
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`as referring to “cache coherency states.”
`16. Moreover, equating “states” with “cache coherency states” is not
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`new—it was also the usage of the term “states” in the field of cache coherency at
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`the time of the filing of the ’121 Patent. For example, in “Specifying and
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`Verifying a Broadcast and a Multicast Snooping Cache Coherence Protocol,” by
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`Sorin et al. (2002), states that “A processor’s access to a cache block is determined
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`by the state of that block in its cache, and this state is generally one of the five
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`MOESI (Modified, Owned, Exclusive, Shared, Invalid) states.” Ex. 2003 at 1.
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`17. Additionally, the teachings of the ’121 Patent both confirm that it is
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`firmly embedded in the specific field of cache coherency, and that it also uses the
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`term “state” to refer to cache coherence protocol states. The ’121 Patent confirms
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`that it is directed to the specific field of cache coherency from the very beginning
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`of the Summary of the Invention section, stating that:
`Data access in multiple processor systems can raise issues relating to
`cache coherency. Conventional multiple processor computer systems
`have processors coupled to a system memory through a shared bus. In
`order to optimize access to data in the system memory, individual
`processors are typically designed to work with cache memory. In one
`example, each processor has a cache that is loaded with data that the
`processor frequently accesses. The cache is read or written by a
`processor. However, cache coherency problems arise because multiple
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`copies of the same data can co-exist in systems having multiple
`processors and multiple cache memories.
`IPR2015-00159, Ex. 1001 (“’121 Patent”) at 1:26-38. Moreover, the’121 Patent
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`describes the primary problem to be solved as “to provide techniques for
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`improving data access and cache coherency in systems having multiple processors
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`connected using point-to-point links.” Id. at 2:39-42.
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`18. The ’121 Patent’s usage of the term “state” is consistent with “states”
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`meaning cache coherence protocol states. For example, the ’121 Patent describes
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`that:
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`[A] coherence protocol can contain several types of messages. In one
`example, a coherence protocol includes four types of messages; data
`or cache access requests, probes, responses or probe responses, and
`data packets. Data or cache access requests usually target the home
`node memory controller. Probes are used to query each cache in the
`system. The probe packet can carry information that allows the
`caches to properly transition the cache state for a specified line.
`Id. at 9:21-29 (emphasis added). This reflects that the “state” discussed in the ’121
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`Patent reflects the “state” of a memory line in a “[cache] coherence protocol.”
`19. Similarly, the ’121 Patent explains that “[b]y using a coherence
`directory, global memory line state information (with respect to each cluster) can
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`be maintained and accessed by a memory controller or a cache coherence
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`controller in a particular cluster.” ’121 Patent at 13:4-7 (emphasis added). Again,
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`this section does not specifically state that the “memory line state information” is
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`referring to states in a cache coherence protocol—that is because one of skill in the
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`art would already understand that the term “state” in a reference discussing cache
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`coherency would refer to cache coherence protocol states. However, it would
`make no sense for a “coherence directory” to be concerned with states other than
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`coherence states. Moreover, one of skill in the art would expect that if the phrase
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`“memory line state information” was referring to cache coherence protocol states
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`plus some other states, it would describe what those other states are—but no
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`description of “states” other than cache coherence protocol states is provided.
`20. Moreover, in describing Figure 7, the patent simply states that “the
`coherence directory 701 includes state information 713” and “[i]n some
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`embodiments, the memory line states are modified, owned, shared, and invalid.”
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`’121 Patent at 13:55-59 (emphasis added). This section does not say “cache
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`coherence protocol state information” because one of ordinary skill in the art
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`would already understand that, in the context of cache coherency, the relevant
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`states are cache coherent protocol states. Indeed, Figure 7 confirms that the “state
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`information” discussed in this passage is referring to cache coherence protocol
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`states, showing “Modified, “Owned,” “Shared, and “Invalid” states in the “State”
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`column of the “Coherence Directory.”
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`’121 Patent, Fig. 7.
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`21.
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`I also disagree with the conclusion of Dr. Horst and the Board that
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`“states” in the ’121 Patent includes the condition of mere presence. I am aware of
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`no such protocol, I do not believe that any such protocol exists, and I do not
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`believe that any such protocol could work. Additionally, as described above, I
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`believe that the term “state” in the ’121 Patent refers to cache coherency protocol
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`states. Furthermore, as explained below, the “state” of the ’121 patent is
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`concerned with the states of lines which are stored in the cache. By contrast,
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`presence information merely indicates whether a line is stored in the cache. The
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`teachings of the ’121 Patent confirm that mere presence is not a state.
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`22. For example, the ’121 Patent teaches that “because the cache
`coherence directory provides information about where [i.e., in which cluster]
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`memory lines are cached as well as their states, probes only need be directed
`toward the clusters in which the requested memory line is cached” and “[t]he state
`of a particular cached line will determine what type of probe is generated.” ’121
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`Patent at 19:36-43 (emphasis added). This passage confirms that the relevant
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`“state” as used in the ’121 Patent is a state of a line that is “cached,” i.e. it is
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`already known that the line is present in one of the caches, and the “state” provides
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`additional information about “a particular cached line.”
`23. This is also confirmed because the ’121 Patent discusses the cache
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`coherence directory, in which state information is stored, as implemented using an
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`“associative” memory. ’121 Patent at 19:46-50 (“The associative nature of the
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`cache coherence directory . . . ”). An “associative” memory permits directly
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`accessing the memory based on content, for example a cache tag, rather than
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`merely providing an address or index into the directory. The “state” information
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`and other information regarding a line are stored as fields in a row in the
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`associative memory which is associated with that tag. ’121 Pat. Fig. 7. However,
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`the “state” information for a line is only stored if the directory’s associative
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`memory has a row corresponding to the cache tag (i.e. the line is present therefore
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`there is a row, containing state information). If the line were not present in any of
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`the caches, searching for its tag would simply result in a miss in the search of the
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`directory’s associative memory. Thus, the teachings of the ’121 Patent regarding a
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`cache coherence directory confirm that if a line is not cached, there is no state
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`information about the line—i.e. presence in a cache is distinct from and a pre-
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`condition to the existence of state for that cache line.
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`24. The ’121 Patent further expressly confirms that it does not use the
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`term “state” to refer to mere presence because per-processing node presence
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`information is stored in an “occupancy vector” in the ’121 Patent. The ’121 Patent
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`explains that “[a]ny mechanism for tracking what clusters hold a copy of the
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`relevant memory line in cache is referred to herein as an occupancy vector.” ’121
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`Patent at 14:2-4. It provides the example of the occupancy vector “implemented as
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`an N-bit string, where each bit represents the availability of the data in the cache of
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`N clusters.” Id. at 13:67-14:2. Moreover, the ’121 Patent distinguishes the
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`“occupancy vector” from “state information.” For example, in describing Figure 7,
`the ’121 Patent states that “the coherence directory 701 includes state information
`713, dirty data owner information 715, and an occupancy vector 717 associated
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`with the memory lines 711.” Id. at 13:55-57. Furthermore, Figure 7 itself further
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`confirms that the mere presence information is not a state, depicting cache
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`coherency states—which are labeled “state information” as distinct from presence
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`information—labeled as the “occupancy vector.” The ’121 Patent would not
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`introduce the term “Occupancy Vector” if “State” already included “presence.”
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`Furthermore, the ’121 Patent would simply fail to operate if “state” was merely
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`presence.
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`’121 Patent, Fig. 71. Thus, the figure further confirms that presence information is
`distinct from the “state” of the “memory line,” as the only “State[s]” shown in Fig.
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`7 are cache coherency states.
`25. Figure 8 of the ’121 patent is also informative. Figure 8 shows how
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`probe filter information can be used to reduce the number of nodes that need to be
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`probed. Notably, in the column labeled “Probe Filter Information 821”, the entries
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`1
`In the rows for Address 781, and 791, the column “Dirty Data Owner”
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`instead provides the presence information. Because those lines are in the
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`“Modified” state, only one cluster has a valid copy of the cache line, and a “vector”
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`is not needed.
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`that are listed--“invalid”, “shared”, “owned,” and “modified” (MOSI protocol)—
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`exactly correspond with the entries in the “State” column of the coherence
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`directory of Figure 7. This further confirms that the “probe filter information
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`representative of states associated with selected ones of the cache memories” of the
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`claims refers to cache coherence states and not to occupancy or presence
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`information.
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`26.
`
`I understand that Dr. Horst and the Board draw particular attention to
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`a passage of the ’121 Patent stating that:
`Although the coherence directory 701 includes the four states of
`modified, owned, shared, and invalid [i.e., the MOSI protocol], it
`should be noted that particular implementations may use a different
`set of states. In one example, a system may have the five states of
`modified, exclusive, owned, shared, and invalid [i.e., MOESI
`protocol]. The techniques of the present invention can be used with a
`variety of different possible memory line states.
`See IPR2015-00159, Paper 12 (“Pong Institution Decision”) at 9 (quoting ’121
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`Patent at 14:30-36). The Board and Dr. Horst apprehend this passage’s statements
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`that the invention can be used with a “variety” of different possible memory line
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`states as supporting that the invention can be used with states other than cache
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`coherence protocol states. To the contrary, one of skill in the art would recognize
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`the phrase “a variety of different possible memory line states” as meaning “a
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`variety of different possible cache coherence protocol states” because the ’121
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`Patent is deeply connected to the field of cache coherency. Thus, this passage
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`merely states that the inventions of the ’121 Patent are not limited to the states of
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`any particular cache coherence protocol (e.g. MOSI, MOESI, etc.)—not that some
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`“state” other than a cache coherence protocol state can be used to practice the
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`invention.
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`27.
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`Indeed, neither this passage, nor anywhere else in the ’121 Patent,
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`describes probe filtering based on probe filtering information representative of
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`states other than cache coherence protocols states. Moreover, there is no
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`explanation from Dr. Horst or elsewhere in the record of how such a configuration
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`could work.
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`28. Moreover, the MOESI states are not the universe of all cache
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`coherency states. For example, the Dragon protocol, a well known cache
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`coherence protocol, uses a very different set of states than the MOESI states. In
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`the Dragon protocol, the cache coherence states are Exclusive, Shared-Clean,
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`Shared-Modified, and Dirty. Ex. 2011 at 302. The Dragon protocol has no
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`“Invalid” state.” Id. Thus, saying that “a variety of different possible memory line
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`states” can be used with the present invention, after mentioning the MOESI
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`protocol, is simply referring to the universe of different cache coherence
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`protocols—not states which are not cache coherence protocol states.
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`29.
`
`I also understand that the Board draws attention to a passage that
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`states:
`According to a specific embodiment, the directory of shared states
`may be implemented as described above with reference to FIGS. 7
`and 8, and indicates where particular memory lines are cached within
`the cluster.
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`See Pong Institution Decision at 8 (quoting ’121 Patent at 28:29-34). This passage
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`does not imply that “states” “indicates where particular memory lines are cached
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`within the cluster.” To the contrary, the phrase “indicates where . . .” is referring
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`to the “directory” which is depicted in Figures 7 and 8. As Figures 7 and 8 depict,
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`in addition to “states,” the directory also stores “dirty data owner” information and
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`an “occupancy vector”—and it is those items, not “states” which “indicate[] where
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`particular memory lines are cached within the cluster.” Interpreting this passage as
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`teaching that “states” “indicate where particular memory lines are cached” would
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`ignore the express teachings of the very figures that the passage is discussing, as
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`well as the knowledge of the field demonstrated by the articles and treatises
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`referenced above.
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`B.
`“Programmed”
`30. The term “programmed” is recited in claim 11 of the ’121 Patent as
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`part of the longer phrase “each of the processing nodes is programmed to complete
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`a memory transaction after receiving a first number of responses to a first probe.”
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`31. Dr. Horst, in IPR2015-00159 and -00163, does not offer any opinion
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`regarding the meaning of the term “programmed.” Similarly, Dr. Sorin, in
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`IPR2015-00158, does not offer any opinion regarding the meaning of the term
`
`“programmed.”
`32.
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`I also understand that the Board, in its decision on institution in
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`IPR2015-00163 did not adopt any express construction of the term “programmed.”
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`However, the Board did cite to a definition from NEWTON’S TELECOM DICTIONARY
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`(20th ed. 2004) defining “program” as “[i]nstructions given to a computer . . . to
`perform certain tasks.” IPR2015-00163, Paper 18 (“Koster Institution Decision”),
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`at 21-22 n.7.
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`33.
`
`It is my opinion that the broadest reasonable interpretation of the term
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`“programmed” in the context of the ’121 patent refers to a device that has been
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`configured by a sequence of instructions. For example, such instructions may be in
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`the form of machine instructions, an assembly language program, or some other
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`form of instructions, such as microinstructions or microcode.
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`34. My opinion regarding the broadest reasonable interpretation of this
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`term is based on my experience of how the term “programmed” is used by those
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`working in the field of computers and microprocessors, including those working in
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`the field of cache coherency.
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`35. My opinion is also based on my review of the ’121 patent and how the
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`term “programmed” is used in the patent. In several places, the specification of the
`
`patent describes how the processing nodes are “programmed.” For example, the
`
`specification states that:
`According to a specific embodiment, the processing nodes in a single
`cluster are programmed according to their normal setup rules with a
`few exceptions. First, the broadcast routing tables in each of the nodes
`are programmed such that the broadcasts initiated from each node go
`directly to the PFU rather than on all of the node interfaces. Second,
`the broadcast routing table in each node is programmed such that
`broadcasts originating from the PFU enter the node and are not
`forwarded to any other node. Third, each node is programmed to
`
`17
`
`

`
`Patent No. 7,296,121
`Case Nos. IPR2015-00158, -00159, -00163
`
`expect only one or two probe responses instead of one from each node
`in the system. More specifically, each node is programmed to expect
`one probe response if the PFU contains temporary storage to hold
`dirty data, and two if it does not.”
`IPR2015-00163, Ex.1001 at 28:8-24 (emphasis added). As another example, the
`
`specification states that “As mentioned above, embodiments are contemplated in
`which the requesting node is programmed to expect two responses from the PFU.”
`
`Id. at 29:1-3. Based on my understanding of the operation of processors, the
`
`references in the patent to “programmed according to their normal setup rules with
`
`a few exceptions” refers to the use of instructions executed by the processing nodes
`
`to store values in certain configuration registers or other locations to configure
`
`their operation. My understanding is further supported by the discussion in the
`
`specification regarding the use of JTAG handshake registers to modify the routing
`tables. The specification states that “routing table entries can be written to the
`
`handshake registers 1908 for eventual storage in routing tables1906a-1906c.” Id.
`
`at 27:67-28:2 (emphasis added). These JTAG handshake registers and routing
`
`tables are located within the processing nodes as shown in Figure 19.
`
`36. My opinion regarding the broadest reasonable interpretation of
`
`“programmed” is also consistent with the definition cited by the Board from
`NEWTON’S TELECOM DICTIONARY (20th ed. 2004) which defined “program” as
`“[i]nstructions given to a computer . . . to perform certain tasks.” Koster
`
`Institution Decision at 21-22 n.7.
`
`18
`
`

`
`Patent No. 7,296,121
`Case Nos. IPR2015-00158, -00159, -00163
`
`37.
`
`I have been asked to consider whether the broadest reasonable
`
`interpretation of “programmed” could encompass “configuration” without the use
`
`of any sequence of instructions. In my opinion, that would not be a reasonable
`
`interpretation of the term “programmed.” There are many terms that could be used
`
`to refer generically to configuration without use of a sequence of instructions.
`
`Examples of such terms are “configured,” “set up,” “arranged,” etc. In contrast,
`
`the term “programmed” indicates that some type of “programming”, i.e., a
`
`sequence of instructions, has been used. In fact, I note that some of the claims of
`
`the ’121 patent use the term “configured” such as claims 9 and 10, whereas claim
`
`11 uses the term “programmed.” The use of these different terms indicates that
`
`these terms are intended to have different meanings.
`
`38.
`
`I have also been asked to consider whether the broadest reasonable
`
`interpretation of “programmed” can encompass hardwired logic. Hardwired logic
`
`refers to a system where the sequence of operations is governed by the physical
`
`interconnection of the digital processing elements. See ELECTRICAL ENGINEER’S
`
`REFERENCE BOOK, edited by M.A. Laughton, et al. (2003). Ex. 2014 at 15/3. As
`
`such, hardwired logic does not involve the use of any “programming” or “sequence
`
`of instructions.” Accordingly, the broadest reasonable interpretation of
`
`“programmed” would not include hardwired logic.
`39. The distinction between hardwired logic and a programmable device
`
`is confirmed by the ELECTRICAL ENGINEER’S REFERENCE BOOK, edited by M.A.
`
`19
`
`

`
`Patent No. 7,296,121
`Case Nos. IPR2015-00158, -00159, -00163
`
`Laughton, et al. (2003). Ex.2014 at 15/3. With respect to hardwired logic, this
`
`book explains that:
`A digital system is considered to be hardwired if the sequence of
`operations is governed by the physical interconnection of the digital
`processing elements. For example, in hardwired logic systems the
`physical interconnections of the elements govern the routes by which
`data flows between the processing elements and thus the sequence of
`processing operations performed on the data. Conventionally, a
`hardwired system is considered to be inflexible because the design is
`specific to a particular processing function: if the processing function
`is changed, then the processing elements and their interconnections
`have to be altered.
`Id. at 15/3. In contrast, with respect to a programmable system, this book explains
`
`that:
`
`A digital system is considered to be genuinely programmable if a
`prescriptive program of instructions (i.e. software) can be used to
`control the data-processing function of the system. This type of
`system usually incorporates a general-purpose processing element
`which is programmed to implement a specific function in a
`predetermined way. The coded instructions are normally stored in the
`memory part of the system and the program forms an integral part of
`the system. The ability to define the function of the digital system by
`programming introduces considerable flexibility into the system
`because the programming operation can take place after the general-
`purpose digital elements have been designed.
`Id. The book goes on to explain that “Traditionally, hardwired logic has been used
`
`extensively to provide the control and interface logic for more complex digital
`
`20
`
`

`
`Patent No. 7,296,121
`Case Nos. IPR2015-00158, -00159, -00163
`
`components such as microprocessors and other very large scale integration (VLSI)
`
`devices.” Id.
`
`C.
`“Read Response Data”
`40. The term “read response data” is recited in dependent claim 12 of the
`
`’121 Patent as part of the longer phrase “temporary storage associated therewith
`
`for holding read response data from one of the cache memories.” The Apple
`
`Petitioners and Dr. Horst do not propose any interpretation of “read response data.”
`
`I also understand that the Board did not adopt a construction of this term.
`
`41.
`
`It is my opinion that the broadest reasonable interpretation of the term
`
`“read response data” in this limitation of the ’121 Patent refers to the data retrieved
`
`from a cache. The claim language itself refers to “read response data from one of
`
`the cache memories” Moreover, the specification of the ’121 Patent confirms this
`
`understanding when it explains that “[w]hile probes and probe responses carry
`information for mainta

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