APPLE 1034
`Apple et al. v. Memory Integrity
`IPR2015-00163
`
`
`Apple et al. v. Memory Integrity
`IPR2015-00163
`
`
`
`Summary of Amendment
`
`o Cache Coherency States
`
`for “wherein said states comprise cache coherency states of a
`cache coherence protocol, and wherein said cache
`coherence protocol includes at least a modified state, an
`exclusive state, a shared state, and an invalid state”
`
`o Protocol Interface
`
`9, “wherein said probe filtering unit is coupled to a coherent
`protocol interface and a non—coherent protocol interface”
`
`2
`
`
`
`
`
`Combination of Culler and Laudon
`
`MIPS R1000 Processor:
`
`(i.e.. Piurultty of Processing Nodes)
`
` Hypercube
`(i.e., point-to-point architecture)
`
`IPRZOIS-00159, Opposition to Motion to Amend (‘Paper 36) .at 12
`
`3
`
`
`
`Combination of Culler and Laudon
`
`
`
`L the probe filtering unit being operable to receive probes
`
`corresponding to memory lines from the processing nodes and to
`probes only to selected ones of the processing nodes I
`
`
`
`
`
`
`Processing Nodes
`Probes Correspond to
`Memory Lines
`{i_e,, Owners}
`_
`_
`_
`Probe Filtering Unit
`(|.e., Read Requests)
`
`(i.e., Home Hub)
`
`Selected Ones of the
`
`lPR2015'-00159, Opposition to Mo'tlon_t_o Amend (Paper 36) at 13
`
`4
`
`
`
`Combination of Culler and Laudon
`
`Local/Requesting Hub
`
`lPR2015-00159, Opposition to Motion to Amend (Paper 36) at 15
`
`5
`
`
`
`Combination of Culler and Laudon
`
`Remote Home Hub
`
`Doasnot
`receive request
`
`lPR2015-00159, Opposition to Motion to Amend (Paper 36) at 18
`
`6
`
`
`
`Summary of M|’s Arguments Against Origin
`
`1) Probe Not “Received From” Processor
`
`2) Not the Same Probe
`
`3) No Point-to-Point Connection
`
`4) No Separate Interfaces
`
`7
`
`
`
`Summary of M|’s Arguments Against Origin
`
`1) Probe Not “Received From” Processor
`
`- Ml argues that “the ‘hub’ is not a ‘probe filtering unit [] operable to
`receive probes .
`.
`. from’ a plurality of ‘processing nodes,’ because
`the hub receives the alleged ‘probe’ from another hub, not from a
`processing node.” Reply in Support of MTA (Paper 37) at 9.
`
`8
`
`
`
`Probes From” Processing Nodes
`
`(1) Probe Filtering Unit “Receives
`
`the probe filtering unit
`being operable to receive probes corresponding to memory
`lines from the processing nodes
`
`’121 Patent, Claim 26.
`
`lPR2015-00159, Opposition to Motion to Amend (Paper 36) at 12-19
`9
`
`9
`
`
`
`Selected Ones of the
`
`Probe Filtering Unit
`
`Processing Nodes
`“'e" owners) T’ P|'0be 3
`
`Probes Correspond to
`_ Memory Lines
`
`(|.e., Read Requests)
`
`Receives Probes From Requesting Processor
`
`
`
`(1) Origin Teaches Home Hub
`
`(Le. Home Hub:(/
`
`L3 5
`{L4 MB:
`
`S
`
`.
`
`Xbow
`
`IPR2015-00159, Opposition to Motion to Amend (Paper 36) at 13
`10
`
`10
`
`10
`
`
`
`(1) ’121 Patent Explicitly Describes “Receive[s] Probes From Processors” Encompassing Indirect Receipt
`
`the probe filtering unit being operable to receive probes corresponding to
`memory lines from the processing nodes
`
`“’121 Patent, Claim 26.
`
`Figure 1B
`
`to various
`.-lmcording.
`a cache coherence controller 230.
`embodiments.
`the cache coherence controller includes a
`
`roiocol en _'ne 305 201111 tired to handle ackeis such as
`
`
`
`The fimotinnalityr of the
`
`’121 Patent, 7:54-58.
`
`Processing
`Cluster 125
`
`Processing
`
`’121 Patent, FIG. 1B.
`
`See |PR2015-00159, Petitioner Motion for Observations (Paper 41) at 4-5
`11
`
`11
`
`
`
`Processing
`C'”5“' 12‘
`
`Processin
`
`Cluster 12?
`
`11
`
`
`
`“Receive[s] Probes From Processors” Via Remote PFU
`
`(1) ’121 Patent Explicitly Describes that a PFU
`
`Figure 2
`
`I Proce5sor202c -
`
`
`
`205°
`
`| no Switch 210
`[/0 215 -»——T
`
`’121 Patent, FIG. 2.
`
`See |PR2015-00159, Petitioner Motion for Observations (Paper 41) at 4-5
`12
`
`12
`
`12
`
`
`
`Summary of M|’s Arguments Against Origin
`
`2) Not the Same Probe
`
`MI argues that “there is nothing to suggest that what is sent by a
`requesting processor in Origin is even the same as what is received
`by the hub at the home node (such that one could argue that the hub
`is indirectly receiving a ‘probe’ ‘from’ a processing node-).” Reply in
`Support of MTA (Paper 37) at 9.
`
`13
`
`13
`
`
`
`Probes From” Processing Nodes
`
`(2) Probe Filtering Unit “Receives
`
`the probe filtering unit
`being operable to receive probes corresponding to memory
`lines from the processing nodes and to transmit the probes
`
`’121 Patent, Claim 26.
`
`lPR2015-00159, Opposition to Motion to Amend (Paper 36) at 12-19
`14
`
`14
`
`14
`
`
`
`(2) ’121 Patent Supports Changes to Probe Beyond
`Mere Formatting
`
`the probe filtering unit being operable to receive probes
`corresponding to memory lines from the processing nodes
`and to transmit the.probes
`
`’121 Patent, Claim 26.
`
`If, on the other hand. the directory lookup dctern1i11es the
`cache line 111:1}; be cached in the S}-'StEll1 {"2010)_. the PFU
`sends out 3 probe enly on links eerrespendi11g In the uersles
`
`that 111:-1}; CL‘}11I£Ii1l the cache line {_2I}l-1}+—
`
`’121 Patent (Ex. 1001) at 23:50-53.
`
`Compare IPR2015-00159, P0 Reply in Support of MTA (Paper 37) at 9-10.
`15
`
`15
`
`15
`
`
`
`(2) ’121 Patent Supports Changes to Probe Beyond
`Mere Formatting
`
`14. The computer system of claim 1 wherein the probe
`filtering unit is further operable to modify the probes such
`that the selected processing nodes transmit responses to the
`probes to the probe filtering unit.
`
`' ’121 Patent, Claim 14.
`
`lPR2015-00159, Petition (Paper 6) at 14, n. 3 (construing “the probes”)
`16
`
`16
`
`16
`
`
`
`(2) Origin Teaches Home Hub “Receives Probes From”
`
`Requesting Processor Consistent With ’121 Patent
`
`Probes correspond to
`D Memory Lmes
`
`Probe Filtering Unit
`
`Processing Nodes
`(i.e., Owners) T, probe 3
`
`Selected Ones of the
`
`(I.e., Read Requests)
`
`“'9' Home Hub,
`
`/
`
`H}:
`
`E;
`E
`5
`
`Mam
`"‘°‘”°"
`H-4 6}
`
`|PR2015-00159, Opposition to Motion to Amend (Paper 36) at 13
`17
`
`17
`
`17
`
`
`
`(2) Origin Teaches Requesting Processor Issues “Read Request”
`
`Selected Ones of the
`
`Probes correspond to
`D Memory Lmes
`
`(I.e., Read Requests)
`
`Probe Filtering Unit
`
`“'8' Home Hub,
`
`Processing Nodes
`(i.e., Owners) T, probe 3
`
`/'
`
` (1-4G}
`
`D
`
`|PR2015-00159, Opposition to Motion to Amend (Paper 36) at 13
`18
`
`18
`
`18
`
`
`
`Origin Teaches Requesting Processor Issues “Read Request”
`
`
`
`by the protocol. These buffers do not, however, hold the messa es themselves. There
`are two read request buffers (RRBS) that
`— two ‘write request buffers (WRBS) that track outstanding write requests,
`and two intervention request.buf1'ers (IRBS) that track incoming invalidation and
`
`intervention requests. Access to the three sets of buffers is through a single bus, so
`
`Culler Book (Ex. 1028) at 615.
`
`
`
`Another example is in the mechanisms used to keep track of and match incoming
`and outgoing requests and responses.A11
`- are given request. numbers, and responses carry these request numbers..as
`well. However, the processor itself does not know about request numbers, and it is
`
`Culler Book (Ex. 1028) at 617.
`
`See lPR2015-00159, Petitioner Motion for Observations (Paper 41) at 3
`19
`
`19
`
`19
`
`
`
`(2) Ml’s Expert Agrees that Requesting Processor
`
`Issues “Read Request”
`
`3
`
`4
`
`5
`
`6
`
`A _
`
`Q
`
`A
`
`And the PI stands for Processor Interface?
`
`That‘s correct.
`
`9
`
`I
`
`1-3'
`
`11
`
`:2
`
`3.3
`
`14
`
`IE
`
`1%
`
`I j
`
`Q
`
`hr.-:3 than these read requests are given
`
`rcqucst numhcrn?
`
`J‘-‘s
`
`Correct.
`
`I
`
`I
`
`1
`
`19 I-
`
`Transcript of Depo of Dr. Oklobdzija
`{EL 1032} at 73325. 176:9-19.
`
`IPR2015—00159, Petitioner Motion for Observations (Paper 41] at 3
`20
`
`20
`
`20
`
`
`
`(2) Processor’s Read Request Sent From Its Hub Chip to Home Hub Chip (i.e., the PFU)
`
`Selected Ones of the
`
`Probes correspond to
`D Memory Lmes
`
`(I.e., Read Requests)
`
`Probe Filtering Unit
`
`“'8' Home Hub,
`
`Processing Nodes
`(i.e., Owners) T, probe 3
`
`/'
`
`
`
`Mam
`memory
`“-4 G}
`
`g‘
`E
`5
`
`|PR2015-00159, Opposition to Motion to Amend (Paper 36) at 13
`21
`
`21
`
`
`
`
`
`(2) Processor’s Read Request Sent From Its Hub Chip
`to Home Hub Chip (i.e., the PFU)
`
`
`
`Handhng Read Requests
`
`*
`
`
` Suppose a processor issues a read that misses in its cache hierarchy. The address of
`
`the miss1-
`
`Culler Book (Ex. 1028) at 599.
`
`|PR2015-00159, Opposition to Motion to Amend (Paper 36) at 15
`22
`
`22
`
`22
`
`
`
`(2) Processor’s Read Request Sent From Its Hub Chip to Home Hub Chip (i.e., the PFU)
`
`Selected Ones of the
`
`Probes correspond to
`D Memory Lmes
`
`(I.e., Read Requests)
`
`Probe Filtering Unit
`
`“'8' Home Hub,
`
`Processing Nodes
`(i.e., Owners) T, probe 3
`
`/'
`
`
`
`|PR2015-00159, Opposition to Motion to Amend (Paper 36) at 13
`23
`
`23
`
`23
`
`
`
`(2) Processor’s Read Request Sent From Its Hub Chip
`
`to Home Hub Chip (i.e., the PFU)
`
`Exclusive. This is the most interesting case. If the home is not the owner of the
`block, the valid data for the block must be obtained from the owner and must
`find its way to the requestor as well as to the home (since theslate will change '
`
`—1f the home itself is the owner, then the home can simply
`
`Culler Book (Ex. 1028) at 599.
`
`|PR2015-00159, Opposition to Motion to Amend (Paper 36) at 16
`24
`
`24
`
`24
`
`
`
`(2) Format of Read Request is Irrelevant to Claims
`
`10
`
`I
`
`11
`
`12
`
`I —
`
`Transcript of Depo of Dr. Oklobdzija (Ex. 1032) at 53:10-12.
`
`8
`
`I
`
`9 —
`
`Transcript of Depo of Dr. Okiobdzija (Ex. 1032) at 53:4-9.
`
`lPR2015-00159, Petitioner Motion for Observations (Paper 41) at 2
`25
`
`25
`
`25
`
`
`
`(2) ’121 Patent Supports Changes in Format to Probe
`
`The ’121 patent’s language stating that—
` combined
`
`with the express disavowal of limitations on the term, leads us to conclude
`
`that the broadest reasonable construction of the term “probe filtering unit”
`
`IPR2015-00163, Institution Decision (Paper 18) at 15
`
`26
`
`26
`
`
`
`(2) ’121 Patent Supports Changes in Format to Probe
`
`- Each cluster of processors includes a cache cohere-11cc
`co11trollr:r used to handle coxluntulications between clusters.
`
`’121 Patent (Ex. 1001) at 4:54-59.
`
`oint-to- oint
`
`links ma‘
`
`‘ll on 2111'
`
`The
`
`
`
`protocol.
`
`
`
`oint-to- oint
`
`’121 Patent (Ex. 1001) at 6:22-23.
`
`See lPR2015-00159, Petitioner Motion for Observations (Paper 41) at 2-3
`27
`
`27
`
`27
`
`
`
`(2) ’121 Patent Supports Changes in Format to Probe
`
`Figure 2
`
`Remote Clusters
`
`200
`
`{-
`
`208a
`
`206:1
`
`Processor 2023j Coherence
`
`vita
`
`'
`
`-J"-"JCache .5:
` ? Con1:ro1ler230_
`
`no |
`iI
`
`
`
`II
`
`
`
`
`
`
`Processor 202::
`
`
`
`206c
`
`
`
`
`
`
`
`
`I
`
`2oac1—7;
`
`Processor 202d
`
`
`
`I/02l6
`
`204
`
`BIOS
`
`See |PR2015-00159, Petitioner Motion for Observations (Paper 41) at 2-3
`
`28
`
`28
`
`
`
`(2) ’121 Patent Supports Changes in Format to Probe
`
`Figure 1B
`
`’121 Patent, FIG. 1B.
`
`See lPR2015-00159, Petitioner Motion for Observations (Paper 41) at 2-3
`29
`
`29
`
`29
`
`
`
`(2) ’121 Patent Supports Changes in Format to Probe
`
`Transcript of Depo of Dr. Oklobdzija (Ex. 1032) at ?4:11-23.
`
`Q
`
` A
`
`I-—
`
`MR. SATJNDERS:
`
`C|&:-jc-x:I:i-can to f-:-rm.
`
`TE-HE HI THE-IE5‘: _
`
`Transcript of Depo of Dr. Oklobdzija (Ex. 1032) at 74:2-6.
`
`lPR2015-00159, Petitioner Motion for Observations (Paper 41) at 2-3
`so
`
`30
`
`30
`
`
`
`Summary of M|’s Arguments Against Origin
`
`3) No Point-to-Point Connection
`
`* Ml argues that “within a local node in SGI Origin, individual
`processors are connected to each other and to the hub chip by a
`‘SysAD bus.’ .
`.
`. Moreover, processors in separate nodes in the SGI
`Origin are not directly connected to each other, as required by the
`substitute claims and the express teachings of the ’121 Patent.”
`Reply in Support of MTA (Paper 37) at 10-11.
`
`31
`
`
`
`by a Point-to-Point Architecture
`
`(3) Processing Nodes Interconnected
`
`a plurality of processing nodes interconnected by a
`first point-to-point architecture
`
`’121 Patent, Claim 26.
`
`lPR2015-00159, Opposition to Motion to Amend (Paper 36) at 10-12
`32
`
`32
`
`32
`
`
`
`(3) Processing Nodes Of Origin Interconnected
`by a Point-to-Point Architecture
`
`
` Owner Node
`
`MIPS R1000 Processors
`
`(I.e., Plurulity of Processing Nodes)
`
` Hypercube
`(i.e., point-to-point architecture)
`
`|PR2015-00159, Opposition to Motion to Amend (Paper 36) at 12
`33
`
`33
`
`33
`
`
`
`(3) Processing Nodes of Origin Interconnected
`
`by a Point-to-Point Architecture
`
`for use in a computer system comprising
`a plurality of processing nodes interconnected by a first point-to-
`point architecture
`
`Point-to-Point Link Between
`
`Hub Chips (i.e., a Point-to-
`
`Point Architecture)
`
`Hfiocuuwsyuon
`
`
`32F and GQP Brlstlod Hyporcubu
`
`Figure 3
`
`See lPR2015-00159, Opposition to Motion to Amend (Paper 36) at 11
`(citing Dr. Horst’ 5 Opposition Decl. (Ex. 1031) at 1] 3)
`34
`
`34
`
`34
`
`
`
`
`
`(3) Ml’s Expert Agrees that Interconnection Network of
`Origin is a Point-to-Point Architecture
`
`Point-to-Point Link Between
`
`showing a cube connected in a point—to—point
`
`Hub Chips (i.e., a Point-to-
`
`architecture?
`
`Point Architectu re]
`
`Is this depiction in figure 3 on the left
`
`329 and up Bristlod Hypcrcubu
`
`Figure 3
`
`A
`
`MR. RUECKHEIM:
`
`I have no further
`
`questions, and I pass the witness to counsel for
`
`Sony.
`
`MR. BILLAH:
`
`I have no further questions.
`
`MR. RUECKHEIM: we're done.
`
`
`Dr. Oklobdzija Depo. Trans. (Ex. 1032) at 181:2-4 to 182:2.
`IPR2015-00159, Petitioner Motion for Observation (Paper 41) at 8.
`35
`
`35
`
`35
`
`
`
`
`
`(3) MI Focuses on SysAD Bus as Prohibitive.
`It Is Not.
`
`MIPS R1000 Processors
`
`(I.e.. Piurulity of Processing Nodes)
`
` Hypercube
`(i.e., point-to-point architecture)
`
`IPRZOIS-00159, Opposition to Motion to Amend (Paper 36) at 12
`
`36
`
`36
`
`
`
`’121 Patent Contrasts Point-to-Point with “Shared Bus”
`
`(3) What is a “Point-to-Point Architecture”?
`
`1'_IE_3l2.Jl-I:3I:I 1:3 I'..'£:'__1-l'.‘._h__ cmlhrcr tllr-H11
`
`pni11t-m- flint links.
`
`|1:-;ine
`
`
`
`
`
`
`multiplr: pmu:c::.=mn1 are 115:-d ::fiir:icu1tl;s in
`:3 ~.-Q,-'5!-en] sharing the I-3$.11TU:‘ mr:1111ury :-;pa1ce_ I’rnL3::t_=.1-wing, and
`
`’121 Patent (Ex. 1001) at 4:40-43.
`
`lPR2015—O0159, PO Reply in Support of MTA (Paper 37) at 10.
`
`37
`
`37
`
`37
`
`
`
`(3) What is a “Point-to-Point Architecture”? Culler Also Contrasts Point-to-Point with “Shared Bus”
`
`Scalable cache coherence is ty Jicall based on the concept of a directory. Since
`the state of a block in the caches
`be determined implicitly by placing a
`by the cache controllers, the idea is to
`maintain this state explicitly in a place——callcd a directoty—-where requests can go
`and look it up. Consider a simple example. Imagine that each cache—line—sized block
`
`
`
`
`
`Culler Book (Ex. 1028) at 554.
`Compare |PR2015-00159, P0 Reply in Support of MTA (Paper 37) at 10-11.
`
`38
`
`38
`
`
`
`(3) SysAD Bus Just a Physical Link, Not a Shared Snoopy Bus
`
`Overview of the Origin2000 Hardware
`
` just as $1 bus-based protocol was implemented out of
`bus transactions and state transitions. Let us now turn our attention to the actual
`
`Culler Book (Ex. 1028) at 612.
`Compare lPR2015-00159, P0 Reply in Support of MTA (Paper 37) at 10-11.
`
`viding substantial bandwidth per processor.
`
`L.)
`
`1.
`
`J
`
`L
`
` and chose not to maintain snooping coherence
`4
`.
`.3..-
`
`Culler Book (Ex. 1028) at 597.
`IPR2015-00159, Petitioner Opposition to MTA (Paper 36) at 11.
`
`While the two rocessors share the same bus connected to the Hub.
`
`they_ Instead the 0 crate as
`two separate processors multiplexed over the*
`(clone to save Hub pins). This is different from many other ccNU-
`
`Laudon Reference (Ex. 1030) at 242.
`Compare lPR2015-00159, PD Reply in Support of MTA (Paper 37) at 10-11.
`
`39
`
`39
`
`39
`
`
`
`Not Shared Snooping Bus
`
`(3) MP5 Expert Agrees 0rigin’s SysAD
`
`D
`
`A
`
`Q
`
`Communications would only go through these
`
`two points; correct?
`
`A
`
`Correct.
`
`10
`
`11
`
`12
`
`13
`
`14
`
`II D
`
`MR. SAUNDERS: Objection.
`
`Form-
`
`THE WITNESS: -
`
`Dr. Oklobdzija Depo. Trans. (Ex. 1032) at 103:2-14.
`
`lPR2015-00159, Petitioner Motion for Observation (Paper 41) at 6.
`
`40
`
`40
`
`
`
`Control Unit Meets Claimed Point-to-Point Architecture
`
`(3) MI Asserts Bus Between Single Processor and
`
`We respectfully disagree with your assertion that the Samsung products identified in the
`C‘on1plaint do not contain a point-to-point architecture and that Memory Integrity failed to
`conduct an ade uate re-filing investigation. As shown in Figure 1.1 of our letter re roduced
`
`
`
`
`
`
` See ‘I21 Patent. Fig. IB and 6:24-35.
`Further. the patent notes that the use of a switch as shown in Figure 1B is advantageous because
`it “allows implementation with fewer point-to—point links.” See id. at 6:28-30.
`
`"Redacted Letter of March 28,2014 from Memory lntegrity's
`Counsel to Samsung's Counsel" (Ex. 1016) at 1-2
`lPR2015-00159, Petition (Paper 1) at 7
`
`41
`
`
`
`Control Unit Meets Claimed Point-to-Point Architecture
`
`
`
`
`
`
`
`
`
`ache ine drrectory
`
`{D”‘’'‘°‘“°d 59“ T59
`
`RAMS)
`
`I
`
`T
`
`Y
`
`T
`
`T
`
`hstruc1aon.dota. and coherency buses
`
`hstruchon. data. and coherency buses
`
`Tag contro:
`
`
`
`Show Control Unt <SCU;
`
`point-to-point links
`
`
`
`
`
`
`(3) MI Asserts Bus Between Single Processor and
`
`Cortex-A9 l.lPCore
`
`
`
`Snoopfiler-mg
`
`
`
`
`Cache to
`cache transfers
`
`Accelerator
`coherency
`___________*____
`Pomgaucp;
`I.tas£or1 (optional; wth
`iophonnn
` address flemg capabilities
`See Figure 1.1 of the Cortex-A9 Reference Manual (annotations added in red).
`
`
`
`"Redacted Letter of March 28,2014 from Memory Inte-grity's
`Counsel to Samsung's CounseI" (Ex. 1016) at 1-2 (annotated in original)
`|PR2015-00159, Petition (Paper 1) at 7
`
`42
`
`42
`
`
`
`in Origin are Point-to-Point
`
`(3) All Links Between Processors
`
`for use in a computer system comprising
`a plurality of processing nodes interconnected by a first point-to-
`point architecture
`
`MIPS R100-O Processors
`
`[l.e.. Pluralitv of Processing Nodes}
`
`Hypercube
`[i.e., point-to-point architecture)
`
`
`
`|PR2015-00159, Opposition to Motion to Amend (Paper 36) at 12
`43
`
`43
`
`43
`
`
`
`(3) Origin System Consistent with ’121 Patent’s Usage
`
`of “Point-to-Point Architecture”
`
`According to various en1b0dimc-nts. teclmiqucs are pro-
`vided for increasing data access efliciency in a multiple
`rocessor svstem.
`
`By using
`
`'121 Patent (Ex. 1001) at 4:36-40.
`
`syslenl In IE0 adapters 216 and 220._
`
`‘ 2
`
`. The comiuter svstem of claim 1-
`
`’121 Patent (Ex. 1001) at 6053-57.
`
`3121 Patent (Ex. 1001), Claim 2.
`
`Compare IPR2015-00159, PO Reply in Support of MTA (Paper 37) at 10.
`44
`
`44
`
`44
`
`
`
`(3) M|’s Expert Agrees that Intervening Elements Don’t
`
`Break “Direct Connection”
`
`’121 Pat, Figs. 1B, 19, col.
`
`
`Dr. Oklobc|zija’s Reply Decl. at 1] 14 n. 4
`
`IPR2015-00159, PO Reply in Support of MTA (Paper 37) at 11.
`45
`
`45
`
`45
`
`
`
`Summary of M|’s Arguments Against Origin
`
`4) No Separate Interfaces
`
`- Ml argues that “nothing suggests that SGI Origin uses separate
`coherent and non-coherent protocol interfaces as opposed to shared
`coherentlnon-coherent interfaces, i.e. handling both coherent and
`non-coherent messages without any physical or logical separation of
`interfaces.” Reply in Support of MTA (Paper 37) at 11-12.
`
`46
`
`46
`
`
`
`A Non-Coherent Protocol Interface
`
`(4) A Coherent Protocol Interface and
`
`wherein said probe
`filtering unit is coupled to a coherent protocol interface and
`a non-coherent protocol interface
`
`’121 Patent, Claim 26.
`
`lPR2015-00159, Opposition to Motion to Amend (Paper 36) at 20-22
`47
`
`47
`
`47
`
`
`
`Protocol Interfaces
`
`(4) ’121 Patent’s Limited Description of
`
`The cache cnhermcu L:unt_ml]cr h_.u:-: an. .i.nlcr_f:icc such as.
`
`cuhe1’em'.'e C01'l'll'i.‘.Illv£-.‘I' can also include other i11te1’l'ar:e:-; such
`
`Th»;-: cac.hL*.
`
`
` .-"Ln:':n;:1';1r{1'i1'1g_ I0 ‘H-'Lr'1r.:II.1:s
`
`i:r1'1budiII1i.:1"11;5;. L'.:lI.':l1
`
`’121 Patent (Ex. 1001) at 8:5-14.
`
`lPR2015-00159, P0 Motion to Amend (Paper 26) at 9-10
`48
`
`48
`
`48
`
`
`
`Coherent and Non-Coherent Interfaces
`
`(4a) Origin Processor Has Separate
`
`3. This is true for accesses that are under he ontrol of the coherence rotocol.
`it is the user's responsibility to insert syn-
`
`
`
`
`chronization to preserve a desired ordering in these cases.
`
`Culler Book (Ex. 1028) at 607.
`
`lPR2015-00159, Petitioner Opposition to MTA (Paper 36) at 21.
`
`In all, the number of transaction types for coherent memory operations in the
`Ori
`in rotocol is 9 re uests, 6 invalidations and interventions, and 39 responses.
`uncached memory operations,-
`-and special synchronization support, the number of-transactions is 19 requests and
`14 replies (no invaliclations or interventions since there isno coherent caching) .J
`Culler Book (Ex. 1023) at 664.
`lPR2015-00159, Petitioner Opposition to MTA (Paper 36) at 21.
`
`49
`
`49
`
`49
`
`
`
`(4b) When Origin System Connected to Non-Coherent IIO
`
`Device, Interface With Device is Non-Coherent Interface \.I
`
`
`that allows multiple cards to plug into it.—
`— either
`or through coherent DMA operations. An [/0 device, too, can transfer I
`
`
`
`
`In}
`
`FIGURE 8.21
`
`Layout of the Hub chip. The mmbar at the LEIHFI E.L}H"il:‘(.lS like builers
`
`Culler Book (Ex. 1028) at 614, 616.
`
`IPR2015-00159, Petitioner Opposition to MTA (Paper 36) at 21
`
`50
`
`50
`
`
`
`(4b) When Origin System Connected to Non-Coherent IIO
`
`Device, Interface With Device is Non-Coherent Interface
`
`Q
`
`And the system we just discussed where you
`
`have
`
`MR. SAUNDERS: Objection.
`
`Form.
`
`THE WITH-°3SS=
`
`therefore, has no coherency because it's not cached,
`
`then what you're trying to say —-—
`
`and,
`
`Dr. Oklobdzija Depo. Trans. (Ex. 1032) at 126:9-22.
`
`IPR2015-00159, Petitioner Motion for Observation (Paper 41) at 8-9.
`
`51
`
`
`
`MI Sought Broad Construction in Motion to Amend, But
`
`Now Seeks Further Amendment Through Construction
`
`Ml Position in MTA Before Addressing Origin
`
`It should be understood rhat—
`
`- Nothing in the intrinsic record of tl1e ‘I21 Patent restricts the interfaces
`
`in that 1nai1ne1'.
`
`lPR2015-00163, PO Motion to Amend (Paper 32) at 24.
`
`Ml Position in Reply After Begin Forced to Address Origin
`
`‘non-coherent protocol inte1'face.”' Ex. 1031 T 7. But. nothing suggests that SGI
`
`ongm
`
`opposed to
`
`shared coherent/11011-eoherent interfaces, i.e. handling both coherent and non-
`
`coherent messages without an
`
`Ex.
`
`lPR2015-D0159, P0 Reply in Support of MTA (Paper 37) at 12.
`
`52
`
`52
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