`
`In re Patent of:
`
`Morton et a].
`
`US. Patent No.:
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`7,296,121
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`Case No. IPR2015—00161
`
`Issue Date:
`Appl. Serial No.:
`Filing Date:
`Title:
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`Nov. 13, 2007
`10/966,161
`Oct. 15, 2004
`REDUCING PROBE TRAFFIC IN MULTIPROCESSOR
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`Attorney Docket No.: 39521-0007IP2
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`SYSTEMS
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`Mail Stop Patent Board
`Patent Trial and Appeal Board
`US. Patent and Trademark Office
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`PO. Box 1450
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`Alexandria, VA 22313-1450
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`PETITION FOR INTER PARTES REVIEW OF UNITED STATES PATENT
`
`NO. 7,296,121 PURSUANT TO 35 U.S.C. §§ 311—319, 37 C.F.R. § 42
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`
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`Attorney Docket No 39521—0007IP2
`Case NO.IPR2015-0016l
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`TABLE OF CONTENTS
`
`II.
`
`III.
`
`MANDATORY NOTICES UNDER 37 C.F.R§ 42.8(a)(1) .......................... 1
`A. Real Party—In-Interest Under 37 C.F.R. § 42.8(b)(1) ............................... 1
`B. Related Matters Under 37 CPR. § 42.8(b)(2) ........................................ 1
`C. Lead And Back-Up Counsel and Service Information ............................ 2
`
`PAYMENT OF FEES — 37 CPR. § 42.103 .................................................. 2
`
`REQUIREMENTS FOR IPR UNDER 37 C.F.R. § 42.104 ........................... 2
`A. Grounds for Standing Under § 42.104(a) ................................................. 2
`B. Challenge Under § 42.104(b) and Relief Requested................................ 3
`C. Claim Construction under 37 C.F.R. §§ 42.104(b)(3) ............................. 4
`1.
`“processing node” (claims 1, 2, 8, 11, 14—16, 25) .......................... 5
`2.
`“interconnected by a first point—to—point architecture” (claims 1,
`16, 25) ............................................................................................. 6
`“probe” (claims 1—3, 6, 8—17, 19, 20, 22, 24, 25) ............................ 7
`“probe filtering information” (claims 1, 3, 6, 16, 25) ..................... 8
`“states associated with selected ones of the cache memories”
`
`3.
`4.
`5.
`
`(claims 1, 16, 25) ............................................................................ 9
`“transmit the probes only to selected ones of the processing
`nodes” (claims 1 and 16) .............................................................. 10
`“cache coherence controller” (claim 3) ........................................ 11
`“cache coherence directory” (claim 3) ......................................... 12
`“the probes” (claim 8) ................................................................... 13
`
`6.
`
`7.
`8.
`9.
`
`IV.
`
`SUMMARY OF THE ‘121 PATENT .......................................................... 14
`
`A. Brief Technology Overview ................................................................... 14
`B. Brief Description of the ‘ 121 Patent ...................................................... 17
`C. Summary of the Prosecution History of the ‘ 121 Patent ....................... 18
`
`MANNER OF APPLYING CITED PRIOR ART TO EVERY CLAIM FOR
`
`WHICH IPR IS REQUESTED, THUS ESTABLISHING A REASONABLE
`LIKELIHOOD THAT AT LEAST ONE CLAIM OF TIDE ‘121 PATENT IS
`
`UNPATENTABLE ....................................................................................... 19
`
`A. Chaiken Anticipates Claims 1—3, 8, 11, 14-16, 19, 20, 22, and 25 ........ 20
`1.
`Chaiken Anticipates Claim 1 ........................................................ 23
`2.
`Chaiken Anticipates Claim 2 ........................................................ 30
`3.
`Chaiken Anticipates Claim 3 ........................................................ 31
`4.
`Chaiken Anticipates Claim 8 ........................................................ 33
`5.
`Chaiken anticipates Claim 11 ....................................................... 34
`6.
`Chaiken Anticipates Claim 14 ...................................................... 35
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`Chaiken Anticipates Claim 15 ...................................................... 36
`7.
`Chaiken Anticipates Claim 16 ...................................................... 36
`8.
`Chaiken Anticipates Claims 19, 20, and 22 .................................. 39
`9.
`10. Chaiken Anticipates Claim 25 ...................................................... 40
`B. Chaiken in View of Duato Renders Claim 9 Obvious ............................ 48
`
`C. Chaiken in View of Smith Renders Claims 17-24 Obvious ................... 50
`
`VI.
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`REDUNDANCY ........................................................................................... 5 4
`
`VII. CONCLUSION ............................................................................................. 5 6
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`EXHIBITS
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`APPL—1001
`
`APPL- 1 002
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`APPL—1003
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`APPL—1004
`
`APPL—1005
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`US. Patent Number 7,296,121 to Morton et al. (“the ‘ 121 Pa—
`ten ”)
`
`Excerpts from the Prosecution History of the ‘ 121 Patent (“the
`Prosecution History”)
`
`US. Patent Application Publication Number 2002/0053 004 to
`Pong (“Pong”)
`
`David Chaiken et al. , “Directory—Based Cache Coherence in
`Large—Scale Multiprocessors,” Computer V01. 24, issue 9 (Jun
`1990) (“Chaiken”)
`
`Daniel Lenoski er al. , “The Directory-Based Cache Coherence
`Protocol for the DASH Multiprocessor,” ISCA ‘90 Proceedings
`ofthe 17th annual international symposium on Computer Ar-
`chitecture, pp. 148—159 (May 1990) (“Stanford DASH”)
`
`APPL—1006
`
`US. Patent Number 6,490,661 to Keller er al (“Keller”)
`
`APPL—1007
`
`APPL-1008
`
`Excerpts from Jose Duato et al. , INTERCONNECTION NETWORKS
`— AN ENGINEERING APPROACH (1997) (“Duato”)
`
`Michael John Sebastian Smith, APPLICATION—SPECIFIC INTE—
`GRATED CIRCUITS (1997) (“Smith”)
`
`APPL—1009
`
`US. Patent No. 7,698,509 to Koster el‘ al. (“Koster”)
`
`APPL-1010
`
`US. Patent No. 7,315,919 to O’Krafl<a et al. (“O’Kraflm”)
`
`APPL-lOll
`
`US. Patent No. 6,338,122 to Baumgartner ei a]. (“Baumgart—
`ner”
`
`iii
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`
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`APPL-1012
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`Anant Agarwal et 61]., “An Evaluation of Directory Schemes for
`Cache Coherence,” Conference Proceedings of 15th Annual In-
`ternational Symposium on Computer Architecture (1988)
`
`APPL—1013
`
`Louis G. Johnson, “Multiprocessors,” ECEN 6253 Lecture
`Notes (April 28, 2003)
`
`APPL—1014
`
`Declaration of Dr. Robert Horst
`
`APPL—lOlS
`
`APPL—1016
`
`APPL—1017
`
`APPL—1018
`
`APPL—1019
`
`Excerpts from Merriam—Webster's Collegiate Dictionary — 10th
`Ed. (2001)
`
`Redacted Letter of March 28, 2014 from Memory Integrity’s
`Counsel to Samsung’s Counsel in Memory Integrity LLC v.
`Samsung Electronics Co., Ltd. et al., Case No. 1:13—cv—01808—
`GMS, including “Response to Samsung’s Allegation of a Rule
`11 Violation”
`
`Luca Benini and Giovanni De Micheli, “Networks on chips: a
`new SoC paradigm,” Computer vol. 35, issue 1 (Jan. 2002)
`(“Benini”)
`
`“HyperTransportTM Technology I/O Link - A High—Bandwidth
`I/O Architecture” (Jul. 20, 2001) (“HyperTranspofi”)
`
`U.S. Publication No. 2005/0228952 to Mayhew et al. (“May—
`heW”)
`
`APPL—1020
`
`US. Patent No. 6,662,277 to Gaither (“Gaither”)
`
`APPL—1021
`
`RESERVED
`
`APPL— 1 022
`
`RESERVED
`
`APPL—1023
`
`RESERVED
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`iV
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`Attorney Docket No 39521—0007IP2
`Case No.1PR2015—00161
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`Apple Inc.; HTC Corporation and HTC America, Inc. (collectively “HTC”);
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`Samsung Electronics Co. Ltd, Samsung Electronics America, Inc., and Samsung
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`Telecommunications America, LLC (collectively “Samsung”); and Amazon.com,
`
`Inc. (collectively “Petitioners”) petition for Inter Partes Review (“IPR”) under 35
`
`U.S.C. §§ 311—319 and 37 C.F.R. § 42 ofclaims 1—3, 8, 9, 11 and 14—25 (“the
`
`Challenged Claims”) of US. Patent No. 7,296,121 (“the ‘121 Patent”). As eX—
`
`plained below, there exists a reaSonable likelihood that Petitioners will prevail in
`
`demonstrating unpatentability of at least one Challenged Claim based on teachings
`
`set forth in the references presented in this petition.
`
`I.
`
`MANDATORY NOTICES UNDER 37 C.F.R § 42.8(a)(l)
`
`A.
`
`Real Party-In-Interest Under 37 C.F.R. § 42.8(b)(1)
`
`Apple Inc.; HTC Corporation and HTC America, Inc. (collectively “HTC”);
`
`Samsung Electronics Co. Ltd, Samsung Electronics America, Inc., and Samsung
`
`Telecommunications America, LLC (collectively “Samsung”); and Amazon.com,
`
`Inc. (collectively “Petitioners”) are the real parties—in—interest.
`
`B.
`
`Related Matters Under 37 C.F.R. § 42.8(b)(2)
`
`Petitioners are not aware of any disclaimers, reexamination certificates or
`
`petitions for inter partes review for the ‘ 121 Patent. The ‘ 121 Patent is the subject
`
`of Civil Action Numbers 1:13—cv- 1795 (Del), 1:13—cv— 1796 (Del), 1:13-cv- 1797
`
`(Del), 1:13-cv— 1798 (Del), 1:13-cv— 1799 (Del), 1:13—cv— 1800 (Del), 1:13—cv—
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`1801 (Del), 1:13-cv— 1802 (Del), 1:13-cv— 1803 (Del), 1:13-cv— 1804 (Del),
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`1
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`1:13-cv— 1805 (Del.), 1:13—cv- 1806 (Del.), 1:13—cv— 1807 (Del.), 1:13—cv— 1808
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`(Del.), 1:13—cv- 1809 (Del.), 1:13-cv- 1810 (Del.), 1:13-cv- 1811 (Del.), all filed
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`November 1, 2013; and Civil Action Numbers 1:13—cv— 1981 (Del.), 1:13—cv- 1982
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`(Del.), 1:13-cv- 1983 (Del.), 1:13—cv— 1984 (Del.), all filed November 26, 2013.
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`Concurrently with this petition, Petitioners are filing three other petitions for
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`IPR (identified with attorney docket numbers IPR2015—00159, IPR2015-00163,
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`and IPR2015—00172) of the ‘121 Patent. The relationship between the limited
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`grounds presented in these four petitions is discussed in Section VI.
`
`C.
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`Lead And Back-Up Counsel and Service Information
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`Petitioners designate W. Karl Renner, Reg. No. 41,265, as Lead Counsel and
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`Roberto Devoto, Reg. No. 55,108, as Backup Counsel, both available at 3200 RBC
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`Plaza, 60 South Sixth Street, Minneapolis, MN 55402 (T: 202-783—5070; F: 202-
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`783-2331), or electronically by email at 1PR39521-0007IP2@fr.com.
`
`II.
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`PAYMENT OF FEES — 37 C.F.R. § 42.103
`
`Petitioners authorize the Patent and Trademark Office to charge Deposit Ac—
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`count No. 06—1050 for the fee set in 37 C.F.R. § 42.15(a) for this Petition and fur—
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`ther authorizes for any additional fees to be charged to this Deposit Account.
`
`111. REQUIREMENTS FOR IPR UNDER 37 C.F.R. § 42.104
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`A.
`
`Grounds for Standing Under § 42.104(a)
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`Petitioners each certify that the ‘ 121 Patent is available for IPR. The present
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`petition is being filed within one year of service of each of the complaints against
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`Petitioners, which was no earlier than November 1, 2013. None of the Petitioners
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`is barred or estopped from requesting this review on the below-identified grounds.
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`B.
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`Challenge Under § 42.104(b) and Relief Requested
`
`Petitioners request IPR of the Challenged Claims on the grounds set forth in
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`the table shown below, and requests that each of the Challenged Claims be found
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`unpatentable. An explanation of unpatentability under the statutory grounds identi—
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`fied below is provided in the form of detailed description that follows, indicating
`
`where each element can be found in the cited prior art, and the relevance of that
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`prior art. Additional explanation and support for each ground of rej ection is set
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`forth in EX. 1014, Declaration of Dr. Robert Horst.
`
`Ground 1
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`1-3, 8, 11, 14—16, 19, 20, 22, 25
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`§102: Chalken
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`
`
`
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`Ground 2
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`9
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`Ground 3
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`17-24
`
`§103: Chaiken and Duato
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`§103: Chaiken and Smith
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`The ‘ 121 Patent issued from US. patent application number 10/966,161,
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`which was filed as a continuation—in—part on October 15, 2004, and which includes
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`a claim of priority to US. Application No. 10/288,347, filed on November 4, 2002,
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`now Patent No. 7,003,633. Petitioners note that the claims ultimately granted in
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`the ‘ 121 Patent are not fully supported by the priority applicationl; the earliest ef—
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`fective filing date for those claims is therefore no earlier than October 15, 2004.
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`Chaiken, Duato and Smitheach qualify as prior art at least under 35 U.S.C. §
`
`102(b). Specifically, Chaiken (EX. 1004) was published in June 1990. Duato (EX.
`
`1007) and Smith (EX. 1008) were each published in 1997. Each of these refer-
`
`ences, therefore, were published more than a year before even the earliest pro—
`
`claimed priority date of the ‘ 121 Patent.
`
`C.
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`Claim Construction under 37 C.F.R. §§ 42.104(b)(3)
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`Each term of a claim subject to IPR is given its “broadest reasonable con—
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`struction in light of the specification of the patent in which it appears.” 2 37 CPR.
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`§ 42.100(b). Accordingly, for purposes of this proceeding only, Petitioners submit
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`constructions for the following terms, and submits that all remaining terms should
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`1 For example, the term “probe filtering unit” does not appear anywhere in the pri—
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`ority application, but there is extensive discussion about the probe filtering unit in
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`the ‘ 121 Patent beginning with the added Figure 18.
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`2 Because the standards of claim interpretation applied in litigation differ from
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`PTO proceedings, any interpretation of claim terms in this IPR is not binding upon
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`Petitioners in any litigation(s) related to the subject patent. See In re Zlez‘z, 13
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`USPQ2d 1320, 1322 (Fed. Cir. 1989).
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`be given their plain meaning.
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`1. “processing node” (claims 1, 2, 8, 11, 14-16, 25)
`
`The ‘ 121 Patent does not provide an explicit definition for the term “pro—
`
`cessing node.” However, on its face, the word “processing” indicates the presence
`
`of a “processor” and, in modifying the word “node” indicates that the node in-
`
`cludes or is otherwise associated with a processor. See Ex. 1014, {l 24. The ‘ 121
`
`Patent supports this notion in its description and usage of the terms “processor”
`
`and “node.” In particular, the ‘ 121 Patent notes that “the terms node and processor
`
`are often used interchangeably herein.” Ex. 1001, 6:52—54. “However, it should
`
`be understood that, according to various implementations, a node (e.g., processors
`
`202a-202d) may comprise multiple sub—units, e.g., CPUs, memory controllers, I/O
`
`bridges, etc.” EX. 1001, 6:54—57. FIG. 19 shows one exemplary implementation of
`
`such a processing node. See Ex. 1001, 27:25-28. Based on this example and the
`
`aforementioned description of “node” as encompassing, in some implementations,
`
`multiple subunits that may be processors (e.g., CPUs), the ‘ 121 Patent describes a
`
`processing node that includes at least one processor. See EX. 1014, 1] 24.
`
`The ‘121 Patent further describes these processing nodes as end—points with-
`
`in a larger interconnected system. Ex. 1001, 27:32—40. Indeed, independent claims
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`1, 16, and 25 recite the plurality of processing nodes as being “interconnected by a
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`first point-to—point architecture” and as being included in “a computer system” and,
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`hence, as being a computer subsystem. See EX. 1014, fl 25.
`
`The Baumgartner reference (US. Patent No. 6,338,122) (EX. 1011), which is
`
`in the same field of art as the ‘ 121 Patent, demonstrates common usage of the term
`
`“processing node,” and in doing so reveals that persons of skill would have under—
`
`stood the term in a manner consistent with the above—noted interpretation: “&
`
`cessing nodes 8a—8n may each include M (M 2 1) processors 10, a local intercon—
`
`nect 16, and a system memory 18...” (emphasis added). EX. 1011, 3217—19 and
`
`Fig. 1. See EX. 1014, 11 26.
`
`Accordingly, it is reasonable, for purposes of this proceeding in which the
`
`broadest reasonable construction standard applies, to consider the term “processing
`
`node” as broad enough to encompass “an interconnectable computer subsystem
`
`comprising at least one processor.” See EX. 1014, 11 22.
`
`2. “interconnected by a first point-to-point architecture”
`(claims 1, 16, 25)
`
`In a co-pending litigation, the Patent Owner has asserted that the term “in-
`
`terconnected by a first point—to—point architecture” reads on any system of proces—
`
`sors that uses point—to-point links and they have contrasted this with “a shared-bus
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`architecture.” See EX. 1016, pp. 1—2. In particular, in response to questions asked 7
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`about the scope of the claimed point-to-point architecture, the Patent Owner indi—
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`cated that the claimed point—to-point architecture is broad enough to cover Figure
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`1B of the ‘ 121 Patent by stating:
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`Indeed, this is consistent with what the ‘ 121 Patent shows in Figure
`
`1B, which the Patent's specification describes as a point-to-point ar—
`
`chitecture that can use the techniques of the patented invention. See
`
`‘121 Patent, Fig. 1B and 6:24-35. Further, the patent notes that the
`
`use of a switch as shown in Figure 1B is advantageous because it “al—
`
`lows implementation with fewer point—to—point links.”
`
`See id. at 2 (emphasis added).
`
`In View of the Patent Owner’s assertions, for purposes of this proceeding in
`
`which the broadest reasonable construction standard applies, it is appropriate to
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`construe the term “interconnected by a first point—to—point architecture” as broad
`
`enough to encompass “connected to each other using point-to—point links.”
`
`3. “probe” (claims 1—3, 6, 8-17, 19, 20, 22, 24, 25)
`
`The ‘ 121 Patent specification defines the term “probe” as a “mechanism for
`
`eliciting a response from a node to maintain cache coherency in a system.” EX.
`
`1001, 5:45—47 (“A mechanism for eliciting a response from a node to maintain
`
`cache coherency in a system is referred to herein as a probe”). Consistent with
`
`this definition, the ‘ 121 Patent specification uses the term probe broadly to de-
`
`scribe messages used for snooping cache, as well as messages that carry infor—
`
`mation for maintaining cache coherency in a system. EX. 1001, 5 :47—48 (“In one
`
`example, a mechanism for snooping a cache is referred to as a probe”) and 11—66—
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`67 (“any message for snooping a cache can be referred to as a probe”) and 11: 20—
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`23 (“While probes and probe responses carry information for maintaining cache
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`coherency in the system, read responses can cany actual fetched data”). See EX.
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`1 0 1 4, 11 27.
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`Accordingly, it is reasonable, for purposes of this proceeding in which the
`
`broadest reasonable construction standard applies, to consider the term “probe” as
`
`broad enough to encompass “a mechanism that elicits a response from a node to
`
`maintain cache coherency in a system.” See EX. 1014, 11 27.
`
`4. “probe filtering information” (claims 1, 3, 6, 16, 25)
`
`The ‘ 121 Patent defines the term “probe filtering information” as “[a]ny cri—
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`terion that can be used to reduce the number of clusters or nodes probed.” EX.
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`1001, 14:50-52 (“[a]ny criterion that can be used to reduce the number of clusters
`
`or nodes probed is referred to herein as probe filter information”). The ‘ 121 Pa-
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`tent uses the term probe filtering information consistent with this definition. For
`
`instance, when describing its figures, the ‘ 121 Patent specification points out that
`
`Fig. 8 shows a diagram representing probe filter information, and, consistent with
`
`its definition for that term, the ‘121 Patent specification points out that the Fig. 8
`
`probe filtering information “can be used to reduce the number of transactions in a
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`multiple or single cluster system.” EX. 1001, 14:48—50. Similarly, according to
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`claim 3, the probe filtering information may comprise a cache coherence directory
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`which includes entries corresponding to memory lines stored in the selected cache
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`memories. Ex. 1001, 31 :12-16. See EX. 1014, W 28-29.
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`Accordingly, it is reasonable, for purposes of this proceeding in which the
`
`broadest reasonable construction standard applies, to consider the term “probe fil—
`
`tering information” as broad enough to encompass “any criterion that can be used
`
`to reduce the number of clusters or nodes probed.” See Ex. 1014, 11 28.
`
`5. “states associated with selected ones of the cache
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`memories” (claims 1, 16, 25)
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`The ‘ 121 Patent does not provide an explicit definition for the term “states
`
`associated with selected ones of the cache memories.” In fact, the ‘ 121 Patent fails
`
`to limit the recited “states” to a specific type of state nor even to a particular group
`
`of states, such as standard coherence protocol states. See Ex. 1001, 14:3 0-3 6. To
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`illustrate, rather than limiting states to standard coherence protocol states, the ‘ 121
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`Patent notes that “[t]he techniques of the present invention can be used with a vari-
`
`ety of different possible memory line states.” See id.
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`Merriam Webster’s Dictionary defines the word “state” as “mode or condi—
`
`tion of being,” which is exemplified by presence. See Ex. 1015, pp. 1145, 919 (de—
`
`fining “presence” as “the fact or conditibn ofbeing present” (emphasis added)).
`
`The ‘ 121 Patent uses the term “state” consistent with this definition. For example,
`
`the ‘121 Patent describes that a “directory of shared states .
`
`.
`
`. indicates where par—
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`ticular memory lines are cached within the cluster.” Ex. 1001, 28:29—34.
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`Furthermore, the Chaiken reference (EX. 1004), which is in the same field of
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`art as the ‘ 121 Patent, uses the word “status” to reference state in a manner con—
`
`sistent with the above—noted interpretation, and, thus, further supports the assertion
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`that presence is one example of a type of state: “The full—map protocol uses direc—
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`tory entries with one bit per processor and a dirty bit. Each bit represents the status
`
`ofthe block in the corresponding processor’s cache (present or absent)” EX. 1004,
`
`p. 50.
`
`Accordingly, it is reasonable, for purposes of this proceeding in which the
`
`broadest reasonable construction standard applies, to consider the term “states as—
`
`sociated with selected ones of the cache memories” as being broad enough to en—
`
`compass “any modes or conditions of selected ones of the cache memories.” See
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`EX. 1014,1111 30—32.
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`6. “transmit the probes only to selected ones of the pro-
`cessing nodes” (claims 1 and 16)
`
`Independent claims 1 and 16 recite transmitting “probes only to selected
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`ones of the processing nodes.” Applying the broadest reasonable interpretation,
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`this phrase should be construed broadly enough to cover transmission of each
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`probe to one or more selected processing nodes. In particular, claims 1 and 16 re-
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`cite that multiple “probes” are transmitted to “selected ones of the processing
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`nodes.” Because the claims describe the transmission of multiple “probes” instead
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`of a single “probe,” the claim language does not require that a single probe be
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`transmitted to more than one selected processing node, despite the claims’ use of
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`the plural form of “selected ones.” See EX. 1014, 11 34. Rather, each probe could
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`be transmitted to a single selected processing node and still satisfy the require—
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`ments of claims 1 and 16. See id. For example, if probe A is transmitted to a se-
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`lected processing node X and probe B is transmitted to a selected processing node
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`Y, probes (i.e., probes A and B) are transmitted to selected ones of the processing
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`nodes (i.e., processing nodes X and Y) despite the distribution of the nodes among
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`plural processing nodes. See id.
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`Accordingly, it is reasonable, for purposes of this proceeding in which the
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`broadest reasonable construction standard applies, to consider the term “transmit
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`the probes only to selected ones of the processing nodes” as broad enough to en—
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`compass “transmit each of the multiple probes only to one or more selected pro—
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`cessing nodes.” See EX. 1014, W 33-34.
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`7. “cache coherence controller” (claim 3)
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`The ‘121 Patent defines the term “cache coherence controller” as any mech—
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`anism or apparatus that can be used to provide communication between multiple
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`processing nodes while maintaining cache coherence. See EX. 1001, 7:2-6. The
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`‘121 Patent uses the term cache coherence controller consistent with this defini—
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`tion. For instance, the ‘121 Patent specification points out with regard to Fig. 2,
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`which shows a diagram of a multiple processor cluster that includes a cache coher-
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`ence controller, the ‘121 Patent illustrates the cache coherence controller may be
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`connected to processors within the cluster and with other clusters of processors. In
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`such a configuration, “cache coherence controller 230 communicates with both
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`processors 202a—d as well as remote clusters using a point—to—point protocol.” EX.
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`1001, 7:10—12.
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`Though FIGS. 4-12 focus on such inter—cluster communications, the ‘ 121
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`Patent also describes the use of the cache coherence controller for filtering intra—
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`cluster communications. See EX. 1001, 25:24-57, 26:36-57; see also EX. 1014, 11
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`37. Specifically, the ‘ 121 Patent specification describes that “the filtering of
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`probes within a cluster, i.e., local probe filtering, may be implemented in systems
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`having multiple clusters as well as systems having a single cluster of processors.”
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`EX. 1001, 26:3 6—39. Thus, a cache coherence controller may filter probes between
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`clusters and/or between processors within a cluster. See EX. 1014, 11 37.
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`Accordingly, it is reasonable, for purposes of this proceeding in which the
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`broadest reasonable construction standard applies, to consider the term “cache co-
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`herence controller” as broad enough to encompass “any mechanism or apparatus
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`that can be used to provide communications between multiple processing nodes
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`while maintaining cache coherence.” See EX. 1014, 1111 35—3 7.
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`8. “cache coherence directory” (claim 3)
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`The ‘ 121 Patent does not provide an explicit definition of the term “cache
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`coherence directory,” but does describe that, “according to some embodiments, a
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`cache coherence directory is a mechanism that facilitates the tracking by that cache
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`coherence controller of where particular memory lines within its cluster’s memory
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`are being cached in remote clusters.” EX. 1001, 18:43—47. The ‘121 Patent uses
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`the term cache coherence directory consistent with this description. See EX. 1014,
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`11 38. For example, the ‘121 Patent describes that the cache coherence directory
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`“indicates the existence and location of any remotely cached copies of the
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`memory.” EX. 1001, 21:7—8.
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`Accordingly, it is reasonable, for purposes of this proceeding in which the
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`broadest reasonable construction standard applies, to consider the term “cache co-
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`herence directory” as broad enough to encompass “a mechanism that facilitates the
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`tracking of where particular memory lines are being cached.” See EX. 1014, {l 38.
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`9. “the probes” (claim 8)
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`Claim 8 recites that “each of the processing nodes is operable to transmit t3
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`REE only to the probe filtering unit” (emphasis added). The term “the probes”
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`employs the definite article “the,” which particularizes the subject “probes” by re—
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`ferring to an antecedent for that term. See NTP, Inc. v. Research in Motion, Ltd. ,
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`418 F. 3d 1282, 1306 (Fed. Cir. 2005). The only antecedent for “probes” is recit—
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`ed in independent claim 1, from which claim 8 depends. Claim 1 recites “a probe
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`filtering unit which is operable to receive prom corresponding to memory lines
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`from the processing nodes and to transmit the probes only to selected ones of the
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`processing nodes.” Ex. 1001, 3111—5. Thus, the term “the probes” recited in claim
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`8 explicitly refers to probes received by the probe filtering unit from the processing
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`nodes.
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`Notably, this means that claim 8 does not require the processing nodes to be
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`operable to send a_ll probes only to the probe filtering unit. Rather, claim 8 simply
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`requires that those probes received by the probe filtering unit from the processing
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`nodes be transmitted only to the probe filtering unit (as opposed to, for example,
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`the processing nodes broadcasting those probes received by the probe filtering unit
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`to other processing nodes).
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`IV.
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`SUMMARY OF THE ‘121 PATENT
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`A.
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`Brief Technology Overview
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`A shared—memory multiprocessor is a computer system in which multiple
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`processors share memory. See Ex. 1014, 11 12. Memory (and I/O devices) are
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`3 In interpreting this feature of claim 1, it is worth noting that dependent claim 14
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`of the ‘ 121 Patent clarifies that “the probes” transmitted to selected ones of the
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`processing nodes by the probe filtering unit need not be exact copies of the probes
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`received by the probe filtering unit but rather may instead be modified versions of
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`the probes received by the probe filtering unit.
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`shared by each of the processors Via a local interconnection network. Ex. 1013, p.
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`1. “Each processor has access to its own memory and all the memory of all the
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`other processors.” Id. “Memory becomes a common resource which must be
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`shared between execution threads running simultaneously (really simultaneously,
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`not time shared) on different processors in the multiprocessor system.” Id.
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`One way to increase the speed of a multiprocessor is to associate a cache
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`memory with each processor. See Ex. 1014, 11 13. Cache memories are signifi—
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`cantly faster than standard main memory (e.g., RAM and ROM). However, be—
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`cause cache memories have significantly smaller capacity than main memory, each
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`processor can use a cache memory to store a copy of only a portion of the data
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`stored in main memory (e.g., the portion most recently or most commonly accessed
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`by the processor). See id. Moreover, because threads are executed simultaneously
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`across the processors within the multiprocessor share memory, more than one pro—
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`cessor may store a copy of a particular memory location in its cache. See id.
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`Each of these simultaneously executed threads has the ability to cause its
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`processor to both load the data stored in its cache and store updates to the data
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`back into its cache. See id. at 11 14. As such, inconsistencies may arise between
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`copies of data that are stored in different of the cache memories. See id. For ex—
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`ample, in the case where multiple processors store a copy of a memory location in
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`their respective caches, one of the processors may update the copy stored in its
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`cache, causing the copy within the cache of that processor to become inconsistent
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`or incoherent with respect to non-updated copies of the data that remain in the
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`cache of other of the processors. See id. Because coherency is valued, the updated
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`copy of the memory location stored in the updating processor’s cache is known as
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`a “dirty” copy of the memory location, because it differs from what is in main
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`memory. See EX. 1012, p. 280; see also EX. 1014, 11 14. The other processors that
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`store stale copies of the now-updated memory location must be notified in some
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`manner of the existence of a dirty copy, and thus of an update, to prevent the other
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`processors from operating with/on that stale data. See EX. 1014, 11 14.
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`A number of schemes have been proposed for maintaining coherency be—
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`tween the caches within a shared—memory multiprocessor. See id. at 11 15. As de—
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`scribed in a 1988 paper that compares several of these schemes:
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`A cache coherency protocol is the mechanism by which the coherency
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`of the caches is maintained. Maintaining coherency entails taking spe-
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`cial action when one processor writes to a block of data that exists in
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`other caches. The data in the other caches, which is now stale, must be
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`either invalidated or updated with the new value, depending on the
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`protocol. Similarly, if a read miss occurs on a shared data item and
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`memory has not been updated with the most recent value (as would
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`happen in a copy-back cache), that most recent value must be found
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`and supplied to the cache that missed. These two actions are the es—
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`sence of all cache coherency protocols. The protocols differ primarily
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`in how they determine whether the block is shared, how they find out
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`Where block copies reside, and how they invalidate or update copies.
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`EX. 1012, p. 280.
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`Two classes of these cache coherency protocols are “snoopy-based” and “di—
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`rectory-based.” See id at 1] 16.
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`In snoopy—based protocols, “each cache in the sys—
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`tem must watch all coherency transactions to determine when consistency-related
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`actions should take place for shared data.” See id. On the other hand, directory-
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`based protocols, “keep a separate directmy associated with main memory that
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`stores the state of each block of main memory.” See id. This directory is refer-
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`enced and, if necessary, updated to account for coherency transactions that occur
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`and to tr