9.1 SCHEMATIC ENTRY
`
`329
`
`26
`
`5
`
`26
`
`26
`
`(a)
`
`19
`
`(b)
`
`D- "spade" D-
`
`exclusive-OR
`
`and
`"shovel"
`
`NAND
`
`FIGURE 9.1
`IEEE-recommended dimensions and their construction for logic-gate sym(cid:173)
`bols. (a) NAND gate (b) exclusive-OR gate (an OR gate is a subset).
`
`Figure 9.2 shows some pictorial definitions of objects you can use in a simple
`schematic. We shall discuss the different types of objects that might appear in an
`ASIC schematic first and then discuss the different types of connections.
`
`fanout = 2
`
`/
`
`carryout
`
`net fanout = 4
`
`net fanin =4
`
`connection
`
`inv1
`
`symbol
`OR
`
`net attribute:
`net name
`
`~or1
`instance attribute: cell fanin = 2 connector
`instance name
`
`GND
`
`1 --r- VDD
`
`FIGURE 9.2 Terms used in circuit schematics.
`
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`
`Schematic-entry tools for ASIC design are similar to those for printed-circuit
`board (PCB) design. The basic object on a PCB schematic is a component or
`device-a TTL IC or resistor, for example. There may be several hundred compo(cid:173)
`nents on a typical PCB. If we think of a logic gate on an ASIC as being equivalent to
`a component on a PCB, then a large ASIC contains hundreds of thousands of com(cid:173)
`ponents. We can normally draw every component on a few schematic sheets for a
`PCB, but drawing every component on an ASIC schematic is impractical.
`
`Hierarchical Design
`9.1.1
`Hierarchy reduces the size and complexity of a schematic. Suppose a building has
`10 floors and contains several hundred offices but only three different basic office
`plans. Furthermore, suppose each of the floors above the ground floor that contains
`the lobby is identical. Then the plans for the whole building need only show detailed
`plans for the ground floor and one of the upper floors. The plans for the upper floor
`need only show the locations of each office and the office type. We can then use a
`separate set of three detailed plans for each of the different office types. All these
`different plans together form a nested structure that is a hierarchical design. The
`plan for the whole building is the top-level plan. The plans for the individual offices
`are the lowest level. To clarify the relationship between different levels of hierarchy
`we say that a subschematic (an office) is a child of the parent schematic (the floor
`containing offices). An electrical schematic can contain subschematics. The subsche(cid:173)
`matic, in turn, may contain other subschematics. Figure 9.3 illustrates the principles
`of schematic hierarchical design.
`The alternative to hierarchical design is to draw all of the ASIC components on
`one giant schematic, with no hierarchy, in a flat design. For a modern ASIC contain(cid:173)
`ing thousands or more logic gates using a flat design or a flat schematic would be
`hopelessly impractical. Sometimes we do use flat netlists though.
`
`The Cell Library
`9.1.2
`Components in an ASIC schematic are chosen from a library of cells. Library ele(cid:173)
`ments for all types of ASICs are sometimes also known as modules. Unfortunately
`the term module will have a very specific meaning when we come to discuss hard(cid:173)
`ware description languages. To avoid any chance of confusion I use the term cell to
`mean either a cell, a module, a macro, or a book from an ASIC library. Library cells
`are equivalent to the offices in our office building.
`Most ASIC companies provide a schematic library of primitive gates to be
`used for schematic entry. The first problem with ASIC schematic libraries is that
`there are no naming conventions. For example, a primitive two-input NAND gate in
`a Xilinx FPGA library does not have the same name as the two-input NAND gate in
`an LSI Logic gate-array library. This means that you cannot take a schematic that
`you used to create a prototype product using a Xilinx FPGA and use that schematic
`to create an LSI Logic gate array for production (something you might very likely
`want to do). As soon as you start entering a schematic using a library from an ASIC
`
`347
`
`

`
`9.1 SCHEMATIC ENTRY
`
`331
`
`cell: HADD
`
`(a)
`
`multiple instances of
`the same cell
`cell: HADD ~ parent
`
`(b)
`
`cell: OR
`
`cell: INV
`instance: INV1
`cell: OR
`instance: OR1
`
`t 111
`4
`
`children
`
`cell:AND
`instance: and1
`instance: and2
`
`(d)
`
`cell: HADD
`instance: ha2
`(c)
`
`FIGURE 9.3 Schematic example showing hierarchical design. (a) The schematic of a half(cid:173)
`adder, the subschematic of cell HADD. (b) A schematic symbol for the half adder. (c) A sche(cid:173)
`matic that uses the half-adder cell. (d) The hierarchy of cell HADD.
`
`vendor, you are, to some extent, making a commitment to use that vendor's ASIC.
`Most ASIC designers are much happier maintaining a large degree of vendor inde(cid:173)
`pendence.
`A second problem with ASIC schematic libraries is that there are no standards
`for cell behavior. For example, a two-input MUX in an Actellibrary operates so that
`the input labeled A is selected when the MUX select input S = '0'. A two-input MUX
`in a VLSI Technology library operates in the reverse fashion, so that the input
`labeled B is selected when S = '0'. These types of differences can cause hard-to-find
`problems when trying to convert a schematic from one vendor to another by hand.
`These problems make changing or retargeting schematics from one vendor to
`another difficult. This process is sometimes known as porting a design.
`
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`
`Library cells that represent basic logic gates, such as a NAND gate, are known
`as primitive cells, usually referred to just as cells. In a hierarchical ASIC design a
`cell may be a NAND gate, a flip-flop, a multiplier, or even a microprocessor, for
`example. To use the office building analogy again, each of the three basic office
`types is a primitive cell. However, the plan for the second floor is also a cell. The
`second-floor cell is a subschematic of the schematic for the whole building. Now we
`see why the commonly accepted use of the term cell in schematic entry can be so
`confusing. The term cell is used to represent both primitive cells and subschematics.
`These are two different, but closely related, things.
`There are two types of macros for MGAs and programmable ASICs. The most
`common type of macro is a hard macro that includes placement information. A
`hard macro can change in position and orientation, but the relative location of the
`transistors, other layout, and wiring inside the macro is fixed. A soft macro contains
`only connection information (between transistors for a gate array or between logic
`cells for a programmable ASIC). Thus the placement and wiring for a soft macro can
`vary. This means that the timing parameters for a soft macro can only be determined
`after you complete the place-and-route step. For this reason the basic library ele(cid:173)
`ments for MGAs and programmable ASICs, such as NAND gates, flip-flops, and so
`on, are hard macros.
`A standard cell contains layout information on all mask levels. An MGA hard
`macro contains layout information on just the metal, contact, and via layers. An
`MGA soft macro or programmable ASIC macro does not contain any layout infor(cid:173)
`mation at all, just the details of connections to be made inside the macro.
`We can stretch the office building analogy to explain the difference between
`hard and soft macros. A hard macro would be an office with fixed walls in which
`you are not allowed to move the furniture. A soft macro would be an office with par(cid:173)
`titions in which you can move the furniture around and you can also change the
`shape of your office by moving the partitions.
`
`Names
`9.1.3
`Each of the cells, primitive or not, that you place on an ASIC schematic has a cell
`name. Each use of a cell is a different instance of that cell, and we give each
`instance a unique instance name. A cell instance is somewhere between a copy and
`a reference to a cell in a library. An analogy would be the pictures of hamburgers on
`the wall in a fast-food restaurant. The pictures are somewhere between a copy and a
`reference to a real hamburger.
`We represent each cell instance by a picture or icon, also known as a symbol.
`We can represent primitive cells, such as NAND and NOR gates, with familiar icons
`that look like spades and shovels. Some schematic editors offer the option of switch(cid:173)
`ing between these familiar icons and using the rectangular IEEE standard symbols
`for logic gates. Unfortunately the term icon is also often used to refer to any of the
`pictures on a schematic, including those that represent subschematics. There is no
`accepted way to differentiate between an icon that represents a primitive cell and
`
`349
`
`

`
`9.1 SCHEMATIC ENTRY
`
`333
`
`one that represents a subschematic that may be in tum a collection of primitive cells.
`In fact, there is usually no easy way to tell by looking at a schematic which icons
`represent primitive cells and which represent subschematics.
`We will have three different icons for each of the three different primitive offices
`in the imaginary office building example of Section 9.1.1. We also will have icons to
`represent the ground floor and the plan for the other floors. We shall call the common
`plan for the second through tenth floors, Floor. Then we say that the second floor is
`an instance of the cell name Floor. The third through tenth floors are also instances
`of the cell name Floor. The same icon will be used to represent the second through
`tenth floors, but each will have a unique instance name. We shall give them instance
`names: FloorTwo, FloorThree, ... , FloorTen. We say that FloorTwo through
`FloorTen are unique instance names of the cell name Floor.
`At the risk of further confusion I should point out that, strictly speaking, the
`definition of a primitive cell depends on the type of library being used. Schematic(cid:173)
`entry libraries for the ASIC designer stop at the level of NAND gates and other sim(cid:173)
`ilar low-level logic gates. Then, as far as the ASIC designer is concerned, the primi(cid:173)
`tive cells are these logic gates. However, from the view of the library designer there
`is another level of hierarchy below the level of logic gates. The library designer
`needs to work with libraries that contain schematics of the gates themselves, and so
`at this level the primitive cells are transistors.
`Let us look at the building analogy again to understand the subtleties of primi(cid:173)
`tive cells. A building contractor need only concern himself with the plans for our
`office building down to the level of the offices. To the building contractor the primi(cid:173)
`tive cells are the offices. Suppose that the first of the three different office types is a
`comer office, the second office type has a window, and a third office type is without
`a window. We shall call these office cells: CornerOffice, WindowOffice, and
`NoWindowOffice. These cells are primitive cells as far as the contractor is con(cid:173)
`cerned. However, when discussing the plans with a client, the architect of our build(cid:173)
`ing will also need to see how each offices is furnished. The architect needs to see a
`level of detail of each office that is more complicated than needed by the building
`contractor. The architect needs to see the cells that represent the tables, chairs, and
`desks that make up each type of office. To the architect the primitive cells are a
`library containing cells such as chair, table, and desk.
`
`Schematic Icons and Symbols
`9.1.4
`Most schematic-entry programs allow the designer to draw special or custom icons.
`In addition, the schematic-entry tool will also usually create an icon automatically
`for a subschematic that is used in a higher-level schematic. This is a derived icon,
`or derived symbol. The external connections of the subschematic are automatically
`attached to the icon, usually a rectangle.
`Figure 9.4(c) shows what a derived icon for a cell, DLAT, might look like (we
`could also have drawn this by hand). The subschematic for DLAT is shown in
`Figure 9.4(b). We say that the inverter with the instance name invl in the subsche-
`
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`334
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`
`LOW-LEVEL DESIGN ENTRY
`
`matic is a sub cell (or submodule) of the cell DLAT. Alternatively we say that cell
`instance invl is a child of the cell DLAT, and cell DLAT is a parent of cell instance
`invl.
`
`schematic
`cell library
`
`primitive
`cells
`
`internal node
`
`instance name ~
`Trigger
`
`connector
`
`(a)
`
`(b)
`
`external node
`
`name
`
`(c)
`
`FIGURE 9.4 A cell and its subschematic. (a) A schematic library containing icons for the
`primitive cells. (b) A subschematic for a cell, DLAT, showing the instance names for the prim(cid:173)
`itive cells. (c) A symbol for cell DLAT.
`
`Figure 9.S(a) shows a more complex subschematic for a 4-bit latch. Each primi(cid:173)
`tive cell instance in this schematic must have a unique name. This can get very tire(cid:173)
`some for large circuits. Instead of creating complex, but repetitive, subschematics
`for complex cells we can use hierarchy.
`Figure 9.S(b) shows a hierarchical subschematic for a cell FourBit, which in
`turn uses four instances of the cell DLAT. The four instances of DLAT in Figure 9 .S(b)
`have different instance names: Ll, L2, L3, and L4. Notice that we cannot use just
`one name for the four instances of DLAT to indicate that they are all the same cell. If
`we did, we could not differentiate between Ll and L2, for example.
`The vertical row of instances in Figure 9.S(b) looks like a vector of elements.
`Figure 9.5(c) shows a vectOl'ed instance representing four copies of the DLAT cell.
`We say the cardinality of this instance is 4. Tools normally use bold lines or some
`other distinguishing feature to represent a vectored instance. The cardinality infor(cid:173)
`mation is often shown as a vector. Thus L [1: 4] represents four instances: L [ 1],
`L [2], L [3], L [4]. This is convenient because now we can see that all subcells are
`identical copies of L, but we have a unique name for each.
`Finally, as shown in Figure 9.S(d) we can create a new symbol for the 4-bit
`latch, FourBi t. The symbol for FourBi t has a 4-bit-wide input bus for the four D
`inputs, and a 4-bit wide output bus for the four Q outputs. The subschematic for
`FourBit could be either Figure 9.S(a), (b), or (c) (though the exact naming of the
`inputs and outputs and their attachment to the buses may be different in each case).
`
`351
`
`

`
`9.1 SCHEMATIC ENTRY
`
`335
`
`vectored name
`
`~Lff~l!
`
`,-----
`
`vectored
`instance
`
`(c)
`
`bus
`width",
`
`.•
`
`~
`bU~~;
`
`Four~it
`
`(d)
`
`(a)
`
`(b)
`
`FIGURE 9.5 A 4-bit latch: (a) drawn as a flat schematic from gate-level primitives,
`(b) drawn as four instances of the cell symbol DLAT, (c) drawn using a vectored instance of
`the DLAT cell symbol with cardinality of 4, (d) drawn using a new cell symbol with cell name
`FourBit.
`
`We need a convention to distinguish, for example, between the inverter subcells,
`invl, which are children of the cell DLAT, which are in turn children of the cell
`FourBi t. Most schematic-entry tools do this by combining the instance names of
`the subcells in a hierarchical manner using a special character as a delimiter. For
`example, if we drew the subschematic as in Figure 9.S(b), the four inverters in
`FourBit might be named Ll. invl, L2. invl, L3. invl, and L4. invl. Once
`again this makes it clear that the inverters, invl, are identical in all four subcells.
`In our office building example, the offices are subcells of the cell Floor. Sup(cid:173)
`pose you and I both have corner offices. Mine is on the second floor and yours is
`above mine on the third floor. My office is 211 and your office is 311. Another way
`to name our offices on a building plan might be FloorTwo. 11 for my office and
`FloorThree.ll for your office. This shows that FloorTwo. II is a subcell of
`
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`
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`
`336
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`
`LOW-LEVEL DESIGN ENTRY
`
`FloorTwo and also makes it clear that, apart from being on different floors, your
`office and mine are identical. Both our offices have instance names 11 and are
`instances of cell name Corner.
`
`9.1.5
`Nets
`The schematics shown in Figure 9.4 contain both local nets and external nets. An
`example of a local net in Figure 9.4(b) is nl, the connection between the output ter(cid:173)
`minal of the AND cell andl to the OR cell orlo When the four copies of this circuit
`are placed in the parent cell FourBit in Figure 9.S(d), four copies of net nl are cre(cid:173)
`ated. Since the four nets named nl are not actually electrically connected, even
`though they have the same name at the lowest hierarchical level, we must somehow
`find a way to uniquely identify each net.
`The usual convention for naming nets in a hierarchical schematic uses the par(cid:173)
`ent cell instance name as a prefix to the local net name. A special character (, : I
`I # I for example) that is not allowed to appear in names is used as a
`I $ I
`delimiter to separate the net name from the cell instance name. Supposing that we
`drew the subschematic for cell FourBi t as shown in Figure 9 .S(b), the four differ(cid:173)
`ent nets labeled nl might then become:
`
`I
`
`•
`
`/
`
`FourBi t. Ll: nl
`
`FourBi t. L2 : nl
`
`FourBi t. L3: nl
`
`FourBit .L4 :nl
`
`This naming is usually done automatically by the schematic-entry tool.
`The schematic DLAT also contains three external nets: D, EN, and Q. The ter(cid:173)
`minals on the symbol DLAT connect these nets to other nets in the hierarchical level
`above. For example,
`the signal Trigger: f lag
`in Figure 9.4( c)
`is also
`Trigger. DLAT: Q. Each schematic tool handles this situation differently, and life
`becomes especially difficult when we need to refer to these nodes from a simulator
`outside the schematic tool, for example. HDLs such as VHDL and Verilog have a
`very precise and well-defined standard for naming nets in hierarchical structures.
`
`9.1.6
`Schematic Entry for ASICs and PCBs
`A symbol on a schematic may represent a component, which may contain compo(cid:173)
`nent parts. You are more likely to come across the use of components in a PCB sche(cid:173)
`matic. A component is slightly different from an ASIC library cell. A simple example
`of a component would be a TTL gate, an SN74LSOON, that contains four 2-input
`NAND gates. We call an SN74LSOON a component and each of the individual NAND
`gates inside is a component part. Another common example of a component would be
`a resistor pack-a single package that contains several identical resistors.
`In PCB design language a component label or name is a reference designator.
`A reference designator is a unique name attribute, such as R9 9, attached to each
`component. A reference designator, such as R99, has two pieces: an alpha prefix R
`and a numerical suffix 99. To understand the difference between reference designa(cid:173)
`tors and instance names, we need to look at the special requirements of PCB design.
`
`353
`
`

`
`9.1 SCHEMATIC ENTRY
`
`337
`
`PCBs usually contain packaged ASICs and other ICs that have pins that are sol(cid:173)
`dered to a board. For rectangular, dual-in-line (DIP) packages the pins are numbered
`counterclockwise from the upper-left corner looking down on the package.
`IC symbols have a pin number for each part in the package. For example, the
`TTL 74174 hex D flip-flop with clear, contains six parts: six identical D flip-flops.
`The IC symbol representing this device has six pinNumber attribute entries for the
`D input corresponding to the six possible input pins. They are pins 3, 4, 6, 11, 13,
`and 14.
`When we need a flip-flop in our design, we use a symbol for a 74174 from a
`schematic library, suppose the symbol name is dffClr. We shall assign a unique
`instance name to the symbol, CarryFF. Now suppose we need another, identical,
`flip-flop and we call this Bi tFF. We do not mind which of the six flip-flop parts in a
`74174 we use for CarryFF and Bi tFF. In fact they do not even have to be in the
`same package. We shall delay the choice of assigning CarryFF and Bi tFF to spe(cid:173)
`cific packages until we get to the PCB routing step. So at this point on our schematic
`we do not even know the pin numbers for CarryFF and Bi tFF. For example the D
`input to CarryFF could be pin 3, 4, 6, 11, 13, or 14.
`The number of wire crossings on a PCB is minimized by careful assignment of
`components to packages and choice of parts within a package. So the placement(cid:173)
`and-routing software may decide which part of which package to use for CarryFF
`and BitFF depending on which is easier to route. Then, only after the placement and
`routing is complete, are unique reference designators assigned to the component
`parts. Only at this point do we know where CarryFF is actually located on the PCB
`by referring to the reference designator, which points to a specific part in a specific
`package. Thus CarryFF might be located in IC4 on our PCB. At this point we also
`know which pins are used for each symbol. So we now know, for example, that the
`D-input to CarryFF is pin 3 of IC4.
`There is no process in ASIC design directly equivalent to the process of part
`assignment described above and thus no need to use reference designators. The
`reference-designator naming convention quickly becomes unwieldy if there are a
`large number of components in a design. For example, how will we find a NAND
`gate named X3146 in an ASIC schematic with 100 pages? Instead, for ASICs, we
`use a naming scheme based on hierarchy.
`In large hierarchical ASIC designs it is difficult to provide a unique reference
`designator to each element. For this reason ASIC designs use instance names to
`identify the individual components. Meaningful names can be assigned to low-level
`components and also the symbols that represent hierarchy. We derive the component
`names by joining all of the higher level cell names together. A special character is
`used as a delimiter and separates each level.
`Examples of hierarchical instance names are:
`
`cpu.alu.adder.andOl
`MotherBoard:Cache:RAM4:ReadBit4:Inverter2
`
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`
`Connections
`9.1.7
`Cell instances have terminals that are the inputs and outputs of the cell. Terminals
`are also known as pins, connectors, or signals. The term pin is widely used, but we
`shall try to use terminal, and reserve the term pin for the metal leads on an ASIC
`package. The term pin is used in schematic entry and routing programs that are pri(cid:173)
`marily intended for PCB design.
`
`c
`
`B
`
`A
`
`3
`21----t--'
`1 I----t---.
`o
`
`31---+-r4-------~
`21-----r~------~
`1 I-----j----------_j
`Ol----~--------_j
`
`(a)
`
`3
`2
`1
`0
`
`bus ripper
`
`DO?
`DO? D06
`D06 D03
`D05 D02
`D04 D05
`D04
`8
`D02
`D03 DOO
`D02 D03
`D01 D02
`DOO D01
`DOO
`(b)
`
`FIGURE 9.6 An example of the use of a bus to simplify a schematic. (a) An address
`decoder without using a bus. (b) A bus with bus rippers simplifies the schematic and reduces
`the possibility of making a mistake in creating and reading the schematic.
`
`Electrical connections between cell instances use wire segments or nets. We
`can group closely related nets, such as the 32 bits of a 32-bit digital word, together
`into a bus or into buses (not busses). If signals on a bus are not closely related, we
`usually use the term bundle or array instead of bus. An example of a bundle might
`be a bus for a SCSI disk system, containing not only data bits but handshake and
`control signals too. Figure 9.6 shows an example of a bus in a schematic. If we need
`to access individual nets in a bus or a bundle, we use a breakout (also known as a
`ripper, an EDIF term, or extractor). For example, a breakout is used to access bits
`0-7 of a 32-bit bus. If we need to realTange bits on a bus, some schematic editors
`offer something called a swizzle. For example, we might use a swizzle to reorder the
`bits on an 8-bit bus so that the MSB becomes the LSB and so on down to the LSB,
`which now becomes the MSB. Swizzles can be useful. For example, we can multi(cid:173)
`ply or divide a number by 2 by swizzling all the bits up or down one place on a bus.
`
`Vectored Instances and Buses
`9.1.8
`So far the naming conventions are fairly standard and easy to follow. However,
`when we start to use vectored instances and buses (as is now common in large
`
`355
`
`

`
`9.1 SCHEMATIC ENTRY
`
`339
`
`ASICs), there are potential areas of difficulty and confusion. Figure 9.7(a) shows a
`schematic for a 16-bit latch that uses multiple copies of the cell FourBi t. The buses
`are labeled with the appropriate bits. Figure 9.7(b) shows a new cell symbol for the
`16-bit latch with 16-bit wide buses for the inputs, D, and outputs, Q.
`
`(b)
`
`(c)
`
`vectored
`
`mismatch in
`cardinality
`
`mismatch in
`cardinality
`
`FourBit
`
`(a)
`
`FIGURE 9.7 A 16-bit latch: (a) drawn as four instances of cell FourBit; (b) drawn as a cell
`named SixteenBit; (c) drawn as four multiple instances of cell FourBit.
`
`Figure 9.7(c) shows an alternative representation of the 16-bit latch using a vec(cid:173)
`tored instance of FourBi t with cardinality 4. Suppose we wish to make a connec(cid:173)
`tion to expressly one bit, D 1 (we have used D 1 as the first bit rather than the more
`conventional DO so that numbering is easier to follow). We also wish to make a con(cid:173)
`nection to bits D9-D 12, represented as D[9: 12]. We do this using a bus ripper. Now
`
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`
`we have the rather awkward situation of bus naming shown in Figure 9.7(c). Prob(cid:173)
`lems arise when we have "buses of buses" because the numbers for the bus widths
`do not match on either side of a ripper. For this reason it is best to use the single-bus
`approach shown
`in Figure 9.7(b) rather than the vectored-bus approach of
`Figure 9.7(c).
`
`Edit-in-Place
`9.1.9
`Figure 9.7(b) shows a symbol sixteenBit, which uses the subschematic shown in
`Figure 9.7(a) containing four copies of FourBit, named NB1, NB2, NB3, and NB4
`(the NB stands for nibble, which is half of a word; a nibble is 4 bits for 8-bit words).
`Suppose we use the schematic-entry program to edit the sub cell NB1.Ll, which is an
`instance of DLAT inside NBl. Perhaps we wish to change the D latch to a D latch
`with a reset, for example. If the schematic editor supports edit-in-place, we can edit
`a cell instance directly. After we edit the cell, the program will update all the DLAT
`subcells in the cell that is currently loaded to reflect the changes that have been
`made.
`To see how edit-in-place works, consider our office building again. Suppose we
`wish to change some of the offices on each floor from offices without windows to
`offices with windows. We select the cell instance FloorTwo-that is, an instance of
`cell Floor. Now we choose the edit mode in the schematic-entry program. But wait!
`Do we want to edit the cell Floor, or do we want to edit the cell instance
`FloorTwo? If we edit the cell Floor, we will be making changes to all of the floors
`that use cell name Floor-that is, instances FloorTwo through FloorTen. If we
`edit the ceIl instance FloorTwo, then the second floor will become different from all
`the other floors. It will no longer be an instance of cell name Floor and we will
`have to create another cell name for the cell used by instance FloorTwo. This is like
`the difference between ordering just one hamburger without pickles and changing
`the picture on the wall that will change all future hamburgers.
`Using edit-in-place we can edit the cell Floor. Suppose we change some of the cell
`instances of cell name NoWindowOffice to instances of cell name WindowOffice.
`When we finish editing and save the cell Floor, we have effectively changed all of the
`floors that contain instances of this cell.
`Instead of editing a cell in place, you may really want to edit just one instance
`of a cell and leave any other instances unchanged. In this case you must create a
`new cell with a new symbol and new, unique cell name. It might also be wise to
`change the instance name of the new cell to avoid any confusion.
`For example, we might change the third-floor plan of our office to be different
`from the other upper floors. Suppose the third floor is now an instance of cell name
`FloorVIP instead of Floor. We could continue to call the third floor cell instance
`FloorThree, but it would be better to rename the instance differently, FloorSpecial
`for example, to make it clear that it is different from all the other floors.
`
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`9.1 SCHEMATIC ENTRY
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`341
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`Some tools have the ability to alias nets. Aliasing creates a net name from the
`highest level in the design. Local names are net names at the lowest level such as D,
`and Q in a flip-flop cell. These local names are automatically replaced by the appro(cid:173)
`priate top-level names such as Clockl, or Data2, using a dictionary. This greatly
`speeds tracing of signals through a design containing many levels of hierarchy.
`
`9.1.10 Attributes
`You can attach a name, also known as an identifier or label, to a component, cell
`instance, net, terminal, or connector. You can also attach an attribute, or property,
`which describes some aspect of the component, cell instance, net, or connector. Each
`attribute has a name, and some attributes also have values. The most common prob(cid:173)
`lems in working with schematics and netlists, especially when you try to exchange
`schematic information between different tools, are problems in naming.
`Since cells and their contents have to be stored in a database, a cell name fre(cid:173)
`quently corresponds (or is mapped to) a filename. This then raises the problems of
`naming conventions including: case sensitivity, name-collision resolution, dictionaries,
`handling of "common" special characters (such as embedded blanks or underscores),
`other special characters (such as characters in foreign alphabets), first-character
`restrictions, name-length problems (only 28 characters are permitted on an NFS com(cid:173)
`patible filename), and so on.
`
`9.1.11 Nellist Screener
`A surprising number of problems can be found by checking a schematic for obvi(cid:173)
`ously fatal errors. A program that analyzes a schematic netlist for simple errors is
`sometimes called a schematic screener or netiist screener. Errors that can be found
`by a netlist screener include:
`• unconnected cell inputs,
`• unconnected cell outputs,
`0. nets not driven by any cells,
`• too many nets driven by one cell,
`o nets driven by more than one celL
`The screener can work continuously as the designer is creating the schematic or
`can be run as a separate program independently from schematic entry. Usually the
`designer provides attributes that give the screener the information necessary to per(cid:173)
`form the checks. A few of the typical attributes that schematic-entry programs use
`are described next.
`A screener usually generates a list of errors together with the locations of the
`problem on the schematic where appropriate. Some editors associate an identifier, or
`handle, to every piece of a schematic, including comments and every net. Normally
`there is some convention to the assigned names such as a grid on a schematic. This
`works like the locator codes on a map, so that a net with Al as part of the name is in
`
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`CHAPTER 9
`
`LOW-LEVEL DESIGN ENTRY
`
`the upper-Ieft-hand corner, for example. This allows you to quickly and uniquely
`find any problems found by a screener. The term handle is a computer programming
`term that is used in referring to a location in memory. Each piece of information on
`a schematic is stored in lists in memory. This technique breaks down completely
`when we move to HDLs.
`Most schematic-entry programs work on a grid. The designer can control the
`size of the grid and whether it is visible or not. When you place components or wires
`you can instruct the editor to force your drawing to snap to grid. This means that
`drawing a schematic is like drawing on graph paper. You can only locate symbols,
`wires, and connections on grid points. This simplifies the internal mechanics of the
`schematic-entry program. It also makes the transfer of schematics between different
`EDA systems more manageable. Finally, it allows the designer to produce schematic
`diagrams that are cleaner in appearance and thus easier to read.
`Most schematic-entry programs allow you to find components by instance name
`or cell name. The editor may either jump to the component location and center the
`graphic window on the component or highlight the component. More sophisticated
`options allow more complex searches, perhaps using wildcard matching. For