throbber
UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`APPLE INC., HTC CORPORATION, HTC AMERICA, INC.,
`SAMSUNG ELECTRONICS CO. LTD, SAMSUNG ELECTRONICS AMER-
`ICA, INC., AMAZON.COM, INC., SONY CORP.,
`SONY ELECTRONICS INC., SONY MOBILE COMMUNICATIONS AB,
`SONY MOBILE COMMUNICATIONS (USA) INC.,
`LG ELECTRONICS, INC., LG ELECTRONICS USA, INC., AND
`LG ELECTRONICS MOBILECOMM USA, INC.,
`
`
`
`Petitioners,
`
`v.
`
`MEMORY INTEGRITY, LLC,
`Patent Owner.
`____________
`
`Case IPR2015-00159
`Patent 7,296,121
`____________
`
`
`
`
`
`
`
`PETITIONERS’ OPPOSITION TO
`PATENT OWNER MOTION TO AMEND
`PURSUANT TO 37 C.F.R. § 42.23
`
`
`
`

`
`
`Patent No. 7,296,121
`Petitioner’s Opposition to Patent Owner’s Motion to Amend
`
`
`Attorney Docket No. 39521-0007IP1
`IPR2015-00159
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`TABLE OF CONTENTS
`
`I. 
`
`INTRODUCTION .............................................................................................. 1 
`
`II.  MI’S MOTION TO AMEND FAILS TO COMPLY WITH 37 C.F.R. §
`42.20(C) ..................................................................................................................... 1 
`
`III.  SUBSTITUTE CLAIMS 26-34 ARE NOT ENABLED AND LACK
`WRITTEN DESCRIPTION ...................................................................................... 5 
`
`IV.  SUBSTITUTE CLAIMS 26-34 ARE NOT PATENTABLE OVER THE
`PRIOR ART ............................................................................................................... 6 
`
`A.  The Combination of the Culler Book and Laudon Renders Claims 26-28
`Obvious .............................................................................................................. 7 
`1. Claim 26 ...................................................................................................... 10
`2. Claims 27 and 28 ......................................................................................... 22
`
`B.  The Combination of the Culler Book, Laudon, and Smith Renders Claims
`29-34 Obvious .................................................................................................. 23 
`
`V.  CONCLUSION ................................................................................................ 25 
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`1
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`Patent No. 7,296,121
`Petitioner’s Opposition to Patent Owner’s Motion to Amend
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`EXHIBITS
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`Attorney Docket No. 39521-0007IP1
`IPR2015-00159
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`APPL-1031
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`Opposition Declaration of Dr. Robert Horst
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`2
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`Patent No. 7,296,121
`Petitioner’s Opposition to Patent Owner’s Motion to Amend
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`I.
`
`Introduction
`Petitioners submit this Opposition to Memory Integrity’s (“MI”) Motion to
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`Attorney Docket No. 39521-0007IP1
`IPR2015-00159
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`Amend (“MTA”) (Paper 26). The MTA should be denied for three primary rea-
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`sons. First, MI failed to meet its burden of proof under 37 C.F.R. § 42.20(c) by
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`failing to identify how the features in the proposed substitute claims are distin-
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`guished from even the prior art of record. Second, the substitute claims are not en-
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`abled. Third, the prior art combination discussed below render the substitute
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`claims obvious.
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`II. MI’s Motion to Amend Fails to Comply with 37 C.F.R. § 42.20(c)
`MI “has the burden of proof to establish that it is entitled to the requested re-
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`lief.” See 37 C.F.R. § 42.20(c). Section 42.20(c) “places the burden on the patent
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`owner to show a patentable distinction of each proposed substitute claim over the
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`prior art.” Idle Free Sys., Inc. v. Bergstrom, Inc., Case IPR2012-00027, slip op. at
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`7 (PTAB June 11, 2013) (Paper 26); Microsoft Corp. v. Proxyconn, Inc., No. 2014-
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`1542, 2015 WL 3747257, at *13-14 (Fed. Cir. June 16, 2015) (affirming denial
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`where patent owner failed to establish the patentability over the prior art of record).
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`Here, MI failed to meet the burden imposed by § 42.20(c) for at least two
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`reasons. First, MI argues that, “all of the substitute claims find support in the ‘347
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`Application, [thus] the Koster reference is not prior art to any of the proposed sub-
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`stitute claims.” MTA, p. 22. MI provides no discussion comparing Koster’s teach-
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`ings to the “proposed new limitations.” However, claims 19-24 are not entitled to
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`Patent No. 7,296,121
`Petitioner’s Opposition to Patent Owner’s Motion to Amend
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`the ’347 Application’s priority date. Because MI did not establish patentability of
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`the substitute claims over Koster, MI has not met its burden under Section
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`42.20(c).
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`More specifically, in identifying support for the limitations of original
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`claims 19-24, MI relies entirely upon disclosure in “the ’893 App.” MTA, pp. 6-8.
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`However, Section 1.57(c) requires “essential material” to be incorporated by refer-
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`ence “to a U.S. patent … which … does not itself incorporate such essential mate-
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`rial by reference.” 37 C.F.R. § 1.57(c); see also 37 C.F.R. § 42.121(b)(1)(must
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`identify support in the original disclosure of the patent). However, here, the ’893
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`App is incorporated by reference into U.S. Application No. 10/157,388, which is
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`incorporated by reference into the ’347 App, which is incorporated by reference
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`into the ’161 App (the ’121 Patent’s application). See MTA, p. 6.
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`In other words, the relied upon essential material that is said to support
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`claims 19-24 is only present in an application that requires multiple incorporation
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`by references before finding its way into the ’161 App. For example, claim 19 re-
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`cites “[a]t least one computer-readable medium having data structures stored
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`therein representative of the probe filtering unit of claim 16.” Neither, the ’347
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`App nor the ’388 App contain any description of this feature, or any of the other
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`features recited in claims 20-24. Therefore, claims 19-24 (and the corresponding
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`substitute claims) are only entitled to a priority date no earlier than the filing date
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`Patent No. 7,296,121
`Petitioner’s Opposition to Patent Owner’s Motion to Amend
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`of the ’161 App (Oct. 15, 2004). As such, Koster is eligible as prior art for substi-
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`Attorney Docket No. 39521-0007IP1
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`tute claims 26-34, and MI was required by 37 C.F.R. § 42.20(c) to explain why the
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`claims are patentable over the Koster reference, which it did not. Accordingly, for
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`at least substitute claims 26-34, the MTA is deficient.
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`Second, the MTA fails to satisfy the Section 42.20(c) burden because it fails
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`to even mention, much less explain, why the claims are patentable over the de-
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`scription of the SGI Origin system, set forth in the Culler reference (Ex. 1028) on
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`pp. 596 to 622. Further, MI did not identify that the Pong and Koster references
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`(Exs. 1003 and 1009 as included in IPR2015-00158, -00159, and -00163) disclosed
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`the newly proposed coherent and non-coherent interface limitation in the substitute
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`claims. See Ex. 1026 at 89:6-15 (MI’s expert admitting that a probe filtering unit
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`with a path to main memory is a non-coherent interface); compare Pong Ex. 1003
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`at FIG. 1 and Koster Ex. 1009 at FIG. 4 (both illustrating a path from controller to
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`main memory). Further, with respect to the other new limitation in the substitute
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`claims, MESI states were well known in the art. See Ex. 1026, 68:4-19. See Corn-
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`ing Optical Comm. RF, LLC v. PPC Broadband, Inc., Case IPR2014-00441, Paper
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`19 at 4 (PTAB Oct. 30, 2014) (patent owner must identify whether the new limita-
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`tions were known anywhere).
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`These failures are emblematic of the fact that MI’s expert only spent about
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`5-10 hours reviewing the hundreds of prior art references of record (Ex. 1026,
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`21:1-23; 23:19 to 24:3), a review time per reference that does not meet the 37
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`C.F.R. § 42.20(c) burden in this case. Further, MI’s expert’s “patentabil[ity]”
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`opinion (Ex. 2019, ¶ 8) is completely unsupported as he failed to identify the legal
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`standard he used in forming this opinion.
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`MI was aware and familiar with the teachings of these references; Pong and
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`Koster are discussed in the IPR2015-00158, -00159 and -00163 Petitions and both
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`MI and its expert cited to the Culler book. POR, pp. 10, 27; Ex. 2016, ¶¶ 28, 90,
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`93. As will be established in Section IV infra, the Culler Book in combination
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`with Laudon not only teaches the features of the original claims 16-24, it also
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`teaches the “proposed new features” added to each of substitute claims 26-34. In-
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`deed, these references clearly contradict MI’s argument that, “[a]mong . . . the
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`prior art known to MI, coherent protocol interfaces and non-coherent protocol in-
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`terfaces are generally not taught in the art.” MTA, p. 22; see, e.g., Ex. 1028, pp.
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`604, 607 (note 3), 610, 614 (discussing additional support for “noncoherent opera-
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`tions such as uncached memory operations, I/O operations, and special synchroni-
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`zation support”). In the pages that follow, the Culler book is applied to the
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`amended claims, but without even resolving whether arguments can be made in at-
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`tempting to distinguish the Culler book, we note that the failure of MI to even at-
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`tempt to distinguish it demonstrates that MI’s MTA does not meet the require-
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`ments of 37 C.F.R. § 42.20(c) and should be denied.
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`4
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`Patent No. 7,296,121
`Petitioner’s Opposition to Patent Owner’s Motion to Amend
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`III. Substitute Claims 26-34 Are Not Enabled and Lack Written Description
`MI drafted “[e]ach of proposed substitute claims 26-34 . . . by first convert-
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`ing the respective original claim 19-24 to independent form, and then adding the
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`same proposed new limitations….” MTA, p. 2. One of these “proposed new limi-
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`tations” is “wherein said probe filtering unit is coupled to a coherent protocol inter-
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`face and a non-coherent protocol interface.” Id. In support of this limitation, MI
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`cites only to FIG. 3, two lines from column 11, and seven lines from column 13.
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`MTA, pp. 9-10. However, this disclosure simply illustrates the broad proposition
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`that the cache coherence controller “can also include other interfaces such as a
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`non-coherent protocol interface 311 for communicating with I/O devices.” Ex.
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`1001, 8:8-11. As such, MI’s support simply identifies where the non-coherent pro-
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`tocol interface is located, but provides no details for how it is implemented.
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`MI’s expert could not fix these §112 problems during his deposition. Dr.
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`Oklobdzija agreed that “one of ordinary skill would not have already had in their
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`knowledge how to build a system with a cache coherent interface and a non-cache
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`coherent interface.” Ex. 1026, 90:5-17. He then identified various ’121 figures,
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`that illustrated simple boxes labeled with the terms “coherent interface” and “non-
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`coherent interface” as providing enabling disclosure. Id. at 91:13-92:15. How-
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`ever, he finally admitted that “the details [of how to have a system with both a co-
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`herent interface and non-coherent interface] are not provided in the [’121] patent
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`5
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`… it is left to someone, you know, with the ordinary skill in the art to – to figure
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`out.” Id. at 95:14-96:10. Given these admissions, a POSITA would not be able to
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`make and use a system with the new limitation of “wherein said probe filtering unit
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`is coupled to a coherent protocol interface and a non-coherent protocol interface,”
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`nor to conclude that the inventor had possession of the claimed invention, as the
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`implementation details are not provided in the ’121 patent and are also not within
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`the knowledge of a POSITA.
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`IV. Substitute Claims 26-34 Are Not Patentable Over the Prior Art
`According to MI, proposed substitute claims 26-34 recite the same features
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`as respective original claims 16-24, but have been re-written in independent form,
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`to include the same “proposed new limitations.” MTA, p. 2. MI treats these “pro-
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`posed new limitations” in two parts:
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`1. wherein said states comprise cache coherency states of a cache co-
`herence protocol, and wherein said cache coherence protocol in-
`cludes at least a modified state, an exclusive state, a shared state,
`and an invalid state, and
`2. wherein said probe filtering unit is coupled to a coherent protocol
`interface and a non-coherent protocol interface
`See, e.g., MTA, pp. 8-9.
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`As to the first feature, MI’s expert admitted that cache coherence protocols
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`that implement modified, exclusive, shared, and invalid states (i.e., the MESI
`
`states) were well known in the art at the time of the ’121 Patent. See Ex. 1026,
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`6
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`68:4-19. Indeed, at least the disclosure of the Origin system in the Culler and Lau-
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`don references, is an example of a system that implemented a protocol that used
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`the MESI states. See Ex. 1028, p. 598. As to the second feature, there were a
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`number of references that disclosed a probe filtering unit with both a coherent and
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`non-coherent protocol interface, including the Culler and Laudon.
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`A. The Combination of the Culler Book and Laudon Renders Claims
`26-28 Obvious
`The Culler Book includes a case study of the SGI Origin architecture. See
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`Ex. 1028, p. 596. Similarly, Laudon is titled “The SGI Origin: A ccNUMA Highly
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`Scalable Server” and describes the same SGI Origin architecture as described in
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`the Culler Book’s case study. Ex. 1030, p. 1. Both the Culler Book and Laudon
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`share similar system diagrams, particularly with regard to the Hub chip, which acts
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`as the probe filtering unit in the SGI Origin architecture and is shown nearly identi-
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`cally in FIG. 8.21 of the Culler Book and FIG. 6 of Laudon. See Ex. 1028, p. 616;
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`Ex. 1030, p. 245. Accordingly, it would have been obvious to a POSITA to com-
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`bine the teachings of the Culler Book and Laudon, as the combination of these ref-
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`erences would have provided a more complete and confirmatory teaching of the
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`SGI Origin architecture. Ex. 1031, ¶ 2.
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`The Culler Book describes that “[t]he Origin system is composed of a num-
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`ber of processing nodes connected by switch-based interconnection network.” Ex.
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`1028, p. 597. “The interconnection network has a hypercube topology,” which is
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`Patent No. 7,296,121
`Petitioner’s Opposition to Patent Owner’s Motion to Amend
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`one form of the “scalable point-to-point interconnection network[s]” on which the
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`directory-based coherence protocols of Chapter 8 of the Culler Book are based.
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`Id., pp. 553, 596-597, 613; see Ex. 1031, ¶ 3 see also Ex. 1026, 132:24-134:1 (ad-
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`mitting that a switch-based network is a “point-to-point architecture”). According
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`to one implementation within the Culler Book, “[e]very processing node contains
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`two MIPS R10000 processors, each with first- and second-level caches, a fraction
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`of the total main memory of the machine, an I/O interface, and a single-chip com-
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`munication assist or cache coherence controller, called the Hub, that implements
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`the coherence protocol.” Ex. 1028, p. 597. Another of the Culler Book implemen-
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`tations suggests a single processor for each node. Id., p. 597 (“for simplicity that
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`each node contains only one processor”). Similarly, Laudon describes that “[e]ach
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`node consists of one or two R10000 processors.” Ex. 1030, p. 241 (emphasis
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`added. Accordingly, it would have been obvious to a POSITA to implement an
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`SGI Origin machine in which each of multiple nodes has only a single processor,
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`and the following section applies such a configuration to claims 26-34.
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`The caches of an SGI Origin machine “use[] the same MESI states as used
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`in Chapter 5” of the Culler Book, which are “modified (M) or dirty, exclusive-
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`clean (E), shared (S), and invalid (I).” Ex. 1028, pp. 598, 299. In the directory ref-
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`erenced by the Hub chip, these MESI states are represented by one of seven direc-
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`tory states. Id. at 598. For example, the “shared” directory state indicates “zero or
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`more read-only cached copies whose whereabouts are indicated by [a] presence
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`vector.” Id. In this “shared” directory state, the presence vector represents the pro-
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`cessors within which a memory line is stored in the shared (S) cache state and the
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`processors within which a memory line has the not-present state or the invalid (I)
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`state. Ex. 1031, ¶ 5. On the other hand, “[a]n exclusive directory state means the
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`block may be in either dirty or (clean) exclusive state in the cache (i.e., either the
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`M or E states of the MESI protocol.” Ex. 1028, p, 598. Thus, the information in
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`the directory referenced by the Hub chip are representative of each of the four
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`MESI states. Ex. 1031, ¶ 5.
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`Each of the SGI Origin processors support “accesses that are under the con-
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`trol of the coherence protocol.” Ex. 1028, p. 607, n. 3. In addition, each “proces-
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`sor also supports memory operations that are not visible to the coherence protocol,
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`called noncoherent memory operations, for which the system does not guarantee
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`any ordering.” Id. These noncoherent operations include “unchached memory op-
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`erations, I/O operations, and special synchronization support.” Id. at 604. For ex-
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`ample, a processor can use uncached references to a special I/O address space to
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`“reference any physical I/O device in the machine.” Id. at 614; Ex. 1031, ¶ 6.
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`Moreover, “[a]ll cache misses, whether to local or remote memory, go
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`through the Hub (which implements the coherence protocol), as do all uncached
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`operations.” Ex. 1028, pp. 612-613. In other words, both a processor and a Hub in
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`the SGI Origin architecture are capable of communicating coherent messages (e.g.,
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`cache misses) and noncoherent messages (e.g., uncached I/O operations) to other
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`components in the machine (e.g., each other), meaning that each contains a “coher-
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`ent protocol interface” and a “non-coherent protocol interface,” by MI’s own con-
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`struction of these terms. See MTA, p. 16; see also Ex. 1031, ¶¶ 6-7. Accordingly,
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`each Hub in the SGI Origin architecture is “coupled to a coherent protocol inter-
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`face and a non-coherent protocol interface,” as recited in the proposed substitute
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`claims, either because the Hub itself includes a coherent protocol interface and a
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`non-coherent protocol interface or because the Hub is coupled to a processor that
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`includes a coherent protocol interface and a non-coherent protocol interface.
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`The following is an explanation of how a combination of the Culler Book
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`and Laudon render substitute claim 26 obvious. This explanation focuses on the
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`SGI Origin architecture’s handling of read requests where the requested memory
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`lines are in the “owned” directory state and the local, home, and owner nodes are
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`all separate from each other. As will be explained, the Hub chip of the home node
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`is the claimed “probe filtering unit,” the processors are the claimed “processing
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`nodes,” and the read requests are “probes corresponding to memory lines.”
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`1.
`
`Claim 26
`The proposed combination of the Culler Book and Laudon discloses “[a]
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`Patent No. 7,296,121
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`probe filtering unit for use in a computer system comprising a plurality of pro-
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`cessing nodes interconnected by a first point-to-point architecture,” as recited in
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`claim 26. See Ex. 1031, ¶¶ 2-3. The Culler Book describes that “[t]he Origin sys-
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`tem is composed of a number of processing nodes connected by switch-based in-
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`terconnection network.” Ex. 1028, p. 597. “The interconnection network has a hy-
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`percube topology,” which is one form of the “scalable point-to-point interconnec-
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`tion network[s]” on which the directory-based coherence protocols of Chapter 8 of
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`the Culler Book are based. Id., pp. 553, 597, 613; see Ex. 1031, ¶ 3 see also Ex.
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`1026, 132:24-134:1 (admitting that a switch-based network is a “point-to-point ar-
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`chitecture”).
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`According to Laudon, “[e]ach node consists of one or two R10000 proces-
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`sors,” and the Culler Book even “assumes for simplicity that each node contains
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`only one processor” when discussing the cache coherence protocol. Ex. 1030, p.
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`241 (emphasis added); Ex. 1028, p. 597. Moreover, an SGI Origin system may
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`contain “up to 512 nodes.” Ex. 1028, p. 612. The proposed Culler and Lauden
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`combination is a system having four nodes, each containing a single processor.
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`However, the proposed combination would be equally applicable for systems con-
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`taining more than four nodes. The following is an adaptation of FIG. 8.15 of the
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`Culler Book that illustrates the proposed combination and annotates the relevant
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`components. See Ex. 1031, ¶ 4.
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`Patent No. 7,296,121
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`The proposed combination of the Culler Book and Laudon discloses “each
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`processing node having a cache memory associated therewith,” as recited in claim
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`26. See Ex. 1031 ¶ 5. As described in the Culler Book, each of the processors in
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`the SGI Origin architecture is associated with “first- and second-level caches.” Ex.
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`1028, pp. 597, 612.
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`The proposed Culler Book and Laudon combination includes a “probe fil-
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`tering unit being operable to receive probes corresponding to memory lines from
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`the processing nodes and to transmit the probes only to selected ones of the pro-
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`cessing nodes with reference to probe filtering information representative of states
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`associated with selected ones of the cache memories,” as recited in claim 26. See
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`Ex. 1031, ¶¶ 8-19. As described below, the home node Hub chip performs the re-
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`cited functionality of a probe filtering unit with regard to at least read requests.
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`The following adaptation of Culler Book FIG. 8.15 illustrates the communication
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`Patent No. 7,296,121
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`of read requests A and B in the implementation of the SGI Origin system of the
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`proposed combination. See Ex. 1031, ¶ 8.
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`Probes Correspond to 
`Memory Lines
`(i.e., Read Requests)
`
`Selected Ones of the 
`Processing Nodes
`(i.e., Owners)
`
`Probe Filtering Unit
`(i.e., Home Hub)
`
`Request A
`Request B
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`
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`Specifically, the home node Hub chip receives read requests for data blocks
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`from a local processing node. The received read requests are “probes correspond-
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`ing to memory lines from the processing nodes,” as recited in claim 26. The Hub
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`chip looks up a directory entry corresponding to the address of the data block of
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`the read request and forwards the read request depending on the state of the data
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`block. The directory look up and forwarding of the read request are “transmit[ing]
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`the probes only to selected ones of the processing nodes with reference to probe
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`filtering information representative of states associated with selected ones of the
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`cache memories,” as recited in claim 26.
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`“The Hub chip is the heart of the machine.” Ex. 1028, p. 612. The Hub chip
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`“implements the coherence protocol.” Id. The Hub chip “must . . . coordinate the
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`activities and dependences of all the different types of transactions that flow
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`through it from different components and implement the necessary pathways and
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`control.” Id., p. 614. “The Hub is divided into four major interfaces, one for each
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`type of external entity that it connects together: the processor interface or PI, the
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`memory/directory interface or MI, the network interface or NI, and the I/O inter-
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`face or II (see Figure 8.21).” Id., p. 615; Ex. 1031, ¶ 9.
`
`Each of the interfaces of the Hub chip “communicate with one another
`
`through an on-chip crossbar switch.” Ex. 1028, p. 615. “A key property of the de-
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`sign is for each interface to shield its external entity from the details of other inter-
`
`faces and entities (and vice versa).” Id. One example of this shielding is per-
`
`formed, during read requests, where the directory interface “treats a cache at the
`
`home just like any other cache; the only difference is that a ‘message’ between a
`
`home directory and a cache at home does not translate to a network transaction.”
`
`Id., p. 599. As a consequence, the processor and its associated cache in the home
`
`node will not receive a read request sent to the home node’s Hub chip, unless the
`
`memory directory interface of the Hub chip determines that the cache of the pro-
`
`cessor in the home node owns the requested cache line. Ex. 1031, ¶ 10.
`
`The following is an explanation of how a read request issued by a processor
`
`in a local/requesting node for a memory line associated with a separate home node
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`flows through the proposed SGI Origin system when the requested memory line is
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`14
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`Patent No. 7,296,121
`Petitioner’s Opposition to Patent Owner’s Motion to Amend
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`owned in the Modified (M) or Exclusive (E) state by a processor in a separate
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`Attorney Docket No. 39521-0007IP1
`IPR2015-00159
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`owner node. Id., ¶ 11. According to the Culler Book, when “a processor issues a
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`read that misses in its cache hierarchy . . . [, t]he address of the miss is examined
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`by the local Hub to determine the home node, and a read request transaction is sent
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`to the home node to look up the directory entry.” Ex. 1028, p. 599. This is illus-
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`trated in the following annotation of Culler Book FIG. 8.21, where “A” is the read
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`request. Ex. 1031, ¶ 11. This message flow corresponds to the yellow and purple
`
`arrows from the local/requesting process to the Hub chip of the home node in the
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`above adaptation of FIG. 8.15 of the Culler Book. Ex. 1031, ¶ 11.
`
`
`
`According to the Culler Book, “[a]t the home, the data for the block is ac-
`
`cessed speculatively in parallel with looking up the directory entry.” Ex. 1028, p.
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`599. The memory/directory interface of the Hub chip of the home node contains a
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`15
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`Patent No. 7,296,121
`Petitioner’s Opposition to Patent Owner’s Motion to Amend
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`directory interface, which “contains the logic and tables that determine what proto-
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`Attorney Docket No. 39521-0007IP1
`IPR2015-00159
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`col actions to take and hence implement the coherence protocol.” Id., p. 617. The
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`directory stores directory information, including states, for each memory block
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`stored in the memory of the node. See Id., pp. 598, 609; Ex. 1031, ¶¶ 12-13.
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`“At the directory, a block may be in one of seven states” including “un-
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`owned, or no cached copies in the system; shared, that is, zero or more read-only
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`cached copies whose whereabouts are indicated by the presence vector; and exclu-
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`sive, or one read-write cached copy in the system . . . .” Ex. 1028, p. 598 (empha-
`
`sis in original). “An exclusive directory state means the block may be in either
`
`dirty or (clean) exclusive state in the cache (i.e., either the M or E states of the
`
`MESI protocol).” Id. When a request memory block is in the exclusive directory
`
`state (i.e., either the M or E states of the MESI protocol) and the home is not the
`
`owner of the block, “the valid data for the block must be obtained from the owner
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`and must find its way to the requestor as well as to the home (since the state will
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`change to shared).” Ex. 1028, p. 599; Ex. 1031, ¶ 14.
`
`“The Origin protocol uses reply forwarding; the request is forwarded to the
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`owner, which replies directly to the requestor, sending a revision message to the
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`home” node. Ex. 1028, p. 599. In other words, the same request that was received
`
`by the home node Hub chip is forwarded to the owner processor. Ex. 1031, ¶ 15.
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`Importantly, in the example described here where the requested memory line is
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`16
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`Patent No. 7,296,121
`Petitioner’s Opposition to Patent Owner’s Motion to Amend
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`owned by a processor in a different node, neither the processor in the home node
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`Attorney Docket No. 39521-0007IP1
`IPR2015-00159
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`nor its associated cache receive the read request, because the Hub chip interface
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`shields its external entity from the details of other interfaces and entities. Id.
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`Moreover, according to the Culler Book, “[i]f a block is in an exclusive state
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`(i.e., modified or exclusive) in a processor cache, then the rest of the directory en-
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`try is not a bit vector with one bit turned on; rather, it contains an explicit pointer
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`to the specific processor (not node). This means that interventions forwarded from
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`the home are targeted to a specific processor.” Ex. 1028., p. 609. The memory/di-
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`rectory interface of the home Hub chip uses this pointer to address the read request
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`to the owner node, and the network interface of the home Hub chip uses the ad-
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`dress to forward the read request only to the specifically addressed processor. See
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`Id., pp. 617-18; see also Ex. 1031, ¶ 16.
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`The handling of a read request by the home node Hub chip is illustrated in
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`the following annotation of FIG. 8.21 of the Culler book, where “A-in” is the read
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`request received by the home hub over the interconnection network from the local
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`processor of the local node, “A-out” illustrates that “the request is forwarded to the
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`owner” across the interconnection network by the home hub, and “Spec” is the re-
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`sult of the speculative memory read that is returned by the home hub across the in-
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`terconnection network to the Hub chip of the local node. Ex. 1031, ¶ 17. In the
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`annotated Culler FIG. 8.15 above, this message flow corresponds to the yellow and
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`17
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`Patent No. 7,296,121
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`purple arrows from the home node Hub chip to the processor indicated in the direc-
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`Attorney Docket No. 39521-0007IP1
`IPR2015-00159
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`tory information to be the owner of the memory line. Id.
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`A‐in
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`A‐out
`
`Spec
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`
`
`Remote Home Hub
`
`Does not 
`receive request
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`
`
`According to the Culler book, when the owner processor receives the re-
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`quest, the Hub chip associated with the owner ensures that a reply is sent to the lo-
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`cal requesting processor and a revision message is sent to the home node Hub chip
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`so that it can update the directory state information. See Ex. 1028, pp. 599-600,
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`617-18; see also Ex. 1031, ¶ 18. Because a read request in the Origin system elic-
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`its a response from the owner processor to maintain cache coherency (e.g., the re-
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`ply by the owner processor causes a revision message to be sent to the home), the
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`read request is a probe.
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`As described above, the memory/directory interface of the home node’s Hub
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`18
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`Patent No. 7,296,121
`Petitioner’s Opposition to Patent Owner’s Motion to Amend
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`chip determines the owner processor with reference to the directory information
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`Attorney Docket No. 39521-0007IP1
`IPR2015-00159
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`stored in the directory and forwards the read request only to that owner processor.
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`Ex. 1031, ¶ 19. Accordingly, the Hub chip of the home node (probe filtering unit)
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`is operable to receive read requests (i.e., probes corresponding to memory lines)
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`from any of the processors of the system (i.e., the processing nodes) and to trans-
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`mit the read requests only to selected ones of the processors that own the requested
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`data (i.e., only to selected ones of the processing nodes) with reference to directory
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`information (i.e., probe filtering information) representative of states associated
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`with selected ones of the cache memories. Id.
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`The proposed combination of the Culler Book and Laudon discloses that
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`“said states comprise cache coherency states of a cache coherence protocol, and
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`wherein said cache coherence protocol includes at least a modified state, an exclu-
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`sive state, a shared state, and an invalid state,” as recited in claim 26. See Ex.
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`1031, ¶ 5. The caches of an SGI Origin machine “use[] the same MESI states a

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