Patent No. 7,296,121
`IPR2015-00159
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`APPLE INC., HTC CORPORATION, HTC AMERICA, INC., SAMSUNG
`ELECTRONICS CO. LTD, SAMSUNG ELECTRONICS AMERICA, INC.,
`SAMSUNG TELECOMMUNICATIONS AMERICA, LLC AND
`AMAZON.COM, INC.
`Petitioners
`
`v.
`
`MEMORY INTEGRITY, LLC
`Patent Owner
`
`U.S. Patent No. 7,296,121
`
`
`
`Inter Partes Review Case No. 2015-00159
`
`
`
`MEMORY INTEGRITY, LLC’S APPENDIX OF CLAIMS
`IN SUPPORT OF ITS MOTION TO AMEND [37 CFR § 42.121(b)]
`
`
`
`
`
`
`IPR2015-00159
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`APPLE INC., HTC CORPORATION, HTC AMERICA, INC., SAMSUNG
`ELECTRONICS CO. LTD, SAMSUNG ELECTRONICS AMERICA, INC.,
`SAMSUNG TELECOMMUNICATIONS AMERICA, LLC AND
`AMAZON.COM, INC.
`Petitioners
`
`v.
`
`MEMORY INTEGRITY, LLC
`Patent Owner
`
`U.S. Patent No. 7,296,121
`
`
`
`Inter Partes Review Case No. 2015-00159
`
`
`
`MEMORY INTEGRITY, LLC’S APPENDIX OF CLAIMS
`IN SUPPORT OF ITS MOTION TO AMEND [37 CFR § 42.121(b)]
`
`
`
`
`
`
`
`LISTING OF PROPOSED SUBSTITUTE CLAIMS
`
`Patent No. 7,296,121
`IPR2015-00159
`
`
`26 (contingent proposed substitute claim for claim 16 if Board determines claim 16
`is unpatentable):
`
`A probe filtering unit for use in a computer system comprising a plurality of
`processing nodes interconnected by a first point-to-point architecture, each
`processing node having a cache memory associated therewith, the probe filtering
`unit being operable to receive probes corresponding to memory lines from the
`processing nodes and to transmit the probes only to selected ones of the processing
`nodes with reference to probe filtering information representative of states
`associated with selected ones of the cache memories, wherein said states comprise
`cache coherency states of a cache coherence protocol, and wherein said cache
`coherence protocol includes at least a modified state, an exclusive state, a shared
`state, and an invalid state, and wherein said probe filtering unit is coupled to a
`coherent protocol interface and a non-coherent protocol interface.
`
`27 (contingent proposed substitute claim for claim 17 if Board determines claim 17
`is unpatentable):
`
`An integrated circuit comprising a probe filtering unit for use in a computer system
`comprising a plurality of processing nodes interconnected by a first point-to-point
`architecture, each processing node having a cache memory associated therewith,
`the probe filtering unit being operable to receive probes corresponding to memory
`lines from the processing nodes and to transmit the probes only to selected ones of
`the processing nodes with reference to probe filtering information representative of
`states associated with selected ones of the cache memories, wherein said states
`comprise cache coherency states of a cache coherence protocol, and wherein said
`cache coherence protocol includes at least a modified state, an exclusive state, a
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`Patent No. 7,296,121
`IPR2015-00159
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`shared state, and an invalid state, and wherein said probe filtering unit is coupled to
`a coherent protocol interface and a non-coherent protocol interface.
`
`28 (contingent proposed substitute claim for claim 18 if Board determines claim 18
`is unpatentable):
`
`An integrated circuit comprising a probe filtering unit for use in a computer system
`comprising a plurality of processing nodes interconnected by a first point-to-point
`architecture, each processing node having a cache memory associated therewith,
`the probe filtering unit being operable to receive probes corresponding to memory
`lines from the processing nodes and to transmit the probes only to selected ones of
`the processing nodes with reference to probe filtering information representative of
`states associated with selected ones of the cache memories, wherein said integrated
`circuit comprises an application-specific integrated circuit, wherein said states
`comprise cache coherency states of a cache coherence protocol, and wherein said
`cache coherence protocol includes at least a modified state, an exclusive state, a
`shared state, and an invalid state, and wherein said probe filtering unit is coupled to
`a coherent protocol interface and a non-coherent protocol interface.
`
`29 (contingent proposed substitute claim for claim 19 if Board determines claim 19
`is unpatentable):
`
`At least one computer-readable medium having data structures stored therein
`representative of a probe filtering unit for use in a computer system comprising a
`plurality of processing nodes interconnected by a first point-to-point architecture,
`each processing node having a cache memory associated therewith, the probe
`filtering unit being operable to receive probes corresponding to memory lines from
`the processing nodes and to transmit the probes only to selected ones of the
`processing nodes with reference to probe filtering information representative of
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`Patent No. 7,296,121
`IPR2015-00159
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`states associated with selected ones of the cache memories, wherein said states
`comprise cache coherency states of a cache coherence protocol, and wherein said
`cache coherence protocol includes at least a modified state, an exclusive state, a
`shared state, and an invalid state, and wherein said probe filtering unit is coupled to
`a coherent protocol interface and a non-coherent protocol interface.
`
`30 (contingent proposed substitute claim for claim 20 if Board determines claim 20
`is unpatentable):
`
`At least one computer-readable medium having data structures stored therein
`representative of a probe filtering unit for use in a computer system comprising a
`plurality of processing nodes interconnected by a first point-to-point architecture,
`each processing node having a cache memory associated therewith, the probe
`filtering unit being operable to receive probes corresponding to memory lines from
`the processing nodes and to transmit the probes only to selected ones of the
`processing nodes with reference to probe filtering information representative of
`states associated with selected ones of the cache memories, wherein said data
`structures comprise a simulatable representation of the probe filtering unit, wherein
`said states comprise cache coherency states of a cache coherence protocol, and
`wherein said cache coherence protocol includes at least a modified state, an
`exclusive state, a shared state, and an invalid state, and wherein said probe filtering
`unit is coupled to a coherent protocol interface and a non-coherent protocol
`interface.
`
`31 (contingent proposed substitute claim for claim 21 if Board determines claim 21
`is unpatentable):
`
`At least one computer-readable medium having data structures stored therein
`representative of a probe filtering unit for use in a computer system comprising a
`3
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`Patent No. 7,296,121
`IPR2015-00159
`
`
`plurality of processing nodes interconnected by a first point-to-point architecture,
`each processing node having a cache memory associated therewith, the probe
`filtering unit being operable to receive probes corresponding to memory lines from
`the processing nodes and to transmit the probes only to selected ones of the
`processing nodes with reference to probe filtering information representative of
`states associated with selected ones of the cache memories, wherein the data
`structures comprise a simulatable representation of the probe filtering unit, wherein
`said simulatable representation comprises a netlist, wherein said states comprise
`cache coherency states of a cache coherence protocol, and wherein said cache
`coherence protocol includes at least a modified state, an exclusive state, a shared
`state, and an invalid state, and wherein said probe filtering unit is coupled to a
`coherent protocol interface and a non-coherent protocol interface.
`
`32 (contingent proposed substitute claim for claim 22 if Board determines claim 22
`is unpatentable):
`
`At least one computer-readable medium having data structures stored therein
`representative of a probe filtering unit for use in a computer system comprising a
`plurality of processing nodes interconnected by a first point-to-point architecture,
`each processing node having a cache memory associated therewith, the probe
`filtering unit being operable to receive probes corresponding to memory lines from
`the processing nodes and to transmit the probes only to selected ones of the
`processing nodes with reference to probe filtering information representative of
`states associated with selected ones of the cache memories, wherein the data
`structures comprise a code description of the probe filtering unit, wherein said
`states comprise cache coherency states of a cache coherence protocol, and wherein
`said cache coherence protocol includes at least a modified state, an exclusive state,
`
`
`
`4
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`
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`a shared state, and an invalid state, and wherein said probe filtering unit is coupled
`to a coherent protocol interface and a non-coherent protocol interface.
`
`Patent No. 7,296,121
`IPR2015-00159
`
`
`33 (contingent proposed substitute claim for claim 23 if Board determines claim 23
`is unpatentable):
`
`At least one computer-readable medium having data structures stored therein
`representative of a probe filtering unit for use in a computer system comprising a
`plurality of processing nodes interconnected by a first point-to-point architecture,
`each processing node having a cache memory associated therewith, the probe
`filtering unit being operable to receive probes corresponding to memory lines from
`the processing nodes and to transmit the probes only to selected ones of the
`processing nodes with reference to probe filtering information representative of
`states associated with selected ones of the cache memories, wherein said data
`structures comprise a code description of the probe filtering unit, wherein said code
`description corresponds to a hardware description language, wherein said states
`comprise cache coherency states of a cache coherence protocol, and wherein said
`cache coherence protocol includes at least a modified state, an exclusive state, a
`shared state, and an invalid state, and wherein said probe filtering unit is coupled to
`a coherent protocol interface and a non-coherent protocol interface.
`
`34 (contingent proposed substitute claim for claim 24 if Board determines claim 24
`is unpatentable):
`
`A set of semiconductor processing masks representative of at least a portion of a
`probe filtering unit for use in a computer system comprising a plurality of
`processing nodes interconnected by a first point-to-point architecture, each
`processing node having a cache memory associated therewith, the probe filtering
`unit being operable to receive probes corresponding to memory lines from the
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`Patent No. 7,296,121
`IPR2015-00159
`
`processing nodes and to transmit the probes only to selected ones of the processing
`nodes with reference to probe filtering information representative of states
`associated with selected ones of the cache memories, wherein said states comprise
`cache coherency states of a cache coherence protocol, and wherein said cache
`coherence protocol includes at least a modified state, an exclusive state, a shared
`state, and an invalid state, and wherein said probe filtering unit is coupled to a
`coherent protocol interface and a non-coherent protocol interface.
`
`
`
`Date: August 11, 2015
`
`Respectfully submitted,
`
`
`
` /Michael D. Saunders/
`Michael D. Saunders
`Admitted Pro Hac Vice
`Farney Daniels PC
`411 Borel Avenue, Suite 350
`San Mateo, California 94402
`Phone: 424-268-5210
`
`E-mail: msaunders@farneydaniels.com
`
`6
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`CERTIFICATE OF SERVICE
`
`Patent No. 7,296,121
`IPR2015-00159
`
`
`Under 37 C.F.R. §§ 42.6(e), this is to certify that I served a copy of the
`
`foregoing MEMORY INTEGRITY, LLC’S APPENDIX OF CLAIMS IN
`
`SUPPORT OF ITS MOTION TO AMEND [37 CFR § 42.121(b)] via email on
`
`August 11, 2015 to Petitioners’ counsel of record at the following email addresses:
`
`W. Karl Renner, Reg. No. 41, 265
`Roberto Devoto, Reg. No. 55, 108
`Fish & Richardson P.C.
`3200 RBC Plaza
`60 South Sixth Street
`Minneapolis, MN 55402
`Email:
`IPR39521-0007IP1@fr.com
`IPR39521-0007IP2@fr.com
`IPR39521-0007IP3@fr.com
`IPR39521-0007IP4@fr.com
`renner@fr.com
`devoto@fr.com
`
`Dated: August 11, 2015
`
`/Michael D. Saunders/
`Michael D. Saunders
`Admitted Pro Hac Vice
`
`
`
`
`
`
`7
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