Trials@uspto.gov
`571.272.7822
`
`
`Paper No. 12
`
` Filed: May 11, 2015
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`APPLE INC., HTC CORPORATION, HTC AMERICA, INC.,
`SAMSUNG ELECTRONICS CO. LTD,
`SAMSUNG ELECTRONICS AMERICA, INC., and
`AMAZON.COM, INC.,
`Petitioner,
`
`v.
`
`MEMORY INTEGRITY, LLC,
`Patent Owner.
`____________
`
`Case IPR2015-00159
`Patent 7,296,121 B2
`____________
`
`
`
`Before JENNIFER S. BISK, NEIL T. POWELL, and KERRY BEGLEY,
`Administrative Patent Judges.
`
`BEGLEY, Administrative Patent Judge.
`
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`571.272.7822
`
`
`Paper No. 12
`
` Filed: May 11, 2015
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`APPLE INC., HTC CORPORATION, HTC AMERICA, INC.,
`SAMSUNG ELECTRONICS CO. LTD,
`SAMSUNG ELECTRONICS AMERICA, INC., and
`AMAZON.COM, INC.,
`Petitioner,
`
`v.
`
`MEMORY INTEGRITY, LLC,
`Patent Owner.
`____________
`
`Case IPR2015-00159
`Patent 7,296,121 B2
`____________
`
`
`
`Before JENNIFER S. BISK, NEIL T. POWELL, and KERRY BEGLEY,
`Administrative Patent Judges.
`
`BEGLEY, Administrative Patent Judge.
`
`
`
`DECISION
`Institution of Inter Partes Review
`37 C.F.R. § 42.108
`
`
`
`
`IPR2015-00159
`Patent 7,296,121 B2
`
`Apple Inc., HTC Corporation, HTC America, Inc., Samsung
`
`Electronics Co. Ltd., Samsung Electronics America, Inc.,1 and Amazon.com,
`Inc. (collectively, “Petitioner”) filed a Petition requesting inter partes review
`of claims 1–3, 8, and 11–25 of U.S. Patent No. 7,296,121 B2 (Ex. 1001, “the
`’121 patent”). Memory Integrity, LLC (“Patent Owner”) filed a Preliminary
`Response to the Petition. Paper 11 (“Prelim. Resp.”).
`Pursuant to 35 U.S.C. § 314(a), an inter partes review may not be
`instituted unless “the information presented in the petition . . . and any
`response . . . shows that there is a reasonable likelihood that the petitioner
`would prevail with respect to at least 1 of the claims challenged in the
`petition.” Having considered the Petition and the Preliminary Response, we
`conclude that there is a reasonable likelihood that Petitioner would prevail in
`establishing the unpatentability of claims 1–3, 8, 11, and 15–25 of the
`’121 patent but not claims 12–14. Therefore, we institute inter partes
`review only as to claims 1–3, 8, 11, and 15–25.
`I. BACKGROUND
`A. THE ’121 PATENT
`The ’121 patent relates to techniques to reduce memory transaction
`
`traffic and to improve data access and cache coherency in systems with
`multiple processors connected using point-to-point links. Ex. 1001, 1:22–
`25, 2:39–47. The ’121 patent explains that cache coherency problems can
`arise in a system with multiple processors, each with an individual cache
`memory, because the system may contain multiple copies of the same data.
`
`1 The Petition also lists Samsung Telecommunications America, LLC
`(“STA”) as a petitioner. Paper 6 (“Pet.”), 1. After the filing of the Petition,
`however, STA merged with and into Samsung Electronics America, Inc.
`Paper 10. Thus, STA no longer exists as a separate corporate entity. Id.
`
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`Id. at 1:26–38. For example, if the caches of two different processors have a
`copy of the same data block and both processors “attempt to write new
`values into the data block at the same time,” then the two caches may have
`different data values and the system may be “unable to determine what value
`to write through to system memory.” Id. at 1:37–45.
`
`The ’121 patent discloses a computer system with processing nodes,
`each with a cache memory, connected by a point-to-point architecture. Id. at
`[57], 2:48–62. The system also includes a “probe filtering unit” that can
`receive a probe, “[a] mechanism for eliciting a response from a node to
`maintain cache coherency in a system,” from a processing node. Id. at [57],
`2:52–65, 5:45–47. The probe filtering unit then can evaluate the probe
`based on probe filtering information, specifically “[a]ny criterion that can be
`used to reduce the number of clusters or nodes probed,” and can transmit the
`probe to selected processing nodes. Id. at [57], 2:52–3:5, 14:50–52; see id.
`at 28:29–58, 29:43–46. The probe filtering unit also may be operable to
`accumulate responses from the selected processing nodes and to respond to
`the node from which the probe originated. Id. at 3:5–8, 28:59–67, 29:46–51.
`Figure 18 of the patent is reproduced below.
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`Figure 18 is a diagrammatic representation of a multiple processor
`system with a probe filtering unit. Id. at 3:61–63, 26:58–27:20, Fig. 18.
`Specifically, Figure 18 depicts multiple processor system 1800 with
`processing nodes 1802a–d interconnected by point-to-point communication
`links 1808a–e. Id. at 26:58–27:1. System 1800 also includes probe filtering
`unit 1830 as well as I/O switch 1810, one or more Basic I/O systems
`(“BIOS”) 1804, I/O adapters 1816, 1820, and a memory subsystem with
`memory banks 1806a–d. Id. at 3:61–63, 26:58–27:20, Fig. 18.
`Claims 1, 16, and 25 of the ’121 patent are independent claims.
`Claim 1 is illustrative of the claimed subject matter and recites:
`1. A computer system comprising a plurality of processing
`nodes interconnected by a first point-to-point architecture,
`each processing node having a cache memory associated
`therewith,
`the computer system further comprising a probe filtering unit
`which is operable to receive probes corresponding to memory
`lines from the processing nodes and to transmit the probes only
`to selected ones of the processing nodes with reference to probe
`filtering information representative of states associated with
`selected ones of the cache memories.
`Id. at 30:65–31:7 (line breaks added).
`B. ASSERTED PRIOR ART
`The Petition relies upon the following prior art references, as well as
`the supporting Declaration of Robert Horst, Ph.D. (Ex. 1014):
`U.S. Patent Application Publication No. 2002/0053004 A1 (published
`May 2, 2002) (Ex. 1003, “Pong”);
`
`U.S. Patent No. 6,662,277 B2 (filed July 31, 2001) (issued Dec. 9,
`2003) (Ex. 1020, “Gaither”);
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`JOSÉ DUATO ET AL., INTERCONNECTION NETWORKS (1997) (Ex. 1007,
`“Duato”); and
`
`MICHAEL JOHN SEBASTIAN SMITH, APPLICATION-SPECIFIC INTEGRATED
`CIRCUITS (1997) (Ex. 1008, “Smith”).
`C. ASSERTED GROUNDS OF UNPATENTABILITY
`Petitioner asserts the following grounds of unpatentability. Pet. 3.
`Challenged Claim[s]
`Basis
`Reference[s]
`1–3, 8, 11, 12, 15, 16, and 25 § 102 Pong
`13
`§ 103 Pong and Gaither
`14
`§ 103 Pong and Duato
`17–24
`§ 103 Pong and Smith
`
`II. ANALYSIS
`A. CLAIM INTERPRETATION
`We begin our analysis by addressing the meaning of the claims. The
`Board interprets claims using the “broadest reasonable construction in light
`of the specification of the patent in which [they] appear[].” 37 C.F.R.
`§ 42.100(b); see In re Cuozzo Speed Techs., LLC, 778 F.3d 1271, 1279–82
`(Fed. Cir. 2015). We presume a claim term carries its “ordinary and
`customary meaning,” which is “the meaning that the term would have to a
`person of ordinary skill in the art in question” at the time of the invention.
`In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007) (citation
`and quotations omitted). This presumption, however, is rebutted when the
`patentee acts as his own lexicographer by giving the term a particular
`meaning in the specification with “reasonable clarity, deliberateness, and
`precision.” In re Paulsen, 30 F.3d 1475, 1480 (Fed. Cir. 1994).
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`Petitioner and Patent Owner each proffer proposed constructions of
`several claim terms. On this record and for purposes of this decision, we
`determine that only the claim terms addressed below require construction.
`1. “probe” (claims 1–3, 8, 11–17, 19, 20, 22, 24, and 25)
`Petitioner points out that the ’121 patent defines the term “probe,”
`
`which is recited in challenged claims 1–3, 8, 11–17, 19, 20, 22, 24, and 25,
`and argues that the term should be construed as “a mechanism that elicits a
`response from a node to maintain cache coherency in a system.” Pet. 7–8.
`Patent Owner does not address Petitioner’s assertions.
`We note that Petitioner’s proposed construction slightly differs from
`the definition of “probe” in the ’121 patent, which uses the language “a
`mechanism for eliciting a response,” as opposed to “a mechanism that elicits
`a response” in Petitioner’s proposed construction. Id. (emphases added); see
`Ex. 1001, 5:45–47. Petitioner has provided no reason for the difference in
`wording. Therefore, for purposes of this decision, we adopt as the broadest
`reasonable construction of “probe” the express definition of the term in the
`’121 patent: “[a] mechanism for eliciting a response from a node to
`maintain cache coherency in a system.” Ex. 1001, 5:45–47.
`2. “probe filtering information” (claims 1, 3, 16, and 25)
`Petitioner argues that the ’121 patent expressly defines “probe
`
`filtering information,” as recited in challenged claims 1, 3, 16, and 25.
`Pet. 8–9. Patent Owner does not respond to this argument. We agree that
`the ’121 patent defines the term “probe filter information.” Ex. 1001,
`14:50–52. On the record before us, we adopt this definition as the broadest
`reasonable construction of the claim term “probe filtering information”:
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`“[a]ny criterion that can be used to reduce the number of clusters or nodes
`probed.” Id.
`3. “states associated with selected ones of the cache memories (claims 1,
`16, and 25)
`Claims 1, 16, and 25 recite “probe filtering information”
`“representative of states associated with selected ones of the cache
`memories.” The parties agree that the ’121 patent does not explicitly define
`“states associated with selected ones of the cache memories.” Pet. 9; Prelim.
`Resp. 13. Each party proposes a construction of the term. Pet. 9–10; Prelim.
`Resp. 13–24. Petitioner’s proposal is that the term is “broad enough to
`encompass ‘any modes or conditions of selected ones of the cache
`memories.’” Pet. 10. Patent Owner proposes that the term means “cache
`coherence protocol states associated with data blocks stored in selected ones
`of the cache memories,” where a “cache coherence protocol state” means
`“the current state of a data block in a protocol used to maintain the
`coherency of caches, in which a data block can only be in one current state
`at a time, and in which the current state can transition to a different state
`upon one or more triggering events or conditions.” Prelim. Resp. 13–14. At
`this preliminary stage of this proceeding, for the reasons discussed below,
`we are not persuaded that either party’s proposal accurately represents the
`broadest reasonable construction of the term “states associated with selected
`ones of the cache memories.” For purposes of this decision, we do not adopt
`a construction of the term and instead address aspects of its scope.
`Petitioner explains that this term should be construed broadly because
`“the ’121 patent fails to limit the recited ‘states’ to a specific type of state
`nor even to a particular group of states, such as standard coherence protocol
`states.” Pet. 9 (citing Ex. 1001, 14:30–36). Petitioner points to a dictionary
`
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`definition of the word “state” as “‘mode or condition of being.’” Id. at 10
`(citing Ex. 1015, 1145). Petitioner argues “state” is exemplified by
`presence, which is defined in the same dictionary as “‘the fact or condition
`of being present.’” Id. (citing Ex. 1015, 919) (emphasis omitted).
`According to Petitioner, the ’121 patent uses the word “state” in a manner
`consistent with this meaning and encompasses the condition of being present
`by describing that a “directory of shared cache states . . . indicates where
`particular memory lines are cached within the cluster.” Id. (quoting
`Ex. 1001, 28:29–34).
`Patent Owner disagrees. Specifically, Patent Owner argues that
`“under Petitioner’s construction, the mode or condition need not have any
`relation to cache coherency or even what is stored in the selected ones of the
`cache memories.” Prelim. Resp. 13. To the extent Petitioner’s construction
`is broad enough to include “states” that are not in any way related to what is
`stored in cache memory, we agree with Patent Owner that this construction
`is unreasonable. The words in the limitation “states associated with selected
`ones of the cache memories,” especially when read in the context of the
`claims, plainly link the “states” to the “cache memories.” The claims use the
`term “representative of states associated with selected ones of the cache
`memory” to modify “probe filtering information.” Ex. 1001, 31:5–7, 32:14–
`15, 32:52–55 (emphasis added). Based on the function of the probe filtering
`information—reducing the number of clusters or nodes probed when
`requesting contents of cache memory (see id. at 14:50–52)—we are
`persuaded that this language effectively relates the recited “states” not just to
`any aspect of the cache memory, but to the contents of that memory.
`
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`On the other hand, we are not persuaded that the ’121 patent supports
`a construction as narrow as that proposed by Patent Owner. Patent Owner
`asserts that “states” refers solely to cache coherence protocol states. Prelim.
`Resp. 14–17. Patent Owner bases this assertion on two examples of
`potential states given in the ’121 patent: “the four states of modified, owned,
`shared, and invalid” and “the five states of modified, exclusive, owned,
`shared, and invalid.” Id. at 14–15 (quoting Ex. 1001, 14:30–36) (emphasis
`omitted). According to Patent Owner, these examples “reinforce[] that the
`relevant states are cache coherence protocol states (although not limited to
`any particular cache coherence protocol’s set of states).” Id. at 15. Patent
`Owner also points to Figures 7 and 8, which show similar states in diagram
`form. Id. The ’121 patent, however, sets these examples within broad
`language stating that “particular implementations may use a different set of
`states” and “[t]he techniques of the present invention can be used with a
`variety of different possible memory line states.” Ex. 1001, 14:30–36. We,
`thus, are not persuaded that these examples limit the broadest reasonable
`construction of the term “states” to cache coherence protocol states.
`In addition, because we are not persuaded that the term “states” is
`limited to cache coherence protocol states, we are not persuaded by
`Patent Owner’s further proposed limitations to the term “states associated
`with selected ones of the cache memories” based on aspects of cache
`coherence protocol states. See Prelim. Resp. 17–24.
`Moreover, given the usage of “states” in the specification of the
`’121 patent as well as the dictionary definition of “state” cited by Petitioner,
`we are persuaded, on this record, that “states associated with selected ones
`of the cache memories” is broad enough to include the condition of
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`presence. See Pet. 9–10; Ex. 1001, 14:30–36, 28:29–34 (“The PFU accepts
`the probe and looks up the address in its directory of shared cache states . . .
`[that] indicates where particular memory lines are cached within the
`cluster.”); Ex. 1015, 919, 1145. This conclusion is further supported by
`other extrinsic evidence, particularly the definition of “state” in MICROSOFT
`COMPUTER DICTIONARY: “[t]he condition at a particular time of any of
`numerous elements of computing—a device, a communications channel, a
`network station, a program, a bit, or other element—used to report on or to
`control computer operations.” Ex. 3001 (MICROSOFT COMPUTER
`DICTIONARY (5th ed. 2002)), 497–98.
`At this preliminary stage of this proceeding, we decline to adopt either
`party’s proposed construction of the term “states associated with selected
`ones of the cache memories.” Instead, for purposes of this decision, we are
`persuaded only that, on this record, the term is not limited to cache
`coherence protocol states and is broad enough to include the condition of
`presence—i.e., what is stored in cache memory.
`4. “after receiving a first number of responses to a first probe” (claim 11),
`“wherein . . . the first number is one” (claim 12), “wherein . . . the first
`number is two” (claim 13)
`Claim 11 depends from claim 1 and further recites “wherein each of
`
`the processing nodes is programmed to complete a memory transaction after
`receiving a first number of responses to a first probe, the first number being
`fewer than the number of processing nodes.” Ex. 1001, 31:49–53.
`Claims 12 and 13 depend from claim 11. Claim 12 adds the limitation:
`“wherein . . . the first number is one.” Id. at 31:57. Claim 13 adds the
`limitation: “wherein . . . the first number is two.” Id. at 31:61–62. Neither
`party discusses this claim language in the claim construction section of its
`
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`briefing. See Pet. 5–15; Prelim. Resp. 11–25. In arguing that Pong
`anticipates claim 12, however, Petitioner proposes an interpretation of “after
`receiving a first number of responses to a first probe” “wherein . . . the first
`number is one” that we must address to determine whether institution of
`inter partes review is warranted. See Pet. 34; Ex. 1014 ¶ A-23.
`Specifically, Petitioner argues that, under the broadest reasonable
`interpretation, “the requirement of claim 12 that ‘the first number is one’
`simply imparts a temporal requirement . . . that the memory transaction be
`completed after receiving one response.” Pet. 34. Therefore, according to
`Petitioner, “even in the case where a requesting processor waits for [a]
`second response to complete the memory transaction, that memory
`transaction is completed after receiving one response” and, thus, falls within
`the claim language. Id. As support, Petitioner cites the testimony of
`Dr. Horst, who similarly opines that “‘after’ can be reasonably read to mean
`any time after receiving one response” and, therefore, “claim 12 can be
`reasonably read to simply impart a temporal requirement that each
`processing node be programmed to wait until receiving at least one response
`to complete a memory transaction.” Ex. 1014 ¶ A-23 (emphases added). In
`other words, Petitioner proposes that even if a processing node performs a
`memory transaction after receiving two, three, four, etc. responses, it would
`still satisfy the claim language “after receiving a first number of responses to
`a first probe” “wherein . . . the first number is one.”
`
`We disagree. Upon review of the claims and the written description
`of the ’121 patent—neither of which is discussed in the Petition or
`Dr. Horst’s testimony—we determine that Petitioner’s proposed
`interpretation of the claim language is too broad to be reasonable. We
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`decline to interpret “after” as “any time after” and “one” as “at least one,” as
`Petitioner suggests. Id.
`Petitioner’s proposed interpretation would render the various specific
`limitations regarding the recited “first number”—“the first number being
`fewer than the number of processing nodes” (claim 11), “the first number is
`one” (claim 12), and “the first number is two” (claim 13)—effectively
`meaningless and nonsensical. See Becton, Dickinson & Co. v. Tyco
`Healthcare Grp., LP, 616 F.3d 1249, 1255 (Fed. Cir. 2010) (holding that a
`claim construction that renders claims nonsensical cannot be correct); Cat
`Tech LLC v. TubeMaster, Inc., 528 F.3d 871, 885 (Fed. Cir. 2008) (refusing
`to adopt a construction that would render a claim limitation meaningless).
`For example, under Petitioner’s proposed interpretation, claim 11’s
`language, “after receiving a first number of responses to a first probe, the
`first number being fewer than the number of processing nodes,” would
`extend to memory transactions performed “any time after receiving” a
`number of responses fewer than the processing nodes. Ex. 1014 ¶ A-23; see
`Pet. 34. In other words, the limitation would cover memory transactions
`performed after the processing node received any number of responses—
`whether fewer than, equal to, or greater than the number of processing
`nodes. It, therefore, would impose no meaningful limitation on the number
`of responses the requesting processor must be programmed to receive before
`performing a memory transaction.
`
`We also are not persuaded that Petitioner’s proposed construction is
`consistent with the discussion of programming the processing nodes in the
`’121 patent specification. The ’121 patent refers to programming each node
`“to expect only one or two probe responses instead of one from each node in
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`the system. More specifically, each node is programmed to expect one
`probe response if the [probe filtering unit] contains temporary storage to
`hold dirty data, and two if it does not.” Ex. 1001, 28:16–21; see id. at
`28:21–29:30. This discussion of programming processing nodes to expect a
`specific number of responses (one or two) is not in line with Petitioner’s
`proposal that claim 12’s limitation—the first number is one—would extend
`to performing a memory transaction any time after receiving one response,
`including after receiving two, three, four, or more responses, and that
`claim 13’s corresponding limitation—the first number is two—similarly
`would extend to performing a transaction after receiving three, four, five, or
`more responses.
`
`In light of the ’121 patent claims and written description, discussed
`above, we determine that “after receiving a first number of responses to a
`first probe” “wherein . . . the first number is one,” as recited in claim 12,
`means after receiving one response—not at least one or more than one
`response, as Petitioner proposes. Similarly, we conclude that the language
`in claim 13, “after receiving a first number of responses to a first probe”
`“wherein . . . the first number is two” means after receiving two responses—
`not at least two or more than two responses. In other words, if a processor
`performs a memory transaction after receiving two responses, the first
`number is two—not one, as Petitioner suggests. See Pet. 34.
`5. “cache coherence controller” (claim 3)
`Petitioner also correctly contends that the ’121 patent defines “cache
`
`coherence controller,” as recited in claim 3. Id. at 12–13. Patent Owner
`does not address this assertion. For purposes of this decision, we adopt this
`express definition as the broadest reasonable construction of “cache
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`coherence controller”: “[a]ny mechanism or apparatus that can be used to
`provide communication between multiple processor clusters while
`maintaining cache coherence.” Ex. 1001, 7:2–5.
`B. ANTICIPATION BY PONG
`We turn to the asserted grounds. Petitioner argues Pong anticipates
`
`claims 1–3, 8, 11, 12, 15, 16, and 25 of the ’121 patent. Pet. 20–44.
`1. Pong
`Pong discloses a multiprocessor system implementing an
`
`asynchronous cache coherence protocol. Ex. 1003, [57], ¶ 12. In the
`asynchronous cache coherence protocol, each data block has associated state
`information, which “indicates whether a copy of the data block is valid or
`invalid.” Id. ¶ 13. When a processor “propagates a read or write request”
`and the receiving processor does not have a valid copy of the requested data
`block, “it simply drops the request without responding.” Id. ¶ 24; see id.
`¶ 13. Therefore, “the processors do not have to synchronize a response to a
`request for a data block.” Id. ¶ 24.
`In addition, Pong explains that “write invalidation and write update”
`are the “two primary protocols for cache coherence.” Id. ¶ 48. “Either of
`these protocols may be used to implement” the disclosed system. Id. ¶ 69;
`see id. ¶ 48. These protocols respond differently to write operations.
`Specifically, in response to a write operation, “[t]he write invalidation
`protocol invalidates other copies of a data block,” whereas the write update
`protocol “updates all of the cached copies of a data block.” Id. ¶ 48.
`Pong discusses an implementation of the disclosed multiprocessor
`system using “point-to-point links to communicate memory requests.” Id.
`¶ 12; see id. ¶¶ 15, 29–30. Figure 2 of Pong is reproduced below.
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`Figure 2 depicts multiprocessor 200, with processors 202, 204 and memory
`controller 206. Id. ¶¶ 18, 30. Each processor includes “one or more
`caches” 212, 214. Id. ¶ 31. Each processor communicates with memory
`controller 206 through “two dedicated and unidirectional links.” Id. ¶ 30;
`see id. ¶ 15.
`Memory controller 206 has one request queue 220, 222 and one snoop
`queue 224, 226 per processor. Id. ¶¶ 31–33. The request queue receives
`requests from the processor; the snoop queue issues requests to the processor
`in first in, first out order. Id. ¶¶ 32–35. Memory controller 206 also
`includes internal address bus 223, through which these queues communicate.
`See id. ¶ 33, Fig. 3. “[W]hen a processor issues a request for a block of
`data,” the request enters a request queue (220 or 222) in memory
`controller 206. Id. ¶ 32; see id. ¶ 43. These request queues may be designed
`either to “broadcast the request to all other processors and the memory” or to
`“target the request to a specific processor or set of processors known to have
`a copy of the requested block.” Id. ¶ 32; see id. at [57], ¶ 13.
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`Pong describes a “possible implementation of the data path for the
`
`architecture” shown in Figure 2, in which the memory controller also
`includes an incoming queue and an outgoing queue for each processor. See
`id. ¶¶ 40–43, Fig. 3. Pong explains that when a processor “is responding to
`a request for a data block,” it transfers the data block to the memory
`controller, particularly the outgoing queue that corresponds to the processor.
`Id. ¶¶ 41, 43. From the outgoing queue, the data block enters the bus of the
`memory controller. Id. ¶ 41. From the bus, the data block is buffered in the
`incoming queue that corresponds to the processor to which the data block is
`destined. Id.
`Pong also discloses the use of a directory to “reduce traffic in the
`control path.” Id. ¶ 51. “A directory, in this context, is a mechanism for
`identifying which processors have a copy of a data block.” Id. The
`directory can be implemented with a “presence bit vector,” with one bit per
`processor. Id. “When the bit corresponding to a processor is set in the bit
`vector, the processor has a copy of the data block.” Id.
`The directory “may be stored in a memory device that is . . .
`integrated into the memory controller.” Id. ¶ 57. “In this implementation,
`the memory controller directs a request from the request queue to the
`directory, which filters the request and addresses it to the appropriate
`processors (and possibly memory devices).” Id. ¶ 56. Specifically,
`“directory filter 400 receives requests from the request queues (e.g., 402,
`404) in the memory controller, determines which processors have a copy of
`the data block of interest, and forwards the request to the [snoop queue](s)
`(e.g., 406, 408) corresponding to these processors.” Id. ¶ 57.
`
`
`
`16
`
`
`
`IPR2015-00159
`Patent 7,296,121 B2
`
`
`2. Independent Claims 1, 16, and 25
`We begin our analysis by addressing the independent claims of the
`
`’121 patent, claims 1, 16, and 25.
`a. Common Disputed Limitations
`Patent Owner’s dispute of Petitioner’s anticipation arguments
`
`regarding claims 1, 16, and 25 focuses on the limitations related to probe
`filtering. Prelim. Resp. 28–48. In addressing the limitations, Petitioner
`contends that Pong’s memory controller corresponds to the recited “probe
`filtering unit” and its presence bit vector corresponds to the recited “probe
`filtering information.” Pet. 25–27, 36–37, 38–44. Further, Petitioner argues
`that both the read requests and write requests in Pong correspond to the
`“probes” recited in claims 1 and 16 and the “probe” recited in claim 25. Id.
` i. “probe filtering unit” and “probes”
`Based on our review of the Petition, Petitioner has proffered sufficient
`evidence that Pong discloses a “probe filtering unit . . . operable to receive
`probes corresponding to memory lines from the processing nodes and to
`transmit the probes only to selected ones of the processing nodes”—as
`recited in claims 1 and 16. Ex. 1001, 31:1–5, 32:11–14; see Pet. 24–26, 36–
`37. We also are persuaded, on this record, that Pong discloses “transmitting
`a probe from a first one of the processing nodes only to a probe filtering
`unit, the probe corresponding to a memory line” and “transmitting the probe
`from the probe filtering unit only to the selected ones of the processing
`nodes,” as recited in claim 25. Ex. 1001, 32:45–57; Pet. 38–42.
`In particular, we are persuaded that Pong’s read requests are
`equivalent to the recited “probes” and its memory controller is equivalent to
`the recited “probe filtering unit.” Specifically, Pong’s memory controller
`
`
`
`17
`
`
`
`IPR2015-00159
`Patent 7,296,121 B2
`
`(“probe filtering unit”) receives a read request, or a “request for a block of
`data,” from a requesting processor (“processing node”). Ex. 1003 ¶ 32; see
`id. ¶¶ 24, 43. The memory controller “target[s] the request to a specific
`processor or set of processors known to have a copy of the requested block”
`(“selected ones of the processing nodes”). Id. ¶ 32; see id. ¶¶ 56–57.
`Specifically, the directory in the memory controller “filters the request” by
`determining “which processors have a copy of the data block of interest[]
`and forward[ing] the request” to the appropriate processors. Id. ¶¶ 56–57;
`see id. ¶¶ 33, 35. Further, at this stage of the proceeding, we agree with
`Petitioner that the requesting processor receives a response to the request as
`part of a cache coherence protocol—thereby bringing a read request within
`the meaning of the claim term “probe.” See id. ¶¶ 24, 33, 41–43; see, e.g.,
`Pet. 25–26, Ex. 1014 ¶ A-8.
`We do not find persuasive Patent Owner’s arguments to the contrary.
`Patent Owner argues that paragraph 47 of Pong “makes clear that read
`requests are filtered not by the memory controller—which Petitioners argue
`is the ‘probe filtering unit’—but rather by the requesting processors
`themselves.” Prelim. Resp. 31–32. Thus, according to Patent Owner, read
`requests do not disclose “probes” filtered by the “probe filtering unit.” Id.
`Paragraph 47 of Pong explains that “state information can be extended
`to include the ID of the processor that currently has a particular data block”
`and that “[t]his ID can be used to target a processor” in a read request.
`Ex. 1003 ¶ 47 (emphases added). In particular, “[u]sing the processor ID
`associated with the requested data block, the requesting processor
`specifically addresses the read request to the processor that has the valid
`copy.” Id. By using the language “can be,” Pong makes clear that extending
`
`
`
`18
`
`
`
`IPR2015-00159
`Patent 7,296,121 B2
`
`state information to include a processor ID is an optional addition to the state
`information. On this record, we are not persuaded that this optional feature,
`which allows the requesting processor to target its requests to a specific
`processor, impacts Pong’s other disclosures, addressed above, that the
`memory controller receives and filters requests. See id. ¶¶ 32, 56–57.
`Because we are persuaded that Petitioner has put forward adequate
`evidence that Pong’s read requests correspond to the recited “probes”
`filtered by the “probe filtering unit,” we do not address the parties’
`arguments directed to whether write requests constitute “probes.”
`ii. “probe filtering information”
`Petitioner argues that—with either the write update protocol or the
`
`write invalidation protocol implemented—Pong’s presence bit vector is
`equivalent to the “probe filtering information” “representative of states
`associated with selected ones of the cache memories,” as recited in claims 1,
`16, and 25. Pet. 26–27, 36–37, 40–42. Petitioner relies on testimony from
`Dr. Horst, opining that—for both the write update protocol and the write
`invalidation protocol—a set bit in the presence bit vector indicates not only
`that the corresponding processor has a copy of the data but also that the copy
`is valid. Id. at 26 (citing Ex. 1014 ¶¶ A-10–A-13); Ex. 1014 ¶¶ A-10–A-13.
`In other words, according to Petitioner, the presence bit vector indicates
`states of both presence and validity of data blocks in the cache of processors.
`See, e
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