APPLE 1033
`Apple et al. v. Memory Integrity
`IPR2015-00159
`
`1
`
`
`Apple et al. v. Memory Integrity
`IPR2015-00159
`
`1
`
`
`
`schallenged ‘121 Patent ............................. ..3
`
`9» Claim Constructions .................................... ..6
`
`s Pong (Claims 1-3, 8, 11, and 15—25)...............24
`
`9 Koster (Claims 4-6, 11, 12, and 19-24) ......... ..56
`
`2
`
`
`
`The ’121 Patent
`
`‘The
`resent ilwcntion cnerall
`relates to_
`Mon:
`5
`ificallv.
`the
`present invention provides techniques ib
`_in a multiple pmcessor system.
`
`Figure 18
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`’121 Patent, FIG 18.
`IPR2015-00159, Paper No. 6, Petition at 19.
`
`3
`
`
`
`The ’121 Patent: Claim 1
`
`1. A computer system comprising a plurality of
`processing nodes interconnected by a first point-to-point
`architecture, each processing node having a cache
`memory associated therewith, the computer system
`further comprising a probe filtering unit which is operable
`to receive probes corresponding to memory lines from
`the processing nodes and to transmit the probes only to
`selected ones of the processing nodes with reference to
`probe filtering information representative of states
`associated with selected ones of the cache memories.
`
`’121 Patent, Claim 1.
`
`IPR2015-00159, Paper No. 6,
`Petition at 23.
`
`4
`
`4
`
`
`
`Q» Challenged ‘121 Patent ............................... ..3
`
`Q Claim Constructions .................................. ..6
`
`92 ‘‘States’’
`
`0 “Programmed”
`
`o Pong (Claims 1-3, 8, 11, and 15—25)...............24
`
`o Koster (Claims 4-6, 11, 12, and 19-24) ......... ..56
`
`5
`
`
`
`The Claimed “States”
`
`probe filtering information representative of states
`associated with selected ones of the cache memories.
`
`with reference to
`
`’121 Patent, Claim 1.
`
`IPR2015-00159, Paper No. 6,
`Petition at 23.
`
`6
`
`6
`
`
`
`The Claimed “States”
`
`probe filtering information representative of states
`associated with selected ones of the cache memories.
`
`5121 Patent, Claim 1.
`
`(From Institution Decision)
`
`Patent Owner Construction
`
`Applied by Petitioner
`
`“the term is not limited to cache
`coherence protocol states and is
`broad enough to include the condition
`of presence—i.e., what is stored in
`cache memory”
`
`IPR2015-00159, Paper No. 12,
`Institution Decision at 10.
`
`“cache coherency states, and .
`mere presence is not a ‘state.”’
`
`.
`
`.
`
`lPR2015-00159, Paper No. 25,
`PO Response at 11.
`
`7
`
`
`
`The Claimed “States”
`
`o Intrinsic Evidence
`
`o No intrinsic evidence to support MI’s construction
`o No express disclaimer. See |PR2015-00159, Institution
`
`Decision at 9 (citing ‘121 Patent at 14:30-36).
`
`o Extrinsic Evidence
`
`o Microsoft Computer Dictionary cited in Institution
`Decision. See Institution Decision at 10.
`
`o Chaiken cited in Petition. See Petition at 10.
`
`o Webster’s Dictionary cited in Petition. See Petition at 9.
`
`8
`
`
`
`The Claimed States “States”:
`
`Intrinsic Evidence — Does not Support M|’s Construction
`
`
`
`associated with a selected set of memory lines. In one
`example, the coherence directory 701 includes fig]; infor-
`mation 713, dirty data owner information 715, and an
`
`
`occupancy vector ‘/17 associated with
`711.
`In some embodiments, the
`are modified,
`owned, shared, and invalid.
`
`ciated with them. By contrast, because the cache coherence
`directory provides information about where-
`are cached as well as their states, probes only need be
`directed toward the clusters in which the requested-
`-is cached. The state of a particular cached line will
`
`
`
`
`
`States of “cache Memories”
`
`transmit the probes only to selected ones of the processing
`nodes with reference to probe filtering information repre-
`sentative of_se1ected ones of-
`
`
`
`‘121 Patent (Ex. 1001), Claim 1.
`
`iPR2015-00159, Paper No. 35, Petitioner Reply at 2-3.
`9
`
`9
`
`
`
`The Claimed “States” Intrinsic Evidence — Does not Support MI’s Construction
`
`Intrinsic Evidence Identified in POPR (FIGS. 7 & 8)
`“Inn-'alid." “Sl1a1'ed."‘ “On-'11ed." “Modified." Ex. 1001. Figs. 7. 8. Additionally,.{
`
` furt11er demonstrate that the relex-‘ant “states" are
`
`cache colierence protocol states. Ex. 1001 at_ Notably. Petitioners
`IPR2015-00159, Paper No. 11, Preliminary Response at 15.
`
`—are strongly illustratix-‘e that the ’ 121 Patent uses “state” to
`
`mean cache coherence protocol states.
`
`In particular. in describing Figure 7, the
`
`Paper No.
`
`Patent Owner iiesponse at 6.
`
`FIG. 7 8: 3 Not Limiting
`
`any particular cache coherence p1*otocol’s set of states).” Id. at 15. -
` which show similar states in diagram
`form Id
`_‘particular implernentations may use a different set of
`
`states” and “[t]l1e techniques of the present inx-'ention can be used with a
`
`variety of different possible memory line states.” Ex. 1001. 14:30-36. We,
`
`IPR2015-00159, Paper No. 18, Institution Decision at 9.
`
`10
`
`10
`
`
`
`The Claimed “States”: Intrinsic Evidence - No Express Disclaimer
`
`“[T]he PTO should only limit the claim based on the
`specification or prosecution history when those sources
`expressly disclaim the broader definition.”
`
`in re Bigio, 381 F.3d 1320, 1325 (Fed. Cir. 2004)
`lPR2015-00159, Paper No. 35, Petitioner Reply at 2.
`
`11
`
`11
`
`
`
`The Claimed “States”:
`
`Extrinsic - Supports Board’s Construction
`
`
`
`Construction of “States” Applied by Petitioner
`(From Institution Decision)
`
`“the term is not limited to cache coherence protocol states and is broad enough
`to include the condition of presence—i.e., what is stored in cache memory”
`
`IPR2015-D0159, Paper No. 12,
`Institution Decision at 10.
`
`Microsoft Computer Dictionary
`(Ex. 3001) at 497-98.
`
`
` ap directories. The full-map
`statu n. The condition at a particular time of any of
`numerous elements of computing-—a device. a communi-
`P"°t°c°1 '1
`cations channel, a network station, a program, a bit, or
`
`_
`_
`_
`directory entnes w
`
`
`
`
`_
`
`other elementmused to report on or to controi computer
`
`operations.
`
`Microsoft Computer Dictionary (Ex. 3001) at 497-98.
`
`If the dirty bit is set, then one
`
`Chaiken (Ex. 1004) at 50.
`
`|PR2015-00159, Paper No. 35, Petitioner Reply at 4-5.
`
`12
`
`12
`
`12
`
`
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`Extrinsic — Even MI’s Evidence Supports Presence as State
`
`The Claimed “states”:
`
`Cornerstone of M|’s construction of “state” is their argument that “presence in a
`cache is distinct from and a pre—condition to the existence of state for that cache
`|ine.” PO Response at 7-8. Their own evidence undermines this point:
`
`but the current state of a block in dlflerent caches is different. As before if a block is
`
`not present in a cache we can assume it to be
`
`
`
`Culler Book (Ex. 20:12) at 230.
`
`°
`
`Knvalid): The block is invalid. The cache either or it contains
`a potentially stale copy that it may not read or write. In this primer, we do not distinguish
`
`between these two situations, although sometimes the former situation may be denoted as
`
`in Table 5.1. The data is presented as the number of state transitions of a particular
`
`type per 1,000 references issued by the processors. This addition hel s clarif
`
`transitions where, on a
`
`Sorin Book (Ex. 2010) at 89.
`
`Culler Book (Ex. 2011) at 307-10.
`
`lPR2015-00159, Paper No. 35, Petitioner Reply at 4-5.
`13
`
`13
`
`13
`
`
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`The Claimed “States”: Extrinsic - Supports Board’s Construction
`
`“[T]he fact that [MI] can point to definitions or usages that
`conform to their interpretation does not make the PTO’s
`definition unreasonable when the PTO can point to
`other sources that support its interpretation.”
`
`In re Morris, 12? F.3d 1048, 1056 (Fed. Cir. 1997)
`lPR2015-00159, Paper No. 35, Petitioner Reply at 4.
`
`14
`
`14
`
`
`
`The Claimed “States”: Board’s Preliminary Findings
`
`ones of the cache memories.” Instead, for pllI‘pOS€S of this decision, we are
`
`persuaded only that, 011 this record, the term is—
`_andis_
`-i.e._, what is stored in cache memory.
`
`
`|PR2015-00159, Paper No. 12,
`Institution Decision at 9-10.
`
`15
`
`15
`
`
`
`Q2 Challenged ‘121 Patent ............................... ..3
`
`~92 Claim Constructions ................................. ..6
`
`9 “States”
`
`0 “Programmed”
`
`Q Pong (Claims 1-3, 8, 11, and 15-25) ............. ..24
`
`Q Koster (Claims 4-6, 11, 12, and 19-24) ......... ..56
`
`16
`
`16
`
`
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`“Programmed”
`
`the processing nodes is programmed to complete a
`memory transaction
`
`'121 Patent, Claim 11.
`
`lPR2015-00159, Paper No. 25,
`Patent Owner Response at 11.
`17
`
`17
`
`17
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`
`
`Board’s Preliminary Findings
`
`“Programmed”
`
`Moreover, Petitioners‘ expe1t’s declaration is conclusory and does 11ot rise to the
`
`level necessary to demonstrate inherency—for example.—
`
`— Ex. 1014 at D-17 to D—l8. In contrast, the *121 Patent
`
`_to specify conditions for completion ofa memory transaction. See
`
`IPR2015-00163, Paper No. 13, Preliminary PO Response at 36.
`
`required by claim 1 1.” Id. at 35. Patent Owner seems to suggest that Koster
`
`leaves open that the microprocessor could be configured to complete
`
`memory transactions using something other than programmincr, but-
` Id at 36»
`
`IPR2015-00163, Paper No. 12, Institution Decision at 21.
`
`18
`
`18
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`
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`
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`“Programmed”
`Ml Uses Construction to Manufacture Alternative
`
`
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`MI submits that the term “progra1n1ned” should be construed to refer to a
`
`device that has been
`
`This construction
`
`|PR2015-00159, Paper No. 25, P0 Response at 13.
`
`Finally, even if the Board chooses 11ot to adopt an explicit construction for
`
`“programmed,” it should at least determine that the broadest reasonable
`
`interpretation ot“‘progra1mned”is—
`
`lPR2015-00159, Paper No. 25. PO Response at 17.
`
`19
`
`19
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`
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`Ml’s “Alternative” Inconsistent with Specification
`
`“Programmed”
`
`with IE0 devices. In cue entbedimellt, the cache coherence
`controller 230 is 3
`
`such as a fircfifinuneble legic device er a
`
`
`
`‘1 21 Patent (Ex. 1001), 7:49-52.
`lPR2015-00159, Paper No. 35, Petitioner Reply at 6.
`
`20
`
`20
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`
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`“Programmed” M|’s “Alternative” Undermined By Ml’s Expert
`
`12
`
`13
`
`14
`
`15
`
`16
`
`17
`
`18
`
`Q
`
`Are you aware of any programmable system
`
`that doesn't use a sequence of
`
`instructions?
`
`MR. SAUNDERS: Objection;
`
`form,
`
`foundation.
`
`THE WITNESS:
`
`It would be a play on words,
`
`you know. What does "programmable" mean?
`
`For
`
`example, you can say you have
`
`19 -, which is a structure that you can configure,
`
`20
`
`and
`
`21 And
`
`22
`
`23
`
`but it's really not programmable in a sense of
`
`executing a sequence of instructions.
`
`It is
`
`Probably
`probably more field programmable logic.
`
`Dr. Oklobdzija Depo. Trans. (Ex. 1026), 123:13-24.
`IPR2015-00159, Paper No. 35, Petitioner Reply at 6.
`21
`
`21
`
`21
`
`
`
`Ml’s Own Evidence Elucidates Proper Construction
`
`“Programmed”
`
`3prbgram afso iarogranime 1"!‘ -grammed or -gi-amed; -gram-ming
`or -gram-ing (I896)
`1
`a : to arran
`
`a program
`: prov: e_w|t
`__
` __
`a :
`to Insert a program or a particu ar action) Into or as if 1nto_a
`mechamsfn 15 : to controi_t_;y or as If by_z_1 program lc _ (1) : ‘to code In
`Merriam Webster’s Dictionary Cited by MI (Ex. 2014) at 931.
`
`'
`
`n1ecl1a11is111).” Ex. 2014, p. 931.
`
`I believe this definition is consistent with the
`
`tlsage of the term “p1'og1'am111ed"’ i11 the ’l2l Patent and the 1111de1‘sta11di11g of a
`
`person of ordinaiy skill in the alt. Accordillgly, I believe a reasonable
`
`iilteipretation of the te11n“p1'og1*a1m11ed” is
`
`Dr. Horst's Reply Deci. (Ex. 1025) at 11 6.
`
`lPR2015-00159, Paper No. 35, Petitioner Reply at 6.
`
`22
`
`22
`
`22
`
`
`
`o Challenged ‘121 Patent ............................... ..3
`
`o Claim Constructions ................................... ..6
`
`o Pong ...................................................... ..24
`o Overview
`
`(0 States (Claims 1-3, 8, 11, and 15-25)
`o Probes (Claims 1-3, 8, 11, and 15-25)
`o Accumulating (Claims 15, 25)
`o Programmed (Claim 11)
`
`o Koster (Claims 4-6, 11, 12, and 19-24) ........ ..56
`
`23
`
`23
`
`
`
`Pong: Overview
`
`Pong discloses—imp1ementing an
`asynchronous_ Ex. 1003. [$71.1 12. In the
`asynchronous cache coherence prcmco1._
`_ which “indicates whetliei‘ a copy of the data block is valid or
`
`invalid." Id. T 13. When a processor "propagates a read or u-‘rite request“
`
`Pong discusses an implementationo
` Id
`
`T 12: see id. 1?] 15. 29-30. Figure 2 of Pong is reproduced below.
`
`Pong also discloses the useo
`_ Id. f 51. “A directory. in this context.
` “ Id The
`directory can be implemented with a
`with one bit per
`
`processor. 10'. “When the bit corresponding to a processor is set in the bit
`
`vector. the processor has a copy ofthe data block.” Id.
`
`lPR2015-00159, Paper No. 12, Institution Decision at 14-16.
`
`24
`
`24
`
`24
`
`
`
`Pong: Overview
`processor 1
`
`
`processor 0
`
`Scheduling
`Window
`
`
`
`Cache orD1 ctory Filter
`
`‘-
`
` I
`
`410
`
`ANNOTATION A
`
`Dr. Horst Decl. (Ex. 1014), 1[1[A-6 to A-7
`IPR2015-00159, Paper No.6, Petition at 25, 40.
`25
`
`25
`
`25
`
`
`
`Pong: Overview
`
`processor 0
`
`processor 1
`
`!-LL.
`
`X
`
`-
`
`-
`=
`-
`'
`E
`Cache or Dlrectory Fill
`
`.
`
`I
`
`-'.I'.-
`
`'
`
`,
`' "" '
`
`..
`
`-
`
`_.
`
`'- -
`
`. 410
`
`s . . . . . - u . . . . - - . . . . . . . . . . . . . - . . . . . . - . u . . . . . . - - . . . - - . . . --
`
`ANNOTATION B
`
`Dr. Horst Decl. (Ex. 1014), 111] A-14 to A-15
`IPR2o15-00159, Paper No. 6, Petition at 25, 40.
`26
`
`26
`
`26
`
`
`
`Mapping of Key Features of Claims
`
`Pong
`
`1. A computer system
`comprising a plurality of
`processing nodes
`interconnected by a first
`point-to-point
`architecture, each
`processing node having a
`cache memory associated
`therewith,
`
`PR2015-00159, Paper No. 6, Petition at 23—24.
`27
`
`27
`
`
`
`' l
`
`processor 0
`
`processor 1
`
`parallel links
`
`27
`
`
`
`Mapping of Key Features of Claims
`
`Pong
`
`
`
`410
`
`, the
`
`computer system further
`comprising a probe
`filtering unit
`
`I
`
`with reference to
`
`probe filtering information
`representative of states
`associated with selected
`
`ones of the cache
`
`5 memories.
`
`IPR2015-00159, Paper NO. 6, Petition at 24-27.
`
`23
`
`28
`
`28
`
`
`
`Mapping of Key Features of Claims
`
`Pong
`
`processor 0
`
`processor 1
`
`memory COFINOIISF
`
`«mi
`.
`addhss b”5’5W“d‘
`
`Qpe;-ab|e to
`receive probes
`corresponding to memory
`lines from the processing
`nodes and to transmit the
`
`probes only to selected
`ones of the processing
`nodes
`
`ANNOTATION A
`
`
`lPR2015-00159, Paper No. 6, Petition at 24-27.
`29
`
`29
`
`29
`
`
`
`Board’s Preliminary Findings
`
`Pong
`
`3227-10.
`
`In particular, on this record, we agree that these limitations are
`
`satisfied by Pong's shared memory multiprocessor, which employs “point-
`
`to-point links” and which includes multiple processors. each with “one or
`
`more caches.” Ex. 1003 iii 30-31, Fig. 2. We, tlierefore, determine that
`
`See Prelim. Resp. 25-48. Based on our review of Petitioner’s arguments a11d
`
`evidence. we are persuaded. on this record. that Pong discloses the
`
`additional limitations ofclaim 25. Pet. 37-44. Accordingly,-
`
`lPR2015-00159, Paper No. 12, Institution Decision at 22-23.
`
`so
`
`30
`
`30
`
`
`
`c Challenged ‘121 Patent ............................... ..3
`
`9/ Claim Constructions ................................... ..6
`
`c Pong ..................................................... ..24
`49 Overview
`
`c» States (Claims 1-3, 8, 11, and 15-25)
`9 Probes (Claims 1-3, 8, 11, and 15-25)
`to Accumulating (Claims 15, 25)
`c Programmed (Claim 11)
`
`Q Koster (Claims 4-6, 11, 12, and 19-24) ........ ..56
`
`31
`
`
`
`“States” Disputes
`
`probe filtering information representative of states
`associated with selected ones of the cache memories.
`
`with reference to
`
`’121 Patent, Claim 1.
`
`Two issues:
`
`1) MI contends that proper construction is not what the
`Board found in the Institution Decision
`
`2) MI contends that Pong’s bit vector fails to meet its
`unreasonably narrow construction
`
`lPR2015-00159, Paper No. 35,
`Petitioner Reply at 1-4, 15-19.
`32
`
`32
`
`32
`
`
`
`Established Construction of Claimed “States”
`
`(1) Pong’s Presence Bit Vector Meets Previously
`
`o Applied Construction (addressed above): “ .
`enough to include the condition of presence .
`
`.
`
`. .broad
`
`o Undisputed that Pong meets applied construction:
`
`Petitioners appear to make two arguments regarding the “states”
`limitation and the Pong reference: (1) that Pong’s “presence bit vector" is
`“probe filtering information” representative of the “state” of mere
`“presence”; and (2) that the "presence bit vector” also conveys whether a
`line is in a "valid" state.
`
`As to Petitioners’ first argument, for the reasons discussed above,
`that is foreclosed by [M|’s] claim construction of state as a cache
`coherence protocol state, which does not include mere presence.
`
`lPR2015-00159, Paper No. 12, PO Response at 25.
`
`33
`
`33
`
`33
`
`
`
`(2) Pong’s Presence Bit Vector Represents Two-State
`
`Protocol Based on Validity
`rotocols: write invalidate and Also, while the above discussion refers to a
`
`[0069] The discussion above refers to two types of cache
`coherence
`
`Pong (Ex. 1004) at'1foos9.
`
`Pong (Ex. 10:34) at 1] (1051.
`
`A-11. specifica11y.
`
` In other words-
`
`eveiy time a processor vrrites an update to a ntemory line. the directoty filter
`
`receives notice of tl1e update a11d sends a copy of the updated 111811101’)! line to each
`
`of the other pI'OC€SS01‘S it deteimiues are storing a copy of the metuory line. See
`
`
`
`Dr. Horst’s Original Dec (Ex. 1014) at1| A-11.
`
`lPR2015-D0159, Paper No. 8, Petition at 40-41.
`34
`
`34
`
`34
`
`
`
`(2) Ml’s Expert and Board Agree That Pong’s Presence Bit Vector Represents Validity
`
`states associated with selected ones of the cache nlernoiies.“ The memoly
`
`controller of Pong cannot selectively filter a11d forward “probes“ to various
`
`processors based on validity in a write update protocol because-
`
`Dr. Ok|obdzija’s Decl. (Ex. 2016) at 1] 90.
`
`Mm-met/._
`
`— Pong explains that the write update protocol
`
`“updates all of the cached copies of a data block when it is modified in a
`
`write operation.” Ex. 1003 T 48; see e.g.. Pet. 26 (citing Ex. 1003 fl 48);
`
`Ex. 1014 ‘n A-10 (citing Ex. 1003 ‘n 48).—
`
` Ex 1014
`
`fl A-1 1. We do not agree with Pate11t Owner that this testimony relies
`
`IPR2015-00159, Paper No. 18, Institution Decision at 20.
`
`35
`
`35
`
`35
`
`
`
`(2) M|’s Suggestion that Pong’s Presence Bit Vector
`
`Does Not Indicate Validity ls lllogical
`
`Afterall-.
`
` as such processor caches are
`
`already known to be unable to respond to the requests and. thus.-
`
` 1
`
`Pong’s control path.
`
` i-en to optimize
`
`pe1'fon11a11ce by “lillliting traffic i11 the control path.” Ex. 1003.
`
`0045.
`
`Dr. Horst’s Reply Decl. (Ex. 1025) at 1] 22.
`
`lPR2015-00159, Paper No. 35, Petitioner Reply at 17.
`
`36
`
`36
`
`36
`
`
`
`(2) Construction of “States” M|’s Own Evidence (Sorin) Teaches that “Valid” is a State
`
`In -.1 system with only one actor (e.g., 21 single core processor without coherent DB/IA),-
` There might be two possible valid states for a cache block
`
`if there is -.1 need to distinguish blocks that are dirty. A dirty block has -.1 value that has been writ-
`
`
`
`ten more recently than other copies of this block. For example, in -.1 two—leve1 cache hierarchy with
`
`21 write—back L1 cache, the block in the L1 may be dirty with respect to the stale copy in the L2
`
`cache.
`
`
`
` as in Section 6-3, but
`Sorin Book (Ex. 2010) at 89.
`
`
`
`IPR2015—00159, Paper No. 35,
`Petitioner Reply at 17-18.
`37
`
`37
`
`37
`
`
`
`Pong Further Teaches Related “Evaluating” Limitation
`
`evaluating the probe with the probe filtering unit to
`determine whether a valid copy of the memory line is in
`any of the cache memoriesr
`o
`o
`
`’121 Patent, Claim 25.
`
`IPR2015-00159, Paper No. 6,
`Petition at 40-41.
`
`33
`
`38
`
`38
`
`
`
`o Challenged ‘121 Patent ............................... ..3
`
`o Claim Constructions ................................... ..6
`
`o Pong ..................................................... ..24
`o Overview
`
`(0 States (Claims 1-3, 8, 11, and 15-25)
`o Probes (Claims 1-3, 8, 11, and 15-25)
`o Accumulating (Claims 15, 25)
`o Programmed (Claim 11)
`
`o Koster (Claims 4-6, 11, 12, and 19-24) ........ ..56
`
`39
`
`39
`
`
`
`Pong Teaches Claimed “Probes”
`
`c
`operable
`to receive Qrobes corresponding to memory lines from
`the processing nodes and to transmit the probes only to
`selected ones of the processing nodes
`i
`s
`s
`so
`
`’121 Patent, Claim 1.
`
`IPR2015-00159, Paper No. 6,
`Petition at 23.
`
`40
`
`40
`
`40
`
`
`
`“Probes” Dispute
`
`o Undisputed: Construction of “probes”
`
`Construction of “Probes”
`
`“[a] mechanism for eliciting a response from a
`node to maintain cache coherency in a system.”
`
`c Disputed: Pong’s read requests satisfy construction
`of “probes”
`
`lPR2015-00159, Paper No. 35, Petitioner Reply at 19-21.
`
`41
`
`41
`
`
`
`Cache Coherent System
`
`Pong Teaches Claimed “Probes”:
`
`[0001] The
`
`Pong (Ex. 1003) at 1] 0001'.
`
`eessors have a copy of a data block. One way to implement
`the directory is with a presence bit vector. Each rocessor
`has a bit in the presence bit vector for a data block.“
`
`
`
`Pong (Ex. 1003) at 1] 0051.
`
`
`
`
`
`integrated into the memory controller. The-
`e.
`., 402,
`
`404) in the memory controller,
`
`
`the s11oopQ(s) (e.g., 406, 408) corresponding to
`via the address bus 410. In addition, the
`
`
`
`Pong (Ex. was) at 1] 0057.
`
`IPR2015-00159, Paper No. 35, Petitioner Reply at 19-20.
`
`42
`
`42
`
`42
`
`
`
`Pong Teaches Claimed “Probes”: Request Elicits Two Responses To Maintain Coherence (1/2)
`
`co11e1‘ence p1'otoco1s.”). -themadi-ns1q;1esiis:»a1re3dasignotf-zto:'iél%isit»oaeihe ‘
`
`.§$.Blfgii_:i‘éZqt-i:i;§,|Qi§§3_.;§f'j'thi3
`
`See, e.g., Ex. 1028, pp. 276-77. ,
`
`Dr. Horst’:-: Repiy Decl. (Ex. 1025) at 11 28.
`lPR2015—00159, Petitioner Reply (Paper No. 35) at 20.
`
`processor 0
`
`
`processor 1
`
`
`
` .~\I\'NOT.~\TIO;\I B
`Dr. Horst Decl. (Ex. 1014), 111] A-14 to A-15
`|PR2015-00159, Paper No. 6, Petition at 25, 40.
`
`43
`
`43
`
`43
`
`
`
`Pong Teaches Claimed “Probes”: Request Elicits Two Responses To Maintain Coherence (2/2)
`
`:read requmsts -also elicit a re.'sp0ns-e (to: ma'inta!in—cach'e_._c’ohere11cy)_.ftom-the
`
`III.eII;1'O1_'.y eont'1'Ol'11e1‘-nO.de',..
`
`forwards the request to other processors and
`
`.u.-tes;i'ts; 1'-esence lbiti-vector direct
`
`
`;. Ex. 1003. fi 0057. Thus, Po11g‘s cache-
`
`Dr. Horst’s Reply Decl. (Ex. 1025) at1| 28.
`
`the control path as explained in the next section.” Ex. 1003,
`
`0049. In other
`
`Wm-ds,
`
`— Thus-
`
` r~ for example»
`
`ensuring that write invalidations are forwarded to the proper processors. Because
`fir. Horst's liepty fiecl. (Ex.
`at 1i 30.
`
`IPR2015-00159, Paper No. 35, Petitioner Reply at 20.
`
`44
`
`44
`
`44
`
`
`
`o Challenged ‘121 Patent ............................... ..3
`
`o Claim Constructions ................................... ..6
`
`o Pong ...................................................... ..25
`o Overview
`
`(0 States (Claims 1-3, 8, 11, and 15-25)
`o Probes (Claims 1-3, 8, 11, and 15-25)
`o Accumulating (Claims 15, 25)
`o Programmed (Claim 11)
`
`o Koster (Claims 4-6, 11, 12, and 19-24) ........ ..57
`
`45
`
`45
`
`45
`
`
`
`Claimed Accumulation
`
`= operable to accumulate responses
`
`to each probe
`
`’121 Patent, Claim 15.
`
`accumulating probe responses j
`
`e ~
`
`’121 Patent, Claim 25.
`
`IPR2015-00159, Paper No. 6,
`Petition at 34-35.
`
`46
`
`46
`
`46
`
`
`
`“Accumulate” Dispute
`
`1) Disputed: Pong Teaches Multiple Responses to a
`Single Probe
`
`2) Disputed: Pong Teaches “Gathering” Responses
`
`3) Disputed: Pong Teaches Storing Multiple
`Responses “at the same time”
`
`lPR2015-00159, Paper No. 12, Institution Decision at 22-23.
`
`47
`
`47
`
`47
`
`
`
`(1) Pong Teaches Multiple Responses to a Single Probe
`
`Accumulating:
`
`integrated into the memory controller. The directory filler
`400 receives requests from the request queues ('e.g., 402,
`404) in— determines which processors
`have a copy of the data block of interest, a11d
`—via the address bus 410. In addition, the
`Peng (Ex. 1'on3)‘a'i 1| 57;",
`
`of the disclosure. See, e. g., Ex. 1003, W 0024, 0048. Thus, in the imp1e111entatio11
`
`Dr. Horst’s Reply Decl. (isx. 1025) at 1] 32.
`
`lPR2015-00163, Paper No. 35, Petitioner Reply at 22-23.
`
`48
`
`48
`
`48
`
`
`
`(1) Pong Teaches Multiple Responses to a Single Probe
`
`Accumulating:
`
`[0024] This approach avoids the need for
`
`re ort soon 3 results.
`
`FDCCSSOIS [CI
`
`—When a procmss-_;or prob-es its local cache
`and discovers that it does not have a data block requested by
`another processor,
`il sim 1
`dm 5 the re uest without
` res ondln .
`
`
`
`Pong (Ex. 1003) at 1] 24.
`
`FIG 4- In otherw'ordsa
`
`Dr. Horst’s Reply Decl. (Ex. 1025) at 1] 33.
`
`IPR2015-00163, Paper No. 35, Petitioner Reply at 22-23.
`
`49
`
`49
`
`49
`
`
`
`Accumulating: (2) Pong Teaches “Gathering”
`
`For purposes of this pr0ceedi11g, the Board should const1"ue these tem1s as
`
`This co11st111ctio11 is supported by the
`lPR2015-00159, Prelim. PO Response (Paper No. 11) at 24.
`
`0024-
`
`— Ex 1003»
`
`0043.
`
`In otherW05»-
`
`Dr. Horst's Reply Decl. (Ex. 1025) at 1] 35.
`
`lPR2015-00163, Paper No. 35, Petitioner Reply at 24.
`
`50
`
`50
`
`50
`
`
`
`(3a) Storing “At the Same Time” Not Required M|’s Implicit Construction From PO Response
`
`Accumulating:
`
`storing multiple responses “at the same time”
`
`lPR2015-00159, Paper No. 25, PO Response at 36.
`
`Unsupported By Record Evidence:
`ac-cu-mu-late \a-'k§rii-m(y)a-.]at\ vb -lat-ed; -lat-ing [L accumuldtus,
`pp. of accumula
`——-—-
`are at CUMU-
`__ LATE] vt (l5c) :
`AMASS (~ a
`
`fortune) H-' vi: -to mcrease gra ua y 111 qua£1__I_:_1t3_[ or num er
`MI’s Dictionary (Ex. 2004) at 8.
`
`Q
`
`My question was a little different.
`
`My question WaS=_
`
`A
`
`Dr. Oklobdzija’s Depo. Trans. (Ex. 1026) at 142:7-12.
`
`IPR2015-00159, Paper No. 35, Petitioner Reply at 21-24.
`51
`
`51
`
`
`
`Accumulating: (3b) Pong Teaches Storing “At the Same Time”
`
`which many lnjllions are load illstmctions. See Ex. 2024, p. 12._
`
`_that the request and response buffers described by Pong would
`
`almost always be queuing multiple requests and responses at any given time. As a
`
`1~esu1t.
`
`
`
`— as the queues would be unable to
`
`pass the illdividual responses through to the requesting processor Witllout some
`
`delay.
`
`Dr. Horst’s Reply Decl. (Ex. 1025) at 1] 37.
`
`lPR2015-00163, Paper No. 35, Petitioner Reply at 24.
`
`52
`
`52
`
`52
`
`
`
`o Challenged ‘121 Patent ............................... ..3
`
`o Claim Constructions ................................... ..6
`
`o Pong ..................................................... ..24
`o Overview
`
`(0 States (Claims 1-3, 8, 11, and 15-25)
`o Probes (Claims 1-3, 8, 11, and 15-25)
`o Accumulating (Claims 15, 25)
`Programmed (Claim 11)
`
`CO
`
`o Koster (Claims 4-6, 11, 12, and 19-24) ........ ..56
`
`53
`
`53
`
`53
`
`
`
`Pong Teaches “Programmed” Microprocessors: MI Admits that Pong “Completes” According to Claim
`
`the processing
`i
`L nodes is programmed to complete a memory transaction
`
`’121 Patent, Claim 11.
`
`111echa11is111)." Ex. 2014. p. 931.
`
`I believe this definition is collsistent with the
`
`usage of the te1111 “prog1‘a1mned" in tl1e '12 1 Patent and the m1de1'standi11g ofa
`
`person of o1‘dina1"y skill in tl1e art. Accordingly. I believe a reasonable
`
`illterpretatioli of the term “prog1'a11nned" is
`
`Dr. i-lorst;s iiegiiy Eiecfiéx. 1‘62'5jait'1i‘é.
`
`transaction after receiving a first number of responses.
`
`In’. Rather,-
`
`Id_ Thus, the mere fact that a processor executes a set of insmmtions does not
`
`IPR2015-00159, Paper No. 25, P0 Response at 33.
`
`54
`
`54
`
`
`
`92 Challenged ‘121 Patent ............................... ..3
`
`9 Claim Constructions ................................... ..6
`
`e Pong (Claims 1-3, 8, 11, and 15-25) ............ ..24
`
`e Koster................................................... ..56
`
`49 Overview
`
`e Programmed (Claim 11)
`9 States (Claims 4-6, 11, 12, and 19-24)
`Temporary Storage (Claim 12)
`
`CO
`
`55
`
`55
`
`55
`
`
`
`Koster: Overview
`
`_ Ex- 1009» title In Kostera when
`
`a microprocessor requests data that is not available i11 its local cache, it sends
`
`a request for that data to a snoop filter. Id. at abs. The snoop filter stores a
`
`copy of the tags of data stored in the local cacl1e111e1uories of each of the
`
`microprocessors» Id»—
`
`_ Id-
`
`lPR2015-00163, Paper No. 18, Institution Decision at 17.
`
`56
`
`56
`
`56
`
`
`
`Koster: Overview
`
`Koster (Ex. 1069), FIG. 9.
`
`lPR2015-00163, Paper No. 18, Institution Decision at 18.
`
`57
`
`57
`
`57
`
`
`
`Mapping of Key Features of Claims
`
`Koster
`
`1. A computer system
`comprising a plurality of
`processing nodes
`interconnected by a first
`point-to-point
`architecture, each
`
`processing node having a
`cache memory associated
`therewith,
`
`Microprocessor
`
`Koster (Ex. 1009), FIG. 9.
`
`lPR2015-00163, Paper No. 1, Petition at 26-27.
`53
`
`58
`
`58
`
`
`
`Mapping of Key Features of Claims
`
`Koster
`
`Shadow Tag
`Memory
`1.95.
`
`, the
`computer system further
`comprising a probe
`filtering unit
`
`Koster (Ex. 10:19), FIG. 9.
`
`with reference to
`
`probe filtering information
`representative of states
`associated with selected
`
`ones of the cache
`
`memories
`
`lPR2015-00163, Paper No. 1, Petition at 27-29.
`59
`
`59
`
`59
`
`
`
`Koster Mapping of Key Features of Claims
`
`Microprocessor
`
`Microprocessor
`
`,
`
`SW09 Filler
`Shadomag
`Memory
`
`.
`
`-
`
`Microprocessor
`
`Microprocessor
`
`Koster (Ex. 1009), FIG. 9.
`
`operable to
`receive prohes
`corresponding to memory
`lines from the processing
`nodes and to transmit the
`
`probes only to selected
`ones of the processing
`nodes
`
`lPR2015-00163, Paper No. 1, Petition at 27-29.
`on
`
`60
`
`60
`
`
`
`92 Challenged ‘121 Patent ............................... ..3
`
`9 Claim Constructions ................................... ..6
`
`e Pong (Claims 1-3, 8, 11, and 15-25) ............. ..24
`
`e Koster.................................................... ..56
`
`49 Overview
`
`49 Programmed (Claim 11)
`9 States (Claims 4-6, 11, 12, and 19-24)
`Temporary Storage (Claim 12)
`
`CO
`
`61
`
`
`
`Koster Teaches “Programmed” Microprocessors: Ml Admits that Koster “Completes” According to Claim
`
`the processing
`nodes is programmed to complete a memory transaction
`
`’?I21 Patent, claim 11.
`
`111echa11is111)." Ex. 2014. p. 931.
`
`I believe this definition is collsistent with the
`
`usage of the te1111 “prog1‘a1mned" in tl1e '12 1 Patent and the m1de1'standi11g ofa
`
`person of o1‘dina1"y skill in the art. Accordingly. I believe a reasonable
`
`illterpretatioli of the term “prog1'a11nned" is
`
`or. Horst's Reply Declaration (Ex. 1ti2.;E_;)_at1lt5.
`
`a me111o1‘y transaction after receiving a first number of responses. Id. Rather.-I
`
`Id. Thus, the mere fact that a p1'ocesso1'executes a set of illstmctions does not
`
`lPR2D15-00163, Paper No. 31, P0 Response at 29.
`
`62
`
`62
`
`
`
`92 Challenged ‘121 Patent ............................... ..3
`
`9 Claim Constructions ................................... ..6
`
`e Pong (Claims 1-3, 8, 11, and 15-25) ............. ..25
`
`e Koster.................................................... ..57
`
`49 Overview
`
`e Programmed (Claim 11)
`e States (Claims 4-6, 11, 12, and 19-24)
`Temporary Storage (Claim 12)
`
`CO
`
`63
`
`63
`
`63
`
`
`
`“States” Disputes
`
`_-
`
`._
`
`T
`
`probe filtering information representative of states
`associated with selected ones of the cache memories.
`
`with reference to
`
`’121 Patent, Claim 1.
`
`Two issues:
`
`1) MI contends that proper construction is not what the
`Board found in the Institution Decision
`
`2) MI contends that Koster’s ‘‘local state memory” fails
`to meet its unreasonably narrow construction
`
`lPR2015-00163, Paper No. 40,
`Petitioner Reply at 2-5, 8-13.
`64
`
`64
`
`64
`
`
`
`(1) Koster’s “Local State Memory” Meets Previously
`
`Established Construction of Claimed “States”
`
`o Applied Construction (addressed above): “ .
`enough to include the condition of presence .
`
`.
`
`. .broad
`
`o Undisputed that Koster meets applied construction:
`
`As explained above, this term should be construed to
`refer to “cache coherency states.” Under [M|’s]
`construction, Koster’s tags do not satisfy this limitation
`because they are not representative of cache coherency
`
`states.
`
`|PR2015-00163, Paper No. 31, PO Response at 21.
`
`65
`
`65
`
`65
`
`
`
`(2a) Koster’s Tags Meet Claimed “States” For Same Rationale as Pong’s Bit Vector
`
`thereto- AI lea st partly in ofcler to deterllline whell1er'Io for-
`ward or czmcel snoopi11g-based cziuhe-mlierenue bmadcasls,
`the $1100. filler 162
`
`
`
`152. 154, 156. 158.
`
`can:-he 111emorie5} (nut shov.-'11) ufeac-h of the micnmpmc-essurs
`
`Koster (Ex. 1009) at 11 40.
`
`40.
`
`In the second case__do not merely provide the snoop
`
`filter with addresses identifying locations of copies of requested data. Instead, they
`
`— After all a person ofdrdidery skid
`
`in the ad would understandrha_
`
`Dr. Horst's Reply Decl. (Ex. 1025) at 1] 40.
`
`IPR2015-00163, Paper No. 40, Petitioner Reply at 12.
`66
`
`66
`
`66
`
`
`
`(2b) Koster Teaches Claimed “States” With Explicit Disclosure of “MOESl Cache-Coherency Protocol”
`
`In one or more etnbndimcnts of the present invention. .
`_n1ny be optimistically z11aintai11eu:l as a
`set -associative eael1e. Further, i11 o11e or more embodiments of
`the present il'l\"Bl1tiDl1, the set-associative cache-
`o
`
`Koster (Ex. 1'0'09), 6:33-38.
`
`where to send a probe." EX. 2016, 1] 50. However. a person of ordinaly skill ill the
`
`an would ulldelwnd than_
`
` Ex. 1009, 6:33-38 (empllasis added). Moreovel‘,
`
`Dr. Horst’s Reply Dec (Ex. 1025) at 1] 41.
`
`IPR2015-00163, Paper No. 40,
`Petitioner Reply at 12.
`67
`
`67
`
`67
`
`
`
`(2c) Koster Teaches Claimed States By MI’s Own Logic
`
`tlmeretn. At least partly in
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